ETC UPD65MC-XXX-5A4

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD64A, 65
4-BIT SINGLE-CHIP MICROCONTROLLERS
FOR INFRARED REMOTE CONTROL TRANSMISSION
DESCRIPTION
The µPD64A and 65 feature low-voltage 2.0 V operation, and incorporate a carrier generator for infrared remote
control transmission, a standby release function through key entry, and a programmable timer, making them ideal
for infrared remote control transmitters.
A one-time PROM product, the µPD6P5 is also available for program evaluation or small-quantity production.
FEATURES
• Program memory (ROM)
• µPD64A: 1002 × 10 bits
• µPD65:
2026 × 10 bits
• Data memory (RAM):
32 × 4 bits
• On-chip carrier generator for infrared remote control
• 9-bit programmable timer:
1 channel
• Instruction execution time:
16 µs (when operating at fX = 4 MHz: ceramic oscillation)
• Stack levels:
1 (stack RAM is also used for data memory RF)
• I/O pins (KI/O):
8
• Input pins (KI):
4
• Sense input pin (S0, S2):
2
• S1/LED pin (I/O):
1 (when in output mode, this is the remote control transmission display
pin.)
• Power supply voltage:
VDD = 2.0 to 3.6 V
• Operating ambient temperature: TA = –40 to +85°C
• Oscillation frequency:
fX = 2.4 to 8 MHz
• On-chip POC circuit
APPLICATIONS
Infrared remote control transmitters (for AV and household electric appliances)
Unless otherwise specified, the µPD65 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U14380EJ3V0DS00 (3rd edition)
Date Published December 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999
µPD64A, 65
ORDERING INFORMATION
Part Number
Package
µPD64AMC-×××-5A4
20-pin plastic SSOP (7.62 mm (300))
µPD65MC-×××-5A4
20-pin plastic SSOP (7.62 mm (300))
Remark ××× indicates ROM code suffix.
PIN CONFIGURATION (TOP VIEW)
20-Pin Plastic SSOP (7.62 mm (300))
• µPD64AMC-×××-5A4
• µPD65MC-×××-5A4
KI/O6
1
20
KI/O5
KI/O7
2
19
KI/O4
S0
3
18
KI/O3
S1/LED
4
17
KI/O2
REM
5
16
KI/O1
VDD
6
15
KI/O0
XOUT
7
14
KI3
XIN
8
13
KI2
GND
9
12
KI1
10
11
KI0
S2
Caution The pin numbers of K I and KI/O are in the reverse order of the µPD6600A and 6124A.
2
Data Sheet U14380EJ3V0DS00
µPD64A, 65
BLOCK DIAGRAM
Carrier
generator
REM
CPU
core
Port KI
4
KI0 to KI3
8
Port KI/O
8
KI/O0 to KI/O7
3
Port S
3
S0, S1/LED, S2
ROM
9-bit
timer
S1/LED
4
RAM
System
control
XIN
XOUT
VDD
GND
LIST OF FUNCTIONS
ROM capacity
µPD65
µPD64A
Item
1002 × 10 bits
µPD6P5
2026 × 10 bits
Mask ROM
One-time PROM
RAM capacity
32 × 4 bits
Stack
1 level (multiplexed with RF of RAM)
I/O pins
•
•
•
•
Number of keys
• 32
• 56 (when extended by key extension input)
Clock frequency
Ceramic oscillation
• fX = 2.4 to 8 MHz
Instruction execution time
16 µs (fX = 4 MHz)
Carrier frequency
fX/8, fX/16, fX/64, fX/96, fX /128, fX/192, no carrier (high level)
Timer
9-bit programmable timer: 1 channel
POC circuit
On chip
Supply voltage
VDD = 2.0 to 3.6 V
Key input (KI):
Key I/O (K I/O):
Key extended input (S0, S1, S 2):
Remote control transmission display output (LED):
Operating ambient temperature
T A = –40 to +85°C
Package
20-pin plastic SSOP (7.62 mm (300))
Data Sheet U14380EJ3V0DS00
4
8
3
1 (alternate function as S1 pin)
Ceramic oscillation
• fX = 2.4 to 4.8 MHz
VDD = 2.2 to 3.6 V
3
µPD64A, 65
CONTENTS
1. PIN FUNCTIONS ...............................................................................................................................
6
1.1
List of Pin Functions ...............................................................................................................................
6
1.2
Pin I/O Circuits.........................................................................................................................................
7
1.3
Recommended Connection of Unused Pins .........................................................................................
8
2. INTERNAL CPU FUNCTIONS ..........................................................................................................
9
2.1
Program Counter (PC) ............................................................................................................................
9
2.2
Stack Pointer (SP) ...................................................................................................................................
9
2.3
Address Stack Register (ASR (RF)) .......................................................................................................
9
2.4
Program Memory (ROM) ......................................................................................................................... 10
2.5
Data Memory (RAM) ................................................................................................................................ 10
2.6
Data Pointer (DP) ..................................................................................................................................... 11
2.7
Accumulator (A) ...................................................................................................................................... 11
2.8
Arithmetic and Logic Unit (ALU) ............................................................................................................ 12
2.9
Flags ......................................................................................................................................................... 12
2.9.1
Status flag (F) ............................................................................................................................... 12
2.9.2
Carry flag (CY) ............................................................................................................................. 13
3. PORT REGISTERS (PX) ................................................................................................................... 14
3.1
KI/O Port (P0) ............................................................................................................................................. 15
3.2
KI Port/Special Port (P1) ......................................................................................................................... 16
3.2.1
KI port (P11: bits 4 to 7 of P1) ....................................................................................................... 16
3.2.2
S0 port (bit 2 of P1) ....................................................................................................................... 16
3.2.3
S1/LED port (bit 3 of P1) ............................................................................................................... 16
3.2.4
S2 port (bit 1 of P1) ....................................................................................................................... 17
3.3
Control Register 0 (P3) ........................................................................................................................... 17
3.4
Control Register 1 (P4) ........................................................................................................................... 18
4. TIMER ............................................................................................................................................... 19
4.1
Timer Configuration ................................................................................................................................ 19
4.2
Timer Operation ....................................................................................................................................... 20
4.3
Carrier Output .......................................................................................................................................... 21
4.4
Software Control of Timer Output ......................................................................................................... 21
5. STANDBY FUNCTION ...................................................................................................................... 22
5.1
Outline of Standby Function .................................................................................................................. 22
5.2
Standby Mode Setting and Release ...................................................................................................... 23
5.3
Standby Mode Release Timing .............................................................................................................. 25
6. RESET ............................................................................................................................................... 26
7. POC CIRCUIT ................................................................................................................................... 27
7.1
Functions of POC Circuit ........................................................................................................................ 28
7.2
Oscillation Check at Low Supply Voltage ............................................................................................. 28
8. SYSTEM CLOCK OSCILLATOR ...................................................................................................... 29
4
Data Sheet U14380EJ3V0DS00
µPD64A, 65
9. INSTRUCTION SET .......................................................................................................................... 30
9.1
Machine Language Output by Assembler ............................................................................................. 30
9.2
Circuit Symbol Description .................................................................................................................... 31
9.3
Mnemonic to/from Machine Language (Assembler Output) Contrast Table ..................................... 32
9.4
Accumulator Operation Instructions ..................................................................................................... 36
9.5
I/O Instructions ........................................................................................................................................ 39
9.6
Data Transfer Instructions ...................................................................................................................... 40
9.7
Branch Instructions ................................................................................................................................ 42
9.8
Subroutine Instructions .......................................................................................................................... 43
9.9
Timer Operation Instructions ................................................................................................................. 44
9.10 Other Instructions ................................................................................................................................... 45
10. ASSEMBLER RESERVED WORDS ................................................................................................ 47
10.1 Mask Option Quasi Directives ............................................................................................................... 47
10.1.1 OPTION and ENDOP quasi directives ......................................................................................... 47
10.1.2 Mask option definition quasi directive .......................................................................................... 47
11. ELECTRICAL SPECIFICATIONS ..................................................................................................... 48
12. CHARACTERISTIC CURVES (REFERENCE VALUES) ................................................................. 52
13. APPLICATION CIRCUIT EXAMPLE ................................................................................................ 53
14. PACKAGE DRAWING ...................................................................................................................... 54
15. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 55
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 56
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD64A, 65 AND OTHER PRODUCTS .... 57
APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT ................................ 58
Data Sheet U14380EJ3V0DS00
5
µPD64A, 65
1. PIN FUNCTIONS
1.1 List of Pin Functions
Pin No.
Symbol
Function
Output Format
After Reset
1
2
15 to 20
KI/O0 to KI/O7
8-bit I/O port. I/O can be switched in 8-bit units.
CMOS
In input mode, a pull-down resistor is added. push-pullNote 1
In output mode, these pins can be used as key scan
outputs from the key matrix.
High-level output
3
S0
Input port.
Can also be used as a key return input from key matrix.
In input mode, use of a pull-down resistor for the S0 and
S 1 ports can be specified by software in 2-bit units.
If input mode is canceled by software, this pin is placed
in the OFF mode and enters a high-impedance state.
High impedance
(OFF mode)
4
S1/LED
I/O port.
CMOS push-pull
In input mode (S1), this pin can also be used as a key
return input from key matrix.
Use of a pull-down resistor for the S0 and S1 ports
can be specified by software in 2-bit units.
In output mode (LED), this pin becomes the remote
control transmission display output (active low).
When the remote control carrier is output from the
REM output, this pin outputs a low level from the LED
output synchronously with the REM signal.
—
High-level output
(LED)
5
REM
Infrared remote control transmission output.
The output is active high.
Carrier frequency: fX/8, f X/64, fX/96, high-level, fX/16,
fX/128, f X/192 (usable on software)
6
VDD
Power supply
—
—
7
8
XOUT
XIN
Connecting ceramic resonators for system clock.
—
Low level
(oscillation stopped)
9
GND
Ground.
—
—
10
S2
Input port.
—
Input
(high impedance,
STOP mode
release cannot be
used)
—
Input (low level)
CMOS push-pull
The use of a STOP mode release for the S2 port can be
specified by software. When using this pin as a key input
from a key matrix, enable the use of the STOP mode
release (at this time, a pull-down resistor is connected
internally.)
Low-level output
When the STOP mode release is disabled, this pin can
be used as an input port that does not release the STOP
mode even if the release condition is established
(at this time, a pull-down resistor is not connected internally.)
11 to 14
KI0 to K I3Note 2 4-bit input port.
These pins can be used as key return inputs from the key
matrix.
Use of a pull-down resistor can be specified by software
in 4-bit units.
Notes 1. Be aware that the drive capability of the low-level output side is held low.
2. In order to prevent malfunction, do not input a high level to all the KI0 to KI3 pins when POC is released
due to supply voltage startup (these pins can be left open. When leaving open, keep pull-down
resistors connected).
6
Data Sheet U14380EJ3V0DS00
µPD64A, 65
1.2 Pin I/O Circuits
The I/O circuits of the µPD64A and 65 pins are shown in partially simplified forms below.
(1) K I/O0 to K I/O7
(4) S 0
VDD
Input buffer
Data
Output
latch
P-ch
OFF mode
N-chNote
Output
disable
Selector
Standby
release
N-ch
Pull-down flag
Input buffer
N-ch
(5) S1/LED
VDD
Note The drive capability is held low.
REM
output latch
(2) K I0 to K I3
Standby
release
P-ch
Output
disable
Input buffer
N-ch
Standby
release
Input buffer
Pull-down flag
N-ch
N-ch
Pull-down flag
(3) REM
(6) S 2
Standby
release
VDD
Input buffer
P-ch
Data
Output
latch
N-ch
STOP release
ON/OFF
N-ch
Carrier
generator
Data Sheet U14380EJ3V0DS00
7
µPD64A, 65
1.3 Recommended Connection of Unused Pins
The following connections are recommended for unused pins.
Table 1-1. Recommended Connection of Unused Pins
Connection
Pin
Inside Microcontroller
KI/O
Input mode
Output mode
REM
—
Outside Microcontroller
Leave open
High-level output
—
S1/LED
Output mode (LED) setting
S0
OFF mode setting
S2
—
KI
—
Directly connect to GND
Caution The I/O mode and the pin output level are recommended to be fixed by setting them
repeatedly in each loop of the program.
8
Data Sheet U14380EJ3V0DS00
µPD64A, 65
2. INTERNAL CPU FUNCTIONS
2.1 Program Counter (PC): 11 Bits
This is a binary counter that holds the address information of the program memory.
Figure 2-1. Program Counter Configuration
PC
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
The program counter contains the address of the instruction that should be executed next. Normally, the counter
contents are automatically incremented in accordance with the instruction length (byte count) each time an
instruction is executed.
However, when executing jump instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump
destination address written in the operand.
When executing the subroutine call instruction (CALL), the call destination address written in the operand is
entered in the PC after the PC contents at the time are saved to the address stack register (ASR). If the return
instruction (RET) is executed after the CALL instruction is executed, the address saved to the ASR is restored to
the PC.
After reset, the value of the program counter becomes “000H”.
2.2 Stack Pointer (SP): 1 Bit
This is a 1-bit register that holds the status of the address stack register.
The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented
when the return instruction (RET) is executed.
After reset, the stack pointer contents are cleared to “0”.
When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up, causing a system
reset signal to be generated and the PC to be cleared to “000H”.
As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer
by means of a program.
2.3 Address Stack Register (ASR (RF)): 11 Bits
The address stack register saves the return address of the program after a subroutine call instruction is executed.
The lower 8 bits are allocated to the RF of the data memory as a dual-function RAM. The register holds the
ASR value even after the RET is executed.
After reset, it holds the previous data (undefined when turning on the power).
Caution If the RF is accessed as the data memory, the higher 3 bits of the ASR become undefined.
Figure 2-2.
Address Stack Register Configuration
RF
ASR
ASR10
ASR9
ASR8
ASR7
ASR6
ASR5
ASR4
Data Sheet U14380EJ3V0DS00
ASR3
ASR2
ASR1
ASR0
9
µPD64A, 65
2.4 Program Memory (ROM): 1002 steps × 10 bits ( µ PD64A)
2026 steps × 10 bits ( µ PD65)
The ROM consists of 10 bits per step, and is addressed by the program counter.
The program memory stores programs and table data, etc.
The 22 steps from 7EAH to 7FFH cannot be used in the test program area.
Figure 2-3.
Program Memory Map
(a) µ PD64A
(b) µ PD65
10 bits
10 bits
000H
000H
Page 0
Page 0
3E9H
3EAH
3FFH
400H
Unmounted areaNote
Page 1
7E9H
7EAH
7E9H
7EAH
Test program areaNote
7FFH
Test program areaNote
7FFH
Note The unmounted area and test program area are designed so that a program or data placed in either of
them by mistake is returned to the 000H address.
2.5 Data Memory (RAM): 32 × 4 Bits
The data memory, which is a static RAM consisting of 32 × 4 bits, is used to hold processed data. The data
memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer.
RF is also used as the ASR.
After reset, R0 is cleared to “00H” and R1 to RF hold the previous data (undefined when turning on the power).
10
Data Sheet U14380EJ3V0DS00
µPD64A, 65
↓
R1n (Higher 4 bits) R0n (Lower 4 bits)
R0
R10
R00
R1
R11
R01
R2
R12
R02
R3
R13
R03
R4
R14
R04
R5
R15
R05
R6
R16
R06
R7
R17
R07
R8
R18
R08
R9
R19
R09
RA
R1A
R0A
RB
R1B
R0B
RC
R1C
R0C
RD
R1D
R0D
RE
R1E
R0E
RF
R1F
R0F
DP (refer to 2.6 Data Pointer (DP))
↓
Figure 2-4. Data Memory Configuration
ASR (refer to 2.3 Address Stack Register (ASR (RF)))
2.6 Data Pointer (DP): 11 Bits
The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents.
The lower 8 bits of the ROM address are specified by R0 of the data memory; and the higher 3 bits by bits 4,
5, and 6 of the P3 register (CR0).
After reset, the pointer contents become “000H”.
Figure 2-5. Data Pointer Configuration
P3 register
b6
P3
Note
DP10
b5
b4
DP9
DP8
R10
DP7
DP6
R00
DP5
DP4
DP3
DP2
DP1
DP0
R0
Note Set DP10 of the µPD64A to 0.
2.7 Accumulator (A): 4 Bits
The accumulator, which is a register consisting of 4 bits, plays a leading role in performing various operations.
After reset, the accumulator contents are left undefined.
Figure 2-6. Accumulator Configuration
A3
A2
A1
A0
A
Data Sheet U14380EJ3V0DS00
11
µPD64A, 65
2.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which is an arithmetic circuit consisting of 4 bits, executes simple
manipulations with priority given to logical operations.
2.9 Flags
2.9.1 Status flag (F)
Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.
The status flag is set (1) in the following cases.
• If the condition specified with the operand is met when the STTS instruction has been executed.
• When standby mode is released.
• When the release condition is met at the point of executing the HALT instruction. (In this case, the system
does not enter standby mode.)
Conversely, the status flag is cleared (0) in the following cases.
• If the condition specified with the operand is not met when the STTS instruction has been executed.
• While the status flag is set (1), the HALT instruction is executed, but the release condition is not met at the
point of executing the HALT instruction. (In this case, the system does not enter standby mode.)
Table 2-1. Conditions for Status Flag (F) to Be Set by STTS Instruction
Operand Value of STTS Instruction
Condition for Status Flag (F) to Be Set
b3
b2
b1
b0
0
0
0
0
High level is input to at least one of the KI pins.
0
1
1
High level is input to at least one of the KI pins.
1
1
0
High level is input to at least one of the KI pins.
1
0
1
The down counter of the timer is 0.
1
Any combination
of b2, b 1, and b0 above
[The following condition is added in addition to the above.]
High level is input to at least one of the S 0Note 1, S 1Note 1, and S2Note 2 pins.
Notes 1. The S0 and S1 pins must be set to input mode (bit 2 of the P4 register is set to 0 and bit 0 to 1).
2. The use of STOP mode release for the S2 pin must be enabled (bit 3 of the P4 register is set to 1).
12
Data Sheet U14380EJ3V0DS00
µPD64A, 65
2.9.2 Carry flag (CY)
The carry flag is set (1) in the following cases.
• If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is “1” and bit 3 of the
operand is “1”.
• If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is “1”.
• If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH.
The carry flag is cleared (0) in the following cases.
• If the ANL instruction or the XRL instruction is executed when either bit 3 of the accumulator or bit 3 of the
operand (or both) is “0”.
• If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is “0”.
• If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH.
• If the ORL instruction is executed.
• When data is written to the accumulator by the MOV instruction or the IN instruction.
Data Sheet U14380EJ3V0DS00
13
µPD64A, 65
3. PORT REGISTERS (PX)
The KI/O port, the KI port, the special ports (S0, S1/LED, S2), and the control registers are treated as port registers.
Port register values after reset are shown below.
Figure 3-1. Port Register Configuration
Port register
After reset
P0
FFH
P10
KI/O7
P00
KI/O5
KI/O6
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
×FHNote
P1
P11
KI3
KI2
P01
KI1
KI0
S1/LED
S0
S2
1
P3 (control register 0)
03H
P13
0
P03
DP9
DP10
DP8
TCTL
CARY
MOD1
MOD0
P4 (control register 1)
P14
0
Note
0
26H
P04
KI
S0/S1
S2
S1/LED mode KI/O mode
pull-down pull-down STOP release
S0 mode
×: Value based on the KI pin state
Table 3-1. Relationship Between Ports and Read/Write
Input Mode
Port Name
Read
Output Mode
Write
Read
Write
KI/O
Pin state
Output latch
Output latch
Output latch
KI
Pin state
—
S0
Pin state
—
Note
Pin state
S1/LED
Pin state
—
S2
Pin state
—
—
—
Note When in OFF mode, “1” is always read.
14
—
—
Data Sheet U14380EJ3V0DS00
—
—
µPD64A, 65
3.1 K I/O Port (P0)
The KI/O port is an 8-bit I/O port for key scan output.
Input/output mode is set by bit 1 of the P4 register.
If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can
be read in output mode.
If a write instruction is executed, data can be written to the output latch regardless of input or output mode.
After reset, the port enters output mode, and the value of the output latch (P0) becomes 1111 1111B.
The KI/O port includes a pull-down resistor, which functions in input mode only.
Caution Because during double pressing of a key, a high-level output and a low-level output may conflict
with each other at the KI/O port, the low-level output current of the KI/O port is held low. Therefore,
be careful when using the KI/O port for purposes other than key scan output.
The KI/O port is designed so that, even when connected directly to VDD within the normal supply
voltage range (VDD = 2.0 to 3.6 V), no problem may occur.
Table 3-2. KI/O Port (P0)
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Name
KI/O7
KI/O6
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
b0 to b7: When reading: In input mode, state of the KI/O pin is read.
In output mode, the KI/O pin’s output latch contents are read.
When writing:
Data is written to the KI/O pin’s output latch regardless of input or output mode.
Data Sheet U14380EJ3V0DS00
15
µPD64A, 65
3.2 K I Port/Special Port (P1)
3.2.1 K I port (P 11: bits 4 to 7 of P1)
The KI port is a 4-bit input port for key entry.
The pin state can be read.
Use of a pull-down resistor for the KI port can be specified in 4-bit units by software using bit 5 of the P4 register.
After reset, a pull-down resistor is connected.
Table 3-3. KI/Special Port Register (P1)
Bit
b7
b6
b5
b4
b3
b2
b1
Name
KI3
KI2
KI1
KI0
S1/LED
S0
S2
b1 :
The state of the S2 pin is read (read only).
b2 :
In input mode, the state of the S0 pin is read (read only).
b0
Fixed to “1”
In OFF mode, this bit is fixed to 1.
b3 :
The state of the S1/LED pin is read regardless of input/output mode (read only).
b4 to b7: The state of the KI pin is read (read only).
Caution In order to prevent malfunction, do not input a high level to all the KI0 to KI3 pins when POC is
released due to supply voltage startup (these pins can be left open. When leaving open, keep
pull-down resistors connected).
3.2.2 S 0 port (bit 2 of P1)
The S0 port is an input/OFF mode port.
The pin state can be read by setting this port to input mode with bit 0 of the P4 register.
In input mode, use of a pull-down resistor for the S0 and S1/LED ports can be specified in 2-bit units by software
using bit 4 of the P4 register.
If input mode is released (thus set to OFF mode), the pin becomes high impedance but through current does
not flow internally. In OFF mode, “1” can be read regardless of the pin state.
After reset, this port is set to OFF mode, thus becoming high impedance.
3.2.3 S 1/LED port (bit 3 of P1)
The S1/LED port is an I/O port.
Bit 2 of the P4 register can be used to set input or output mode. The pin state can be read in both input mode
and output mode.
In input mode, use of a pull-down resistor for the S 0 and S 1/LED ports can be specified in 2-bit units by software
using bit 4 of the P4 register.
In output mode, the pull-down resistor is automatically disconnected, and this pin becomes the remote control
transmission display pin (refer to 4. TIMER).
After reset, this port enters output mode, and a high level is output.
16
Data Sheet U14380EJ3V0DS00
µPD64A, 65
3.2.4 S 2 port (bit 1 of P1)
The S2 port is an input port.
Use of a STOP mode release for the S2 port can be specified by bit 3 of the P4 register.
When using this port as a key input from a key matrix, enable the use of the STOP mode release (bit 3 of P4
register is set to 1) (at this time, a pull-down resistor is connected internally). When the STOP mode release is
disabled (bit 3 of P4 register is set to 0), this port can be used as an input port that does not release the STOP
mode even if the release condition is established (at this time, a pull-down resistor is not connected internally).
The state of the pin can be read in both cases.
After reset, the pin is set to input mode in which the STOP mode release is disabled, and enters a high-impedance
state.
3.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.
After reset, the register becomes 0000 0011B.
Table 3-4. Control Register 0 (P3)
Bit
b7
Name
b6
—
b5
b4
DP (Data Pointer)
DP10 Note
DP9
b3
b2
b1
b0
TCTL
CARY
MOD1
MOD0
Refer to Table 3-5.
DP8
Set
0
Fixed
0
0
0
1/1
ON
value
1
to “0”
1
1
1
1/2
OFF
0
0
0
0
0
0
After reset
1
1
b0, b1: These bits specify the carrier frequency and duty ratio of the REM output.
b2 :
This bit specifies the availability of the carrier of the frequency specified by b0 and b1.
b3 :
This bit changes the carrier frequency and the timer clock’s frequency division ratio.
“0” = ON (with carrier); “1” = OFF (without carrier; high level)
“0” = 1/1 (carrier frequency: The specified value of b0 and b1; timer clock: fX/64)
“1” = 1/2 (carrier frequency: Half of the specified value of b0 and b1; timer clock: fX/128)
Table 3-5. Timer Clock and Carrier Frequency Settings
b3
0
1
b2
0
b1
b0
Timer Clock
fX/64
Carrier Frequency (Duty Ratio)
0
0
fX/8 (Duty 1/2)
0
1
fX/64 (Duty 1/2)
1
0
fX/96 (Duty 1/2)
1
1
fX/96 (Duty 1/3)
1
×
×
Without carrier (high level)
0
0
0
0
1
fX/128 (Duty 1/2)
1
0
fX/192 (Duty 1/2)
1
1
fX/192 (Duty 1/3)
×
×
Without carrier (high level)
1
fX/128
fX/16 (Duty 1/2)
b4, b5, b6: These bits specify the higher 3 bits (DP8, DP9 and DP10) of ROM’s data pointer.
Note Set DP10 of the µPD64A to 0.
Remark
×: don’t care
Data Sheet U14380EJ3V0DS00
17
µPD64A, 65
3.4 Control Register 1 (P4)
Control register 1 consists of 8 bits. The contents that can be controlled are as shown below.
After reset, the register becomes 0010 0110B.
Table 3-6. Control Register 1 (P4)
Bit
b7
Name
b6
—
—
b5
b4
KI
S0/S1
b3
S2
b2
b1
b0
S1/LED
KI/O
S0
Mode
Mode
Set
0
Fixed
Fixed
Pull-down Pull-down STOP Release Mode
OFF
OFF
Disabled S1
IN
OFF
value
1
to “0”
to “0”
ON
ON
Enabled
LED
OUT
IN
0
0
1
0
1
1
0
After reset
0
b 0: Specifies the input mode of the S0 port. “0” = OFF mode (high impedance); “1” = IN (input mode).
b 1: Specifies the I/O mode of the KI/O port. “0” = IN (input mode); “1” = OUT (output mode).
b 2: Specifies the I/O mode of the S1/LED port. “0” = S1 (input mode); “1” = LED (output mode).
b 3: Specifies the use of the STOP mode release for the S2 port (with/without pull-down resistor). “0” = Disabled
(pull-down unavailable); “1” = Enabled (pull-down available).
b4: Specifies the availability of the pull-down resistor for the S0/S1 port input mode. “0” = OFF (unavailable);
“1” = ON (available).
b5: Specifies the availability of the pull-down resistor for the KI port. “0” = OFF (unavailable);
“1” = ON (available).
Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected.
18
Data Sheet U14380EJ3V0DS00
µPD64A, 65
4. TIMER
4.1 Timer Configuration
The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists
of a 9-bit down counter (t8 to t0), a flag (t9) to enable the 1-bit timer output, and a zero detector.
Figure 4-1. Timer Configuration
t9
t8
T0
t7
t6
t3
t5
t4
t2
9-bit down counter
t0
fX/64
fX/128
Timer operation end signal
(HALT #×101B release
signal)
S1/LED
Carrier
synchronous
circuit
REM
t1
Count
clock
Selector
Bit 3 of control register 0 (P3)
T
T1
Zero detector
Bit 2 of control register 0 (P3)
Carrier signal
Data Sheet U14380EJ3V0DS00
19
µPD64A, 65
4.2 Timer Operation
The timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation
instruction. The timer operation instructions for making the timer start operation are shown below.
MOV T0, A
MOV T1, A
MOV T, #data10
MOV T, @R0
The down counter is decremented (–1) in the cycle of 64/fX or 128/fXNote. If the value of the down counter becomes
0, the zero detector generates the timer operation end signal to stop the timer operation. At this time, if the timer
is in HALT mode (HALT #×101B) waiting for the timer to stop operation, the HALT mode is released and the
instruction following the HALT instruction is executed. The output of the timer operation end signal is continued
while the down counter is 0 and the timer is stopped. The following expression indicates the relationship between
the timer’s time and the down counter’s set value.
Timer time = (Set value + 1) × 64/fX (or 128/fXNote)
Note This becomes 128/fX if bit 3 of control register 0 is set (1).
By setting the flag (t9) that enables the timer output to 1, the timer can output its operation status from the S1/
LED and REM pins. The REM pin can also output the carrier while the timer is in operation.
Table 4-1. Timer Output (When t9 = 1)
Timer operating
Timer halted
S 1/LED Pin
REM Pin
L
H
H (or carrier outputNote)
L
Note The carrier is output if bit 2 of control register 0 is cleared (0).
Figure 4-2. Timer Output (When Carrier Is Not Output)
Timer value: (Set value + 1) × 64/fX (or 128/fX)
LED
REM
20
Data Sheet U14380EJ3V0DS00
µPD64A, 65
4.3 Carrier Output
The carrier for remote-controlled transmission can be output from the REM pin by clearing (0) bit 2 of control
register 0.
As shown in Figure 4-3, in the case where the timer stops when the carrier is at a high level, the carrier continues
to be output until its next fall and then stops due to the function of the carrier synchronous circuit. When the timer
starts operation, however, the high-level width of the first carrier may become shorter than the specified width.
Figure 4-3. Timer Output (When Carrier Is Output)
Timer value: (Set value + 1) × 64/fX (or 128/fX)
LED
REM (low-level start)
Note 1
REM (high-level start)
Note 2
Notes 1. Error when the REM output ends: Lead by “carrier low-level width” to lag by “carrier highlevel width”
2. Error of carrier high-level width: 0 to “carrier high-level width”
4.4 Software Control of Timer Output
The timer output can be controlled by software. As shown in Figure 4-4, a pulse with a minimum width of 1
instruction cycle (64/fX) can be output.
…
Figure 4-4. Pulse Output of 1 Instruction Cycle Width
…
MOV T, #0000000000B; low-level output from the REM pin
MOV T, #1000000000B; high-level output from the REM pin
…
MOV T, #0000000000B; low-level output from the REM pin
64/fX
LED
REM
Data Sheet U14380EJ3V0DS00
21
µPD64A, 65
5. STANDBY FUNCTION
5.1 Outline of Standby Function
To reduce current consumption, two types of standby modes, i.e., HALT mode and STOP mode, are available.
In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed at a low level.
In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the
timer (including REM output and LED output) operates.
In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port register, etc.
immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system
so that the current consumption of the whole system is suppressed before the standby mode is set.
Table 5-1. Statuses in Standby Mode
STOP Mode
Setting instruction
HALT instruction
Clock oscillator
Oscillation stopped
CPU
• Operation halted
Data memory
• Immediately preceding status retained
Operation
Accumulator
• Immediately preceding status retained
statuses
Flag
Port register
Timer
HALT Mode
Oscillation continued
F
• 0 (when 1, the flag does not enter the standby mode.)
CY
• Immediately preceding status retained
• Immediately preceding status retained
• Operation halted
• Operable
(The count value is reset to “0”)
Cautions 1. Write the NOP instruction as the first instruction after STOP mode is released.
2. When standby mode is released, the status flag (F) is set (1).
3. If, at the point the standby mode has been set, its release condition is met, then the system
does not enter the standby mode. However, the status flag (F) is set (1).
22
Data Sheet U14380EJ3V0DS00
µPD64A, 65
5.2 Standby Mode Setting and Release
The standby mode is set with the HALT #b3b 2b1b 0B instruction for both STOP mode and HALT mode. For the
standby mode to be set, the status flag (F) is required to have been cleared (0).
The standby mode is released by the release condition specified with the reset (POC) or the operand of the HALT
instruction. If the standby mode is released, the status flag (F) is set (1).
Even when the HALT instruction is executed in a state in which the status flag (F) is set (1), the standby mode
is not set. If the release condition is not met at this time, the status flag is cleared (0). If the release condition is
met, the status flag remains set (1).
Even in the case when the release condition has already been met at the point that the HALT instruction is
executed, the standby mode is not set. Here, also, the status flag (F) is set (1).
Caution Note that depending on the status of the status flag (F), the HALT instruction may not be
executed. For example, when setting HALT mode after checking the key status with the STTS
instruction, the system does not enter HALT mode as long as the status flag (F) remains set
(1), sometimes resulting in an unintended operation. In this case, the intended operation can
be realized by executing the STTS instruction immediately after setting the timer to clear (0)
the status flag.
#03H
;To check the KI pin status
MOV
T, #0xxH
;To set the timer
STTS
#05H
;To clear the status flag
STTS
…
…
Example
HALT
(During this time, be sure not to execute an instruction that may set the status flag.)
#05H
;To set HALT mode
Table 5-2. Addresses Executed After Standby Mode Release
Release Condition
Address Executed After Release
Reset
0 address
Release condition shown in Table 5-3
The address following the HALT instruction
Data Sheet U14380EJ3V0DS00
23
µPD64A, 65
Table 5-3. Standby Mode Setting (HALT #b3b2b1b0B) and Release Conditions
Operand Value of
HALT Instruction
Setting Mode
Precondition for Setting
Release Conditions
b3
b2
b1
b0
0
0
0
0
STOP
All KI/O pins are high-level output.
High level is input to at least one
of KI pins.
0
1
1
STOP
All KI/O pins are high-level output.
High level is input to at least one
of KI pins.
1
1
0
STOPNote 1
The KI/O0 pin is high-level output.
High level is input to at least one
of KI pins.
1
Any combination of
STOP
[The following conditions are added in addition to the above.]
b2b1b0 above
—
High level is input to at least one
of S0, S1 and S2 pins Note 2.
0/1
1
0
1
HALT
—
When the timer’s down counter is 0
Notes 1. When setting HALT #×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that an
internal reset takes effect at the time of program runaway.
2. At least one of the S0, S1 and S2 pins (the pin used for releasing the standby) must be specified as
follows.
S0, S1 pins: Input mode (specified by bits 0 and 2 of the P4 register)
S2 pin:
Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
enters STOP mode only after all the 10 bits of the timer’s down counter and the timer output
enable flag are cleared to 0.
3. Write the NOP instruction as the first instruction after STOP mode is released.
24
Data Sheet U14380EJ3V0DS00
µPD64A, 65
5.3 Standby Mode Release Timing
(1) STOP mode release timing
Figure 5-1. STOP Mode Release by Release Condition
Wait
(52/fX + α)
HALT instruction
(STOP mode)
Standby
release signal
Operating
mode
STOP mode
Oscillation
Oscillation
stopped
HALT mode
Operating
mode
Oscillation
Clock
α : Oscillation growth time
Caution When a release condition is established in the STOP mode, the device is released from the STOP
mode, and goes into a wait state. At this time, if the release condition is not held, the device
goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP
mode, it is necessary to hold the release condition longer than the wait time.
(2) HALT mode release timing
Figure 5-2. HALT Mode Release by Release Condition
Standby
release signal
HALT instruction
(HALT mode)
Operating
mode
HALT mode
Operating mode
Oscillation
Clock
Data Sheet U14380EJ3V0DS00
25
µPD64A, 65
6. RESET
The system is reset by the following occurrences.
• When the POC circuit has detected low-power voltage
• When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed
• When the accumulator is 0H when the RLZ instruction is executed
• When the stack pointer overflows or underflows
Table 6-1. Hardware Statuses After Reset
• Reset by Internal POC Circuit in Operation
• Reset by Other Factor Note 1
Hardware
PC (11 bits)
• Reset by Internal POC Circuit in
Standby Mode
000H
SP (1 bit)
0B
Data
R0 = DP
000H
memory
R1 to RF
Undefined
Accumulator (A)
Undefined
Status flag (F)
0B
Carry flag (CY)
0B
Timer (10 bits)
Port register
Previous status retained
000H
P0
FFH
P1
×××× 11×1BNote 2
Control register P3
P4
03H
26H
Notes 1. The following resets are available.
• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy
the precondition)
• Reset when executing the RLZ instruction (when A = 0)
• Reset by stack pointer overflow or underflow
2. Value according to the KI or S2 pin status.
In order to prevent malfunction, do not input a high level to all the KI0 to KI3 pins when POC is released
due to supply voltage startup (these pins can be left open. When leaving open, keep pull-down
resistors connected).
26
Data Sheet U14380EJ3V0DS00
µPD64A, 65
7. POC CIRCUIT
The POC circuit monitors the power supply voltage and applies an internal reset in the microcontroller when the
battery is replaced.
Cautions 1. There are cases in which the POC circuit cannot detect a low power supply voltage of less
than 1 ms. Therefore, if the power supply voltage has become low for a period of less than
1 ms, the POC circuit may malfunction because it does not generate an internal reset signal.
2. Clock oscillation is stopped by the resonator due to low power supply voltage before the
POC circuit generates the internal reset signal. In this case, malfunction may result, for
example when the power supply voltage is recovered after the oscillation is stopped. This
type of phenomenon takes place because the POC circuit does not generate an internal reset
signal (because the power supply voltage recovers before the low power supply voltage is
detected) even though the clock has stopped. If, by any chance, a malfunction has taken
place, remove the battery for a short time and put it back. In most cases, normal operation
will be resumed.
3. In order to prevent malfunction, do not input a high level to all the KI0 to KI3 pins when POC
is released due to supply voltage startup (these pins can be left open. When leaving open,
keep pull-down resistors connected).
Data Sheet U14380EJ3V0DS00
27
µPD64A, 65
7.1 Functions of POC Circuit
The POC circuit has the following functions.
• Generates an internal reset signal when VDD ≤ V POC.
• Cancels an internal reset signal when VDD > VPOC.
Here, VDD: Power supply voltage, VPOC: POC detection voltage.
VDD
Operating ambient temperature TA = –40 to +85°C
3.6 V
Clock frequency fX = 2.4 to 8 MHz
2.0 V
←POC detection voltage VPOC = 1.85 V (TYP.)Note 3
VPOC
Approx. 1.7 V
0V
→t
Internal reset signal
Reset
↑
Note 1
Operating mode
↑ Reset
Note 2
Notes 1. In reality, an oscillation stabilization wait time must elapse before the circuit is switched to operating
mode. The oscillation stabilization wait time is about 246/fX to 694/fX (about 70 to 190 µs, at fX = 3.64
MHz).
2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen,
it is necessary for the power supply voltage to be kept less than the VPOC for a period of 1 ms or more.
Therefore, in reality, there is a time lag of up to 1 ms until the reset takes effect.
3. The POC detection voltage (VPOC) varies between approximately 1.7 to 2.0 V; thus, the reset may
be canceled at a power supply voltage smaller than the assured range (VDD = 2.0 to 3.6 V). However,
as long as the conditions for operating the POC circuit are met, the actual lowest operating power
supply voltage is lower than the POC detection voltage. Therefore, no malfunction occurs due to the
shortage of power supply voltage. However, malfunction for such reasons as the clock not oscillating
due to low power supply voltage may occur (refer to Cautions 3. in 7. POC CIRCUIT).
7.2 Oscillation Check at Low Supply Voltage
A reliable reset operation can be expected from the POC circuit if it satisfies the condition that the clock can
oscillate even at a low power supply voltage (the oscillation start voltage of the resonator being even lower than
the POC detection voltage). Whether this condition is met or not can be checked by measuring the oscillation status
on a product which actually contains a POC circuit, as follows.
<1> Connect a storage oscilloscope to the X OUT pin so that the oscillation status can be measured.
<2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply
voltage V DD from 0 V (making sure to avoid V DD > 3.6 V).
At first (when VDD < approx. 1.7 V), the XOUT pin is 0 V regardless of the VDD. However, at the point when VDD
reaches the POC detection voltage (VPOC = 1.85 V (TYP.)), the voltage of the XOUT pin jumps to about 0.5VDD.
Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If, by any chance, the
oscillation start voltage of the resonator is lower than the POC detection voltage, the growing oscillation of the XOUT
pin can be confirmed within several ms after VDD has reached VPOC.
28
Data Sheet U14380EJ3V0DS00
µPD64A, 65
8. SYSTEM CLOCK OSCILLATOR
The system clock oscillator is configured by an oscillator circuit for a ceramic resonator (fX = 2.4 to 8 MHz).
Figure 8-1. System Clock
µ PD64A, 65
XOUT
XIN
GND
Ceramic resonator
The system clock oscillator stops its oscillation after reset or in STOP mode.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as the ground.
Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Data Sheet U14380EJ3V0DS00
29
µPD64A, 65
9. INSTRUCTION SET
9.1 Machine Language Output by Assembler
The bit length of the machine language of this product is 10 bits per word. However, the machine language output
by the assembler is extended to 16 bits per word. As shown in the example below, the extension is made by inserting
3 extended bits (111) in two locations.
Figure 9-1. Example of Assembler Output (10 Bits Extended to 16 Bits)
<1> In the case of “ANL A, @R0H”
1 1 1
1
1 0 1 0
1
1
1 0 1 0
1 1 1
Extended bits
0 0 0 0
1
0 0 0 0
= FAF0
1 0 0 0
= E6F8
Extended bits
<2> In the case of “OUT P0, #data8”
1 1 1
Extended bits
30
0
0 1 1 0
1
0
0 1 1 0
1 1 1
1 0 0 0
1
Extended bits
Data Sheet U14380EJ3V0DS00
µPD64A, 65
9.2 Circuit Symbol Description
A:
Accumulator
ASR:
Address stack register
addr:
Program memory address
CY:
Carry flag
data4:
4-bit immediate data
data8:
8-bit immediate data
data10:
10-bit immediate data
F:
Status flag
PC:
Program counter
Pn:
Port register pair (n = 0, 1, 3, 4)
P0n:
Port register (lower 4 bits)
P1n:
Port register (higher 4 bits)
ROMn:
Bit n of the program memory (n = 0 to 9)
Rn:
Register pair
R0n:
Data memory (general-purpose register; n = 0 to F)
R1n:
Data memory (general-purpose register; n = 0 to F)
SP:
Stack pointer
T:
Timer register
T0:
Timer register (lower 4 bits)
T1:
Timer register (higher 4 bits)
(×):
Content addressed with ×
Data Sheet U14380EJ3V0DS00
31
µPD64A, 65
9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table
Accumulator operation instructions
Instruction Code
Operand
1st Word
Operation
Instruction
Instruction
Length
Cycle
3rd Word
A, R0n
FBEn
(A) ← (A)
A, R1n
FAEn
CY ← A3 • Rmn3
A, @R0H
FAF0
(A) ← (A)
(Rmn) m = 0, 1 n = 0 to F
∨
ANL
2nd Word
∨
Mnemonic
1
((P13), (R0))7-4
CY ← A3 • ROM7
(A) ← (A)
FBF0
∨
A, @R0L
((P13), (R0)) 3-0
CY ← A3 • ROM3
FBF1
data4
(A) ← (A)
∨
A, #data4
data4
2
CY ← A3 • data43
ORL
A, R0n
FDEn
(A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F
A, R1n
FCEn
CY ← 0
A, @R0H
FCF0
1
(A) ← (A) ∨ ((P13), (R0))7-4
CY ← 0
A, @R0L
(A) ← (A) ∨ ((P13), (R0))3-0
FDF0
CY ← 0
A, #data4
FDF1
data4
(A) ← (A) ∨ data4
2
CY ← 0
XRL
A, R0n
F5En
(A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F
A, R1n
F4En
CY ← A3 • Rmn3
A, @R0H
F4F0
1
(A) ← (A) ∨ ((P13), (R0))7-4
CY ← A3 • ROM7
A, @R0L
(A) ← (A) ∨ ((P13), (R0))3-0
F5F0
CY ← A3 • ROM3
A, #data4
F5F1
data4
(A) ← (A) ∨ data4
2
CY ← A3 • data43
INC
A
F4F3
(A) ← (A) + 1
if (A) = 0
CY ← 1
else CY ← 0
RL
A
FCF3
(An+1) ← (A n), (A0) ← (A3)
RLZ
A
FEF3
if A = 0
CY ← A3
reset
else (An+1) ← (An), (A 0) ← (A 3)
CY ← A3
32
Data Sheet U14380EJ3V0DS00
1
1
µPD64A, 65
Input/output instructions
IN
OUT
ANL
ORL
XRL
Mnemonic
Instruction Code
Operand
2nd Word
3rd Word
A, P0n
FFF8 + n
—
—
(A) ← (Pmn)
A, P1n
FEF8 + n
—
—
CY ← 0
(Pmn) ← (A)
Remark
m = 0, 1
n = 0, 1, 3, 4
m = 0, 1
n = 0, 1, 3, 4
P0n, A
E5F8 + n
—
—
P1n, A
E4F8 + n
—
—
A, P0n
FBF8 + n
—
—
(A) ← (A)
A, P1n
FAF8 + n
—
—
CY ← A3 • Pmn 3
A, P0n
FDF8 + n
—
—
(A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
A, P1n
FCF8 + n
—
—
CY ← 0
A, P0n
F5F8 + n
—
—
(A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
A, P1n
F4F8 + n
—
—
CY ← A3 • Pmn 3
Pn, #data8 E6F8 + n
2nd Word
Instruction
Instruction
Length
Cycle
1
1
Instruction
Instruction
(Pmn) m = 0, 1 n = 0, 1, 3, 4
Instruction Code
Operand
1st Word
OUT
Operation
1st Word
∨
Mnemonic
Operation
3rd Word
Length
(Pn) ← data8
data8
n = 0, 1, 3, 4
2
Cycle
1
Pn: P1n-P0n are handled in pairs.
Data transfer instructions
Mnemonic
Instruction Code
Operand
1st Word
MOV
2nd Word
Operation
Instruction
Instruction
Length
Cycle
3rd Word
A, R0n
FFEn
(A) ← (Rmn)
A, R1n
FEEn
CY ← 0
A, @R0H
FEF0
(A) ← ((P13), (R0))7-4
m = 0, 1
n = 0 to F
1
1
CY ← 0
A, @R0L
(A) ← ((P13), (R0))3-0
FFF0
CY ← 0
Mnemonic
A, #data4
FFF1
R0n, A
E5En
R1n, A
E4En
(Rmn) ← (A)
Instruction Code
Operand
1st Word
MOV
Rn, #data8 E6En
Rn, @R0
Remark
(A) ← data4
CY ← 0
data4
E7En
2nd Word
2
m = 0, 1
n = 0 to F
Operation
1
Instruction
Instruction
Length
Cycle
3rd Word
data8
—
(R1n-R0n) ← data8
n = 0 to F
2
—
—
(R1n-R0n) ← ((P13), (R0)) n = 1 to F
1
1
Rn: R1n-R0n are handled in pairs.
Data Sheet U14380EJ3V0DS00
33
µPD64A, 65
Branch instructions
Mnemonic
Instruction Code
Operand
1st Word
JMP
JC
JNC
JF
JNF
2nd Word
addr (Page 0) E8F1
addr
addr (Page 1) E9F1
addr
Operation
Instruction
Instruction
Length
Cycle
3rd Word
PC ← addr
2
1
PC ← addr
addr (Page 0) ECF1
addr
If CY = 1
addr (Page 1) EAF1
addr
else PC ← PC + 2
addr (Page 0) EDF1
addr
If CY = 0
addr (Page 1) EBF1
addr
else PC ← PC + 2
addr (Page 0) EEF1
addr
If F = 1
addr (Page 1) F0F1
addr
else PC ← PC + 2
addr (Page 0) EFF1
addr
If F = 0
addr (Page 1) F1F1
addr
else PC ← PC + 2
PC ← addr
PC ← addr
PC ← addr
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics.
Subroutine instructions
Mnemonic
Instruction Code
Operand
1st Word
CALL
Operation
2nd Word
3rd Word
addr (Page 0) E6F2
E8F1
addr
addr (Page 1) E6F2
E9F1
addr
RET
E8F2
Instruction
Instruction
Length
Cycle
SP ← SP + 1, ASR ← PC, PC ← addr
3
2
PC ← ASR, SP ← SP – 1
1
1
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics.
Timer operation instructions
Mnemonic
Instruction Code
Operand
1st Word
MOV
Mnemonic
MOV
34
2nd Word
3rd Word
FFFF
A, T1
FEFF
CY ← 0
T0, A
E5FF
(Tn) ← (A)
T1, A
F4FF
(T) n ← 0
Instruction Code
1st Word
2nd Word
T, #data10
E6FF
data10
T, @R0
F4FF
Instruction
Length
(A) ← (Tn)
A, T0
Operand
Instruction
Operation
n = 0, 1
1
Cycle
1
n = 0, 1
Operation
Instruction
Instruction
Length
Cycle
3rd Word
(T) ← data10
(T) ← ((P13), (R0))
Data Sheet U14380EJ3V0DS00
1
1
µPD64A, 65
Other instructions
Mnemonic
Instruction Code
Operand
1st Word
2nd Word
Operation
HALT
#data4
E2F1
data4
Standby mode
STTS
#data4
E3F1
data4
If statuses match
R0n
E3En
else
FAF3
NOP
E0E0
Instruction
Length
Cycle
F←1
F←0
If A = 0FH
else
2
1
F←1
F←0
If statuses match
else
SCAF
Instruction
3rd Word
1
n = 0 to F
CY ← 1
CY ← 0
PC ← PC + 1
Data Sheet U14380EJ3V0DS00
35
µPD64A, 65
9.4 Accumulator Operation Instructions
ANL A, R0n
ANL A, R1n
1 1 0 1 R4 0 R3 R2 R1 R0
<2> Cycle count:
1
<3> Function:
(A) ← (A)
∨
<1> Instruction code:
(Rmn)
m = 0, 1
n = 0 to F
CY ← A 3 • Rmn3
The accumulator contents and the register Rmn contents are ANDed and the results are entered in the
accumulator.
ANL A, @R0H
ANL A, @R0L
<1> Instruction code:
1 1 0 1 0/1 1 0 0 0 0
<2> Cycle count:
1
(A) ← (A)
∨
<3> Function:
((P13), (R0))7-4 (in the case of ANL A, @R0H)
CY ← A 3 • ROM 7
∨
(A) ← (A)
((P13), (R0))3-0 (in the case of ANL A, @R0L)
CY ← A 3 • ROM 3
The accumulator contents and the program memory contents specified with the control register P13 and
register pair R10-R00 are ANDed and the results are entered in the accumulator.
If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b 0 take effect.
• Program memory (ROM) organization
b9
b7
b6
b5
b4
b8
b3
b2
H↓
b1
b0
L↓
Valid bits at the time of accumulator operation
ANL A, #data4
<1> Instruction code:
1 1 0 1 1 1 0 0 0 1
0 0 0 0 0 0 d3 d2 d1 d0
1
<3> Function:
(A) ← (A)
∨
<2> Cycle count:
data4
CY ← A 3 • data43
The accumulator contents and the immediate data are ANDed and the results are entered in the
accumulator.
36
Data Sheet U14380EJ3V0DS00
µPD64A, 65
ORL A, R0n
ORL A, R1n
<1> Instruction code:
1 1 1 0 R4 0 R3 R2 R1 R0
<2> Cycle count:
1
<3> Function:
(A) ← (A) ∨ (Rmn)
m = 0, 1
n = 0 to F
CY ← 0
The accumulator contents and the register Rmn contents are ORed and the results are entered in the
accumulator.
ORL A, @R0H
ORL A, @R0L
<1> Instruction code:
1 1 1 0 0/1 1 0 0 0 0
<2> Cycle count:
1
<3> Function:
(A) ← (A) ∨ (P13), (R0)) 7-4 (in the case of ORL A, @R0H)
(A) ← (A) ∨ (P13), (R0)) 3-0 (in the case of ORL A, @R0L)
CY ← 0
The accumulator contents and the program memory contents specified with the control register P13 and
register pair R10-R00 are ORed and the results are entered in the accumulator.
If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b 0 take effect.
ORL A, #data4
<1> Instruction code:
1 1 1 0 1 1 0 0 0 1
0 0 0 0 0 0 d3 d2 d1 d0
<2> Cycle count:
1
<3> Function:
(A) ← (A) ∨ data4
CY ← 0
The accumulator contents and the immediate data are ORed and the results are entered in the
accumulator.
XRL A, R0n
XRL A, R1n
<1> Instruction code:
1 0 1 0 R4 0 R3 R2 R1 R0
<2> Cycle count:
1
<3> Function:
(A) ← (A) ∨ (Rmn)
m = 0, 1
n = 0 to F
CY ← A 3 • Rmn3
The accumulator contents and the register Rmn contents are exclusive-ORed and the results are
entered in the accumulator.
Data Sheet U14380EJ3V0DS00
37
µPD64A, 65
XRL A, @R0H
XRL A, @R0L
<1> Instruction code:
1 0 1 0 0/1 1 0 0 0 0
<2> Cycle count:
1
<3> Function:
(A) ← (A) ∨ (P13), (R0)) 7-4 (in the case of XRL A, @R0H)
CY ← A 3 • ROM 7
(A) ← (A) ∨ (P13), (R0)) 3-0 (in the case of XRL A, @R0L)
CY ← A 3 • ROM 3
The accumulator contents and the program memory contents specified with the control register P13 and
register pair R10-R00 are exclusive-ORed and the results are entered in the accumulator.
If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect.
XRL A, #data4
<1> Instruction code:
1 0 1 0 1 1 0 0 0 1
0 0 0 0 0 0 d3 d2 d1 d0
<2> Cycle count:
1
<3> Function:
(A) ← (A) ∨ data4
CY ← A 3 • data43
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in
the accumulator.
INC A
<1> Instruction code:
1 0 1 0 0 1 0 0 1 1
<2> Cycle count:
1
<3> Function:
(A) ← (A) + 1
If
A = 0
else
CY ← 1
CY ← 0
The accumulator contents are incremented (+1).
RL A
<1> Instruction code:
1 1 1 0 0 1 0 0 1 1
<2> Cycle count:
1
<3> Function:
(A n + 1) ← (A n), (A 0) ← (A 3)
CY ← A 3
The accumulator contents are rotated counterclockwise bit by bit.
RLZ A
<1> Instruction code:
1 1 1 1 0 1 0 0 1 1
<2> Cycle count:
1
<3> Function:
If
A = 0
else
reset
(A n + 1) ← (A n), (A 0) ← (A3)
CY ← A 3
The accumulator contents are rotated counterclockwise bit by bit.
If A = 0H at the time of instruction execution, an internal reset takes effect.
38
Data Sheet U14380EJ3V0DS00
µPD64A, 65
9.5 I/O Instructions
IN A, P0n
IN A, P1n
<1> Instruction code:
1 1 1 1 P4 1 1 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(A) ← (Pmn)
m = 0, 1
n = 0, 1, 3, 4
CY ← 0
The port Pmn data is loaded (read) into the accumulator.
OUT P0n, A
OUT P1n, A
<1> Instruction code:
0 0 1 0 P4 1 1 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(Pmn) ← (A)
m = 0, 1
n = 0, 1, 3, 4
The accumulator contents are transferred to port Pmn to be latched.
ANL A, P0n
ANL A, P1n
<1> Instruction code:
1 1 0 1 P4 1 1 P2 P1 P0
<2> Cycle count:
1
(A) ← (A)
∨
<3> Function:
(Pmn)
m = 0, 1
n = 0, 1, 3, 4
CY ← A 3 • Pmn
The accumulator contents and the port Pmn contents are ANDed and the results are entered in the
accumulator.
ORL A, P0n
ORL A, P1n
<1> Instruction code:
1 1 1 0 P4 1 1 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(A) ← (A) ∨ (Pmn)
m = 0, 1
n = 0, 1, 3, 4
CY ← 0
The accumulator contents and the port Pmn contents are ORed and the results are entered in the
accumulator.
XRL A, P0n
XRL A, P1n
<1> Instruction code:
1 0 1 0 P4 1 1 P2 P1 P0
<2> Cycle count:
1
<3> Function:
(A) ← (A) ∨ (Pmn)
m = 0, 1
n = 0, 1, 3, 4
CY ← A 3 • Pmn
The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered
in the accumulator.
Data Sheet U14380EJ3V0DS00
39
µPD64A, 65
OUT Pn, #data8
<1> Instruction code:
0 0 1 1 0 1 1 P2 P1 P0
0 d7 d6 d5 d4 0 d3 d2 d1 d0
<2> Cycle count:
1
<3> Function:
(Pn) ← data8
n = 0, 1, 3, 4
The immediate data is transferred to port Pn. In this case, port Pn refers to P1n-P 0n operating in pairs.
9.6 Data Transfer Instructions
MOV A, R0n
MOV A, R1n
<1> Instruction code:
1 1 1 1 R4 0 R3 R2 R1 R0
<2> Cycle count:
1
(A) ← (Rmn)
<3> Function:
m = 0, 1
n = 0 to F
CY ← 0
The register Rmn contents are transferred to the accumulator.
MOV A, @R0H
<1> Instruction code:
1 1 1 1 0 1 0 0 0 0
<2> Cycle count:
1
<3> Function:
(A) ← ((P13), (R0))7-4
CY ← 0
The higher 4 bits (b7 b6 b5 b4) of the program memory specified with control register P13 and register
pair R10-R00 are transferred to the accumulator. b9 is ignored.
MOV A, @R0L
<1> Instruction code:
1 1 1 1 1 1 0 0 0 0
<2> Cycle count:
1
<3> Function:
(A) ← ((P13), (R0))3-0
CY ← 0
The lower 4 bits (b3 b2 b1 b0) of the program memory specified with control register P13 and register
pair R10-R00 are transferred to the accumulator. b8 is ignored.
• Program memory (ROM) contents
@R0 H
b9
b7
b6
b5
@R0 L
b4
b8
b3
b2
b1
b0
MOV A, #data4
<1> Instruction code:
1 1 1 1 1 1 0 0 0 1
<2> Cycle count:
1
0 0 0 0 0 0 d3 d2 d1 d0
<3> Function:
(A) ← data4
CY ← 0
The immediate data is transferred to the accumulator.
40
Data Sheet U14380EJ3V0DS00
µPD64A, 65
MOV R0n, A
MOV R1n, A
<1> Instruction code:
0 0 1 0 R4 0 R3 R2 R1 R0
<2> Cycle count:
1
<3> Function:
(Rmn) ← (A)
m = 0, 1
n = 0 to F
The accumulator contents are transferred to register Rmn.
MOV Rn, #data8
<1> Instruction code:
0 0 1 1 0 0 R3 R2 R1 R0
<2> Cycle count:
1
<3> Function:
(R1n-R0n) ← data8
0 d7 d6 d5 d4 0 d3 d2 d1 d0
n = 0 to F
The immediate data is transferred to the register. Using this instruction, registers operate as register
pairs.
The pair combinations are as follows.
R0: R10 - R00
…
R1: R11 - R01
RE: R 1E - R0E
RF: R1F - R0F
Lower column
Higher column
MOV Rn, @R0
<1> Instruction code:
0 0 1 1 1 0 R3 R2 R1 R0
<2> Cycle count:
1
<3> Function:
(R1n-R0n) ← ((P13), R0))
n = 1 to F
The program memory contents specified with control register P13 and register pair R10-R00 are
transferred to register pair R1n-R0n. The program memory consists of 10 bits and has the following
state after the transfer to the register.
Program memory
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
→
b9
b7
@R0
b6
b5
R1n
b4
b8
b3
b2
b1
b0
R0n
The higher 3 bits of the program memory address is specified with the control register (P13).
Data Sheet U14380EJ3V0DS00
41
µPD64A, 65
9.7 Branch Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically
performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as
follows.
µPD64A (ROM: 1K steps):
Page 0
µPD65 (ROM: 2K steps):
Pages 0, 1
µPD6P5 (PROM: 2K steps): Pages 0, 1
JMP addr
<1> Instruction code:
page 0
<2> Cycle count:
1
<3> Function:
PC ← addr
0 1 0 0 0 1 0 0 0 1
,
page 1
0 1 0 0 1 1 0 0 0 1
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to
a0).
JC addr
<1> Instruction code:
page 0
<2> Cycle count:
1
<3> Function:
If
0 1 1 0 0 1 0 0 0 1
,
page 1
0 1 0 1 0 1 0 0 0 1
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
CY = 1
else
PC ← addr
PC ← PC + 2
If the carry flag CY is set (1), a jump is made to the address specified with addr (a9 to a0).
JNC addr
<1> Instruction code:
page 0
<2> Cycle count:
1
<3> Function:
If
0 1 1 0 1 1 0 0 0 1
,
page 1
0 1 0 1 1 1 0 0 0 1
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
CY = 0
else
PC ← addr
PC ← PC + 2
If the carry flag CY is cleared (0), a jump is made to the address specified with addr (a9 to a0).
JF addr
<1> Instruction code:
page 0
<2> Cycle count:
1
<3> Function:
If
0 1 1 1 0 1 0 0 0 1
,
page 1
1 0 0 0 0 1 0 0 0 1
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
F = 1
else
PC ← addr
PC ← PC + 2
If the status flag F is set (1), a jump is made to the address specified with addr (a9 to a0).
JNF addr
<1> Instruction code:
page 0
<2> Cycle count:
1
<3> Function:
If
0 1 1 1 1 1 0 0 0 1
,
page 1
1 0 0 0 1 1 0 0 0 1
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
F = 0
else
PC ← addr
PC ← PC + 2
If the status flag F is cleared (0), a jump is made to the address specified with addr (a9 to a0).
42
Data Sheet U14380EJ3V0DS00
µPD64A, 65
9.8 Subroutine Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically
performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as
follows.
µPD64A (ROM: 1K steps):
Page 0
µPD65 (ROM: 2K steps):
Pages 0, 1
µPD6P5 (PROM: 2K steps): Pages 0, 1
CALL addr
<1> Instruction code:
0 0 1 1 0 1 0 0 1 0
page 0
0 1 0 0 0 1 0 0 0 1
,
page 1
0 1 0 0 1 1 0 0 0 1
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
<2> Cycle count:
<3> Function:
2
SP ← SP + 1
ASR ← PC
PC ← addr
The stack pointer value is incremented (+1) and the program counter value is saved to the address stack
register. The address specified with the operand addr (a9 to a0) is then entered in the program counter.
If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect.
RET
<1> Instruction code:
0 1 0 0 0 1 0 0 1 0
<2> Cycle count:
1
<3> Function:
PC ← ASR
SP ← SP – 1
The value saved in the address stack register is restored to the program counter. The stack pointer
is then decremented (–1).
If a borrow is generated when the stack pointer value is decremented (–1), an internal reset takes effect.
Data Sheet U14380EJ3V0DS00
43
µPD64A, 65
9.9 Timer Operation Instructions
MOV A, T0
MOV A, T1
<1> Instruction code:
1 1 1 1 0/1 1 1 1 1 1
<2> Cycle count:
1
<3> Function:
(A) ← (Tn)
n = 0, 1
CY ← 0
The timer Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0 corresponds
to (t5, t4, t3, t2).
T
t9
t8
t7
t6
T1
t5
t4
t3
t2
t1
t0
T0
↓
MOV T, #data10
Can be set with
MOV T, @R0
MOV T0, A
MOV T1, A
<1> Instruction code:
0 0 1 0 0/1 1 1 1 1 1
<2> Cycle count:
1
<3> Function:
(Tn) ← (A)
n = 0, 1
The accumulator contents are transferred to timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0
corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes
0; if data is transferred to T0, t0 becomes 0.
MOV T, #data10
<1> Instruction code:
0 0 1 1 0 1 1 1 1 1
<2> Cycle count:
1
<3> Function:
(T) ← data10
t1 t9 t8 t7 t6 t0 t5 t4 t3 t2
The immediate data is transferred to timer register T (t9-t0).
Remark The timer time is set with (set value + 1) × 64/f X (or 128/fX).
44
Data Sheet U14380EJ3V0DS00
µPD64A, 65
MOV T, @R0
<1> Instruction code:
0 0 1 1 1 1 1 1 1 1
<2> Cycle count:
1
<3> Function:
(T) ← ((P13), (R0))
The program memory contents specified by the control register P13 and the register pair R10-R00 are
transferred to timer register T (t9 to t0).
The program memory, which consists of 10 bits, is placed in the following state after the transfer to the
register.
Timer
Program memory
t9
t1
t8
t7
t6
t0
T
t5
t4
t3
→
t2
t9
@R0
t8
t7
T1
t6
t5
t4
t3
t2
t1
t0
T0
The higher 3 bits of the program memory address are specified by the control register (P13).
Caution When setting a timer value in the program memory, be sure to use the DT quasi
directive.
9.10 Other Instructions
HALT #data4
<1> Instruction code:
0 0 0 1 0 1 0 0 0 1
<2> Cycle count:
1
<3> Function:
Standby mode
0 0 0 0 0 0 d3 d2 d1 d0
Places the CPU in standby mode.
The condition to cancel the standby mode (HALT/STOP mode) is specified by the immediate data.
STTS R0n
<1> Instruction code:
0 0 0 1 1 0 R3 R2 R1 R0
<2> Cycle count:
1
<3> Function:
If statuses match
else
F ← 0
F← 1
n = 0 to F
The S0, S1, KI/O , KI, and TIMER statuses are compared with the register R0n contents. If at least one
of the statuses matches the bits that have been set, status flag F is set (1).
If none of them match, status flag F is cleared (0).
Data Sheet U14380EJ3V0DS00
45
µPD64A, 65
STTS #data4
<1> Instruction code:
0 0 0 1 1 1 0 0 0 1
0 0 0 0 0 0 d3 d2 d1 d0
<2> Cycle count:
1
<3> Function:
If statuses match
else
F← 1
F ← 0
The S0, S1, KI/O, KI, and TIMER statuses are compared with the immediate data contents. If at least
one of the statuses matches the bits that have been set, status flag F is set (1).
If none of them match, status flag F is cleared (0).
SCAF (Set Carry If ACC = F H)
<1> Instruction code:
1 1 0 1 0 1 0 0 1 1
<2> Cycle count:
1
<3> Function:
If
CY ← 1
A = 0FH
else
CY ← 0
The carry flag CY is set (1) if the accumulator contents are FH.
The accumulator values after executing the SCAF instruction are as follows.
Accumulator Value
Before Execution
Carry Flag
After Execution
×××0
0000
0 (clear)
××01
0001
0 (clear)
×011
0011
0 (clear)
0111
0111
0 (clear)
1111
1111
1 (set)
Remark
×: don’t care
NOP
<1> Instruction code:
0 0 0 0 0 0 0 0 0 0
<2> Cycle count:
1
<3> Function:
PC ← PC + 1
No operation
46
Data Sheet U14380EJ3V0DS00
µPD64A, 65
10. ASSEMBLER RESERVED WORDS
10.1 Mask Option Quasi Directives
When creating the µPD64A and 65 program, it is necessary to use a mask option quasi directive in the
assembler’s source program.
10.1.1 OPTION and ENDOP quasi directives
The OPTION and subsequent quasi directives down to the ENDOP quasi directive are called the mask option
definition block. The format of the mask option definition block is as follows.
Format
Symbol field
Mnemonic field
[Label:]
OPTION
Operand field
Comment field
[; Comment]
:
:
ENDOP
10.1.2 Mask option definition quasi directive
The quasi directive that can be used in the mask option definition block is shown in Table 10-1.
The mask option definition can only be specified as follows. Be sure to specify the following quasi directive.
Example
Symbol field
Mnemonic field
Operand field
Comment field
OPTION
USEPOC
; POC circuit incorporated
ENDOP
Table 10-1. Mask Option Definition Quasi Directive
Name
POC
PRO File
Mask Option Definition Quasi Directive
USEPOC
(POC circuit incorporated)
Address Value
Data Value
2044H
01
Data Sheet U14380EJ3V0DS00
47
µPD64A, 65
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C)
Parameter
Power supply voltage
Symbol
Conditions
Ratings
Unit
–0.3 to +3.8
V
–0.3 to V DD + 0.3
V
–0.3 to V DD + 0.3
V
VDD
Input voltage
VI
Output voltage
VO
Output current, high
IOHNote
KI/O, K I, S0, S1, S2
REM
LED
Peak value
–30
mA
rms value
–20
mA
Peak value
–7.5
mA
–5
mA
–13.5
mA
–9
mA
rms value
Per K I/O pin
Peak value
rms value
Total of LED and KI/O pins
Output current, low
IOLNote
REM
Peak value
–18
mA
rms value
–12
mA
Peak value
7.5
mA
5
mA
rms value
LED
Peak value
rms value
7.5
mA
5
mA
Operating ambient
temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Note The rms value should be calculated as follows: [rms value] = [Peak value] × √ Duty
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Power Supply Voltage Range (TA = –40 to +85°C)
Parameter
Power supply voltage
48
Symbol
VDD
Conditions
fX = 2.4 to 8 MHz
Data Sheet U14380EJ3V0DS00
MIN.
TYP.
MAX.
Unit
2.0
3.0
3.6
V
µPD64A, 65
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)
Parameter
Input voltage, high
Input voltage, low
Input leakage
Symbol
MAX.
Unit
0.8V DD
VDD
V
KI/O
0.7V DD
VDD
V
K I , S 0 , S1
0.65VDD
VDD
V
S2
VIH2
VIH3
MIN.
TYP.
VIL1
S2
0
0.2V DD
V
VIL2
KI/O
0
0.3V DD
V
VIL3
K I , S 0 , S1
0
0.15VDD
V
ILIH1
KI
VI = VDD, pull-down resistor not incorporated
3
µA
ILIH2
S 0, S 1 , S 2
VI = VDD, pull-down resistor not incorporated
3
µA
ILIL1
KI
VI = 0 V
–3
µA
current, high
Input leakage
Conditions
VIH1
ILIL2
KI/O
VI = 0 V
–3
µA
ILIL3
S 0, S 1 , S 2 V I = 0 V
–3
µA
Output voltage, high
VOH1
REM, LED, KI/O
IOH = –0.3 mA
Output voltage, low
VOL1
REM, LED
IOL = 0.3 mA
current, low
0.8VDD
V
0.3
V
VOL2
KI/O
IOL = 15 µA
Output current, high
IOH1
REM
VDD = 3.0 V, VOH = 1.0 V
–5
–12
mA
IOH2
KI/O
VDD = 3.0 V, VOH = 2.2 V
–2.5
–7
mA
Output current, low
IOL1
KI/O
VDD = 3.0 V, VOL = 0.4 V
30
70
µA
VDD = 3.0 V, VOL = 2.2 V
100
390
On-chip pull-down
R1
K I , S 0 , S1 , S 2
75
150
300
kΩ
resistor
R2
KI/O
130
250
500
kΩ
Data retention power
supply voltage
VDDDR
In STOP mode
0.9
3.6
V
Supply current
IDD1
Operating
fX = 8.0 MHz, VDD = 3 V ±10%
0.8
1.6
mA
mode
fX = 4.0 MHz, VDD = 3 V ±10%
0.7
1.4
mA
IDD2
IDD3
HALT mode
STOP mode
0.4
V
µA
fX = 8.0 MHz, VDD = 3 V ±10%
0.75
1.5
mA
fX = 4.0 MHz, VDD = 3 V ±10%
0.65
1.3
mA
VDD = 3 V ±10%
1.9
9.0
µA
VDD = 3 V ±10%, TA = 25°C
1.9
5.0
µA
Data Sheet U14380EJ3V0DS00
49
µPD64A, 65
AC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)
Parameter
Symbol
Instruction execution time
t CY
KI, S0, S1, S2 high-level
tH
width
Conditions
MIN.
TYP.
7.9
When standby mode is released
MAX.
Unit
27
µs
10
µs
In HALT mode
10
µs
In STOP mode
Note
µs
Note 10 + 52/fX + oscillation growth time
Remark tCY = 64/fX (fX: System clock oscillation frequency)
POC Circuit (TA = –40 to +85°C)
Parameter
POC detection voltageNote
Symbol
Conditions
MIN.
VPOC
TYP.
MAX.
Unit
1.85
2.0
V
Note The voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal reset is
canceled.
From the time of VPOC ≥ V DD until the internal reset takes effect, a lag of up to 1 ms occurs. When the
period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect.
System Clock Oscillator Characteristics (TA = –40 to +85 °C, VDD = 2.0 to 3.6 V)
Parameter
Oscillation frequency
Symbol
Conditions
fX
(ceramic resonator)
50
Data Sheet U14380EJ3V0DS00
MIN.
TYP.
MAX.
Unit
2.4
3.64
8.0
MHz
µPD64A, 65
Recommended Ceramic Resonator (TA = –40 to +85°C)
Manufacturer
TDK Corp.
Murata Mfg. Co., Ltd
Part Number
Frequency Recommended Constant
(MHz)
C1 [pF]
C2 [pF]
FCR3.52MC5
3.52
FCR3.58MC5
3.58
FCR3.64MC5
3.64
FCR3.84MC5
3.84
FCR4.0MC5
4.0
FCR6.0MC5
6.0
FCR8.0MC5
8.0
CSA2.50MG040
2.5
Unnecessary
(On-chip C type)
100
CST2.50MG040
CSA3.52MG
3.52
3.58
3.64
30
30
30
Unnecessary
(On-chip C type)
CSTS0364MG03
3.84
30
30
Unnecessary
(On-chip C type)
CST3.84MGW
CST0384MG03
4.0
30
30
Unnecessary
(On-chip C type)
CST4.00MGW
CSTS0400MG03
6.0
30
30
Unnecessary
(On-chip C type)
CST6.00MGW
CSTS0600MG03
CSA8.00MTZ
30
30
CST3.64MGW
CSA6.00MG
3.6
Unnecessary
(On-chip C type)
CST0358MG03
CSA4.00MG
2.0
Remark
Unnecessary
(On-chip C type)
CST3.58MGW
CSA3.84MG
MAX.
100
30
CSTS0352MG03
CSA3.64MG
MIN.
Unnecessary
(On-chip C type)
CST3.52MGW
CSA3.58MG
Power Supply
Voltage [V]
8.0
30
CST8.00MTW
30
Unnecessary
(On-chip C type)
CSTS0800MG03
External circuit example
XIN
C1
XOUT
C2
Data Sheet U14380EJ3V0DS00
51
µPD64A, 65
12. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD vs. VDD (fX = 8 MHz)
(TA = 25°C)
1
1
0.9
0.9
Power supply current IDD [mA]
Power supply current IDD [mA]
IDD vs. VDD (fX = 4 MHz)
(TA = 25°C)
0.8
0.7
0.6
Operating mode
0.5
HALT mode
0.4
0.3
0.2
0.1
0
1.5
0.8
0.6
0.5
0.3
0.2
0.1
2
2.5
3
3.6
0
1.5
4
− 20
High-level output current IOH [mA]
25
Low-level output current IOL [mA]
2
2.5
3
3.6
4
Power supply voltage VDD [V]
IOL vs. VOL (REM, LED)
(TA = 25°C, VDD = 3.0 V)
20
15
10
5
IOH vs. VOH (REM, LED, KI/O)
(TA = 25°C, VDD = 3.0 V)
− 18
− 16
− 14
− 12
− 10
−8
−6
−4
−2
0
1
3
2
0
VDD
Low-level output voltage VOL [V]
500
450
400
350
300
250
200
150
100
50
0
1
2
Low-level output voltage VOL [V]
VDD − 1
VDD − 2
High-level output voltage VOH [V]
IOL vs. VOL (KI/O)
(TA = 25°C, VDD = 3.0 V)
Low-level output current IOL [µ A]
HALT mode
0.4
Power supply voltage VDD [V]
52
Operating mode
0.7
3
Data Sheet U14380EJ3V0DS00
VDD − 3
µPD64A, 65
13. APPLICATION CIRCUIT EXAMPLE
Example of application to system
·
Remote-control transmitter (48 keys; mode selection switch accommodated)
+
KI/O6
KI/O5
KI/O7
KI/O4
S0
KI/O3
S1/LED
KI/O2
REM
KI/O1
VDD
KI/O0
XOUT
KI3
XIN
KI2
GND
KI1
Note
KI0
S2
Mode selection
switch
Key matrix
8 × 6 = 48 keys
Note S2: Set this pin to disabled when releasing STOP mode.
·
Remote-control transmitter (56 keys accommodated)
+
KI/O6
KI/O5
KI/O7
KI/O4
S0
KI/O3
S1/LED
KI/O2
REM
KI/O1
VDD
KI/O0
XOUT
KI3
XIN
KI2
GND
KI1
S2
KI0
Key matrix
8 × 7 = 56 keys
Data Sheet U14380EJ3V0DS00
53
µPD64A, 65
14. PACKAGE DRAWING
20-PIN PLASTIC SSOP (7.62 mm (300))
20
11
detail of lead end
F
G
T
P
L
U
E
1
10
A
H
J
I
S
N
S
K
C
D
M
M
B
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
6.65±0.15
B
0.475 MAX.
C
0.65 (T.P.)
D
0.24 +0.08
−0.07
E
0.1±0.05
F
1.3±0.1
G
1.2
H
8.1±0.2
I
6.1±0.2
J
1.0±0.2
K
0.17±0.03
L
0.5
M
0.13
N
0.10
P
3° +5°
−3°
T
0.25
U
0.6±0.15
S20MC-65-5A4-2
Remark The external dimensions and material of the ES version are the same as those of the mass-produced
version.
54
Data Sheet U14380EJ3V0DS00
µPD64A, 65
15. RECOMMENDED SOLDERING CONDITIONS
The µPD64A and 65 should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Table 15-1. Surface Mounting Type Soldering Conditions
µ PD64AMC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))
µ PD65MC-×××-5A4:
Soldering Method
20-pin plastic SSOP (7.62 mm (300))
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, time: 30 seconds max. (210°C or higher),
count: three times or less
IR35-00-3
VPS
Package peak temperature: 215°C, time: 40 seconds max. (200°C or higher),
count: three times or less
VP15-00-3
Wave soldering
Solder bath temperature: 260°C max., time: 10 seconds max, count: once,
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., time: 3 seconds max. (per pin row)
—
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U14380EJ3V0DS00
55
µPD64A, 65
APPENDIX A. DEVELOPMENT TOOLS
Emulators are provided for the µPD64A and 65 emulation tools.
Hardware
• Emulators (EB-65, EB-69Note)
These are tools used to emulate the µPD64A and 65.
Note Products of Naito Densei Machida Mfg. Co., Ltd. For details, consult Naito Densei Machida Mfg. Co.,
Ltd. (+81-44-822-3813).
Software
• Assembler (AS6133)
• This is a development tool for remote control transmitter software.
Part Number List of AS6133
Host Machine
PC-9800 series
OS
Supply Medium
Part Number
MS-DOS (Ver. 5.0 to Ver. 6.2)
3.5-inch 2HD
µS5A13AS6133
MS-DOS (Ver. 6.0 to Ver. 6.22)
3.5-inch 2HC
µS7B13AS6133
(CPU: 80386 or more)
IBM PC/AT compatible
PC DOS (Ver. 6.1 to Ver. 6.3)
Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this
software.
56
Data Sheet U14380EJ3V0DS00
µPD64A, 65
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD64A, 65 AND OTHER PRODUCTS
µPD62
µPD62A
ROM capacity
512 × 10 bits
512 × 10 bits
RAM capacity
32 × 4 bits
Stack
1 level (multiplexed with RF of RAM)
Key matrix
8 × 6 = 48 keys
Key extended input
S0, S1
Clock frequency
Ceramic oscillation Ceramic oscillation
• fX = 2.4 to 8 MHz • fX = 2.4 to 8 MHz
• fX = 2.4 to 4 MHz
(with POC circuit)
Timer
Clock
fX/64, fX/128
Count start
Writing count value
Frequency
• fX/8, fX/64, fX/96 (timer clock: fX/64)
• fX/16, fX/128, fX/192 (timer clock: fX/128)
• No carrier
Item
Carrier
Output start
1002 × 10 bits
µPD64A
1002 × 10 bits
µPD65
2026 × 10 bits
8 × 7 = 56 keys
S0 , S1 , S2
Ceramic oscillation Ceramic oscillation
• fX = 2.4 to 8 MHz • fX = 2.4 to 8 MHz
• fX = 2.4 to 4 MHz
(with POC circuit)
Synchronized with timer
Instruction execution time
16 µs (fX = 4 MHz)
“MOV Rn, @R0” instruction
n = 1 to F
Standby mode Reset
RESET input, POC
Release
condition
(HALT
instruction)
µPD64
POC
• HALT mode for timer only.
• STOP mode for only releasing KI
(KI/O high-level output or KI/O0 high-level output)
Relationship between HALT
instruction execution and
status flag (F)
HALT instruction not executed when F = 1
POC circuit
• Mask option
• Low level output to RESET pin on detection
POC detection VPOC = 1.6 V (TYP.) VPOC = 1.85 V (TYP.) VPOC = 1.6 V (TYP.)
voltage
• Provided
• Generates internal reset signal on
detection
VPOC = 1.85 V (TYP.)
Mask option
POC circuit only
Supply voltage
• VDD = 1.8 to 3.6 V VDD = 2.0 to 3.6 V
• VDD = 2.2 to 3.6 V
(with POC circuit)
None
Operating ambient
temperature
• TA = –40 to +85°C • TA = –40 to +85°C • TA = –40 to +85°C TA = –40 to +85°C
• TA = –20 to +70°C
• TA = –20 to +70°C
(with POC circuit)
(with POC circuit)
Electrical specifications,
recommended soldering
conditions
Refer to the data sheet for each product.
Package
20-pin plastic SSOP
One-time PROM version
µPD6P4B
• VDD = 1.8 to 3.6 V VDD = 2.0 to 3.6 V
• VDD = 2.2 to 3.6 V
(with POC circuit)
• 20-pin plastic
SOP
• 20-pin plastic
SSOP
20-pin plastic SSOP
µPD6P5
Data Sheet U14380EJ3V0DS00
57
µPD64A, 65
APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT
(in the case of NEC transmission format in one-shot command transmission mode)
Caution When using the NEC transmission format, please apply for a custom code at NEC.
(1) REM output waveform (from <2> on, the output is made only when the key is kept pressed)
REM output
58.5 to 76.5 ms
<1>
108 ms
<2>
108 ms
Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can
be reduced by sending the reader code and the stop bit from the second time.
(2) Enlarged waveform of <1>
<3>
REM output
9 ms
4.5 ms
Custom code
8 bits
13.5 ms
Leader code
Custom code
8 bits
,
Data code
8 bits
18 to 36 ms
Data code
8 bits
Stop bit
1 bit
27 ms
58.5 to 76.5 ms
(3) Enlarged waveform of <3>
REM output
4.5 ms
9 ms
0.56 ms
1.125 ms 2.25 ms
0
1
13.5 ms
(4) Enlarged waveform of <2>
REM output
2.25 ms
9 ms
11.25 ms
Leader code
58
Data Sheet U14380EJ3V0DS00
0.56 ms
Stop bit
1
0
0
µPD64A, 65
(5) Carrier waveform (enlarged waveform of each code’s high period)
REM output
8.77 µ s
26.3 µ s
9 ms or 0.56 ms
Carrier frequency: 38 kHz
(6) Bit array of each code
C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
=
=
=
=
=
=
=
=
C0 C1 C2 C3 C4 C5 C6 C7
or or or or or or or or
Co C1 C2 C3 C4 C5 C6 C7
Leader code
Custom code
,
Custom code
Data code
Data code
Caution To prevent malfunction with other systems when receiving data in the NEC transmission
format, the total 32 bits of the 16-bit custom codes (Custom code, Custom code’) and the
16-bit data codes (Data code, Data code) must not only be fully decoded (make sure to check
Data code as well) but also checked to make sure that no signals are present.
Data Sheet U14380EJ3V0DS00
59
µPD64A, 65
[MEMO]
60
Data Sheet U14380EJ3V0DS00
µPD64A, 65
[MEMO]
Data Sheet U14380EJ3V0DS00
61
µPD64A, 65
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V DD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
62
Data Sheet U14380EJ3V0DS00
µPD64A, 65
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
Data Sheet U14380EJ3V0DS00
63
µPD64A, 65
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
PC/AT and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of September, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4