DATA SHEET MOS INTEGRATED CIRCUIT µPD784224, 784225, 784224Y, 784225Y 16/8-BIT SINGLE-CHIP MICROCONTROLLERS The µPD784224 and 784225 are products of the µPD784225 Subseries in the 78K/IV Series. Besides a highspeed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral hardware. The µPD784224Y and 784225Y are based on the µPD784225 Subseries with the addition of a multimastersupporting I2C bus interface. Flash memory versions, the µPD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM version with flash memory, and various development tools are also available. The functions are explained in detail in the following user’s manuals. Be sure to read this manual when designing your system. µPD784225, 784225Y Subseries User’s Manual - Hardware : U12697E 78K/IV Series User’s Manual - Instruction : U10905E FEATURES • I2C bus • Standby function • ROM correction HALT/STOP/IDLE mode • Inherits peripheral functions of µ PD780058Y In power-saving mode: HALT/IDLE mode (with subsystem clock) Subseries • Clock division function • Minimum instruction execution time 160 ns (main system clock fXX = 12.5 MHz) • Watch timer: 1 channel 61 µs (subsystem clock fXT = 32.768 kHz) • Watchdog timer: 1 channel • Clock output function • I/O port: 67 pins • Timer/counter: 16-bit timer/counter × 1 unit fXX, f XX/2, fXX/22, fXX/23 , fXX/24, fXX/25, f XX/26, fXX/27 , fXT 8-bit timer/counter × 4 units selectable • Buzzer output function • Serial interface: 3 channels fXX/210, fXX/211, fXX/212, fXX/213 selectable UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O, multi-master supporting I 2C • A/D converter: 8-bit resolution × 8 channels busNote): 1 channel • D/A converter: 8-bit resolution × 2 channels Note µPD784225Y Subseries only • Supply voltage: VDD = 1.8 to 5.5 V APPLICATION FIELD Car audio, portable audio, telephones, etc. Unless contextually excluded, references in this document to µPD784225 mean µPD784224, 784225, 784224Y, and 784225Y. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Document No. U12376EJ1V0DS00 (1st edition) Date Published May 2000 J CP(K) Printed in Japan The mark shows major revised points. © 1997, 2000 µPD784224, 784225, 784224Y, 784225Y ORDERING INFORMATION Part Number µPD784224GC-×××-8BT µPD784224GK-×××-9EUNote µPD784225GC-×××-8BT µPD784225GK-×××-9EU µPD784224YGC-×××-8BT µPD784224YGK-×××-9EU µPD784225YGC-×××-8BTNote µPD784225YGK-×××-9EUNote Package 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin plastic plastic plastic plastic plastic plastic plastic plastic QFP (14 × 14 mm) TQFP (fine pitch) (14 QFP (14 × 14 mm) TQFP (fine pitch) (14 QFP (14 × 14 mm) TQFP (fine pitch) (14 QFP (14 × 14 mm) TQFP (fine pitch) (14 Internal ROM (Bytes) Internal RAM (Bytes) × 20 mm) × 20 mm) × 20 mm) × 20 mm) Note Under development Remark ××× indicates a ROM code suffix. 2 Data Sheet U12376EJ1V0DS00 96 K 96 K 128 K 128 K 96 K 96 K 128 K 128 K 3,584 3,584 4,352 4,352 3,584 3,584 4,352 4,352 µPD784224, 784225, 784224Y, 784225Y 78K/IV SERIES LINEUP : In mass production : Under development Supports I2C bus µ PD784038Y µ PD784038 Standard models µ PD784026 Enhanced A/D converter, 16-bit timer, and power management Enhanced internal memory capacity Pin-compatible with the µ PD784026 Supports multi-master I2C bus µ PD784225Y µ PD784225 80-pin, ROM correction added Supports multi-master I2C bus Supports multi-master I2C bus µPD784216AY µPD784218AY µ PD784216A 100-pin, enhanced I/O and internal memory capacity µ PD784218A Enhanced internal memory capacity, ROM correction added µPD784054 µPD784046 ASSP models On-chip 10-bit A/D converter µ PD784956A For DC inverter control µ PD784908 On-chip IEBusTM controller µ PD784938A Enhanced functions of the µ PD784908, enhanced internal memory capacity, ROM correction added. Supports multi-master I2C bus µ PD784928Y µPD784915 Software servo control On-chip analog circuit for VCRs Enhanced timer µ PD784928 Enhanced functions of the µ PD784915 µ PD784967 On-chip FIP controller/driver Data Sheet U12376EJ1V0DS00 3 µPD784224, 784225, 784224Y, 784225Y FUNCTIONS Part Number Item Number of basic instructions (mnemonics) µPD784224, µPD784225, µPD784224Y µPD784225Y 113 General-purpose register 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) Minimum instruction execution time • 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: fXX = 12.5 MHz) • 61 µs (subsystem clock: fXT = 32.768 kHz) Internal memory ROM 96 Kbytes 128 Kbytes RAM 3,584 bytes 4,352 bytes Memory space I/O port Pins with ancillary 1 MB with program and data spaces combined Total 67 CMOS Input 8 CMOS I/O 59 Pins with pull-up resistor 57 functionsNote 1 LEDs direct drive output 16 Real-time output port 4 bits × 2, or 8 bits × 1 Timer Timer/event counter (16-bit) : Timer counter × 1 Capture/compare register × 2 Pulse output • PWM/PPG output • Square wave output • One-shot pulse output Timer/event counter 1 : Timer counter × 1 (8-bit) Compare register × 1 Pulse output • PWM output • Square wave output Timer/event counter 2 : Timer counter × 1 (8-bit) Compare register × 1 Pulse output • PWM output • Square wave output Timer 5 (8-bit) : Timer counter × 1 Compare register × 1 Timer 6 (8-bit) : Timer counter × 1 Compare register × 1 Serial interface • UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) • CSI (3-wire serial I/O, I2C busNote 2 supporting multi master): 1 channel A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Clock output Selectable from fXX, fXX /2, fXX /22, fXX /23, fXX /24, fXX /25 , fXX/26 , fXX/27, fXT Buzzer output Selectable from fXX /210, fXX /211, fXX/212, fXX/213 Watch timer 1 channel Watchdog timer 1 channel Standby • HALT/STOP/IDLE mode • In power-saving mode (with subsystem clock): HALT/IDLE mode Interrupt Hardware 25 (internal: 18, external: 7) Software BRK instruction, BRKCS instruction, operand error Non-maskable Internal: 1, external: 1 Maskable Internal: 17, external: 6 • 4 programmable priority levels • 3 service modes: vectored interrupt/macro service/context switching Supply voltage VDD = 1.8 to 5.5 V Package • 80-pin plastic QFP(14 × 14 mm) • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Notes 1. The pins with ancillary functions are included in the I/O pins. 2. µPD784225Y Subseries only 4 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y CONTENTS 1. DIFFERENCES AMONG MODELS IN µPD784225, 784225Y SUBSERIES .............................. 7 2. MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES AND µPD780058Y SUBSERIES ............................................................................................................. 8 3. PIN CONFIGURATION (Top View) ............................................................................................... 9 4. BLOCK DIAGRAM ........................................................................................................................ 11 5. PIN FUNCTION ............................................................................................................................... 12 6. 7. 5.1 Port Pins ................................................................................................................................................ 12 5.2 Pins Other Than Port Pins .................................................................................................................. 14 5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 16 CPU ARCHITECTURE ................................................................................................................... 20 6.1 Memory Space ...................................................................................................................................... 20 6.2 CPU Registers ...................................................................................................................................... 23 6.2.1 General-purpose registers .......................................................................................................... 23 6.2.2 Control registers .......................................................................................................................... 24 6.2.3 Special function registers (SFRs) ............................................................................................... 25 PERIPHERAL HARDWARE FUNCTIONS .................................................................................... 30 7.1 Ports ....................................................................................................................................................... 30 7.2 Clock Generator ................................................................................................................................... 31 7.3 Real-Time Output Port ......................................................................................................................... 33 7.4 Timer ...................................................................................................................................................... 34 7.5 A/D Converter ....................................................................................................................................... 37 7.6 D/A Converter ....................................................................................................................................... 38 7.7 Serial Interface ..................................................................................................................................... 39 7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 40 7.7.2 Clocked serial interface (CSI) ..................................................................................................... 42 7.8 Clock Output Function ........................................................................................................................ 43 7.9 Buzzer Output Function ...................................................................................................................... 44 7.10 Edge Detection Function .................................................................................................................... 44 7.11 Watch Timer .......................................................................................................................................... 44 7.12 Watchdog Timer ................................................................................................................................... 45 8. INTERRUPT FUNCTION ................................................................................................................ 46 8.1 Interrupt Sources ................................................................................................................................. 46 8.2 Vectored Interrupt ................................................................................................................................ 48 8.3 Context Switching ................................................................................................................................ 49 8.4 Macro Service ....................................................................................................................................... 49 8.5 Application Example of Macro Service ............................................................................................. 50 Data Sheet U12376EJ1V0DS00 5 µPD784224, 784225, 784224Y, 784225Y 9. LOCAL BUS INTERFACE ............................................................................................................. 51 9.1 Memory Expansion .............................................................................................................................. 51 9.2 Programmable Wait ............................................................................................................................. 51 9.3 External Access Status Function ...................................................................................................... 51 10. STANDBY FUNCTION ................................................................................................................... 52 11. RESET FUNCTION ......................................................................................................................... 54 12. ROM CORRECTION ...................................................................................................................... 55 13. INSTRUCTION SET ........................................................................................................................ 56 14. ELECTRICAL SPECIFICATIONS ................................................................................................. 61 15. PACKAGE DRAWINGS ................................................................................................................. 82 16. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 84 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 85 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 88 6 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 1. DIFFERENCES AMONG MODELS IN µPD784225, 784225Y SUBSERIES The only difference among the µPD784224 and 784225 lies in the internal memory capacity. The µPD784224Y and 784225Y are based on the µPD784224 and 784225 respectively, with the addition of an I2C bus control function. The µPD78F4225 and 78F4225Y are provided with a 128-Kbyte flash memory instead of the mask ROM of the above models. These differences are summarized in Table 1-1. Table 1-1. Differences among Models in µPD784225, 784225Y Subseries µPD784224, µPD784224Y Part Number Item µPD784225, µPD784225Y Internal ROM 96 Kbytes (mask ROM) 128 Kbytes (mask ROM) Internal RAM 3,584 bytes 4,352 bytes µPD78F4225, µPD78F4225Y 128 Kbytes (Flash memory) Internal memory None size switching register (IMS)Note Provided Supply voltage VDD = 1.8 to 5.5 V VDD = 1.9 to 5.5 V Electrical specifications Refer to the data sheet for each device. Recommended soldering conditions TEST pin Provided None VPP pin None Provided Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version. Data Sheet U12376EJ1V0DS00 7 µPD784224, 784225, 784224Y, 784225Y 2. MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES AND µPD780058Y SUBSERIES Series Name Item CPU µPD784225, 784225Y Subseries µPD784216Y Subseries 16-bit CPU 8-bit CPU Minimum instruction With main system clock selected 160 ns (at 12.5 MHz) 400 ns (at 5.0 MHz) execution time With subsystem clock 61 µs (at 32.768 kHz) 122 µs (at 32.768 kHz) 1 Mbytes 64 Kbytes Memory space I/O port Total 67 pins 86 pins 68 pins CMOS input 8 pins 8 pins 2 pins CMOS I/O 59 pins 72 pins 62 pins 6 pins 4 pins − N-ch open-drain I/O Pins with ancillary functionNote 1 Pins with pull-up resistor 57 pins 70 pins 66 pins (flash memory model: 62 pins) LED direct drive output 16 pins 22 pins 12 pins 6 pins 4 pins • 16-bit timer/event counter × 1 unit • 8-bit timer/event counter • 16-bit timer/event counter × 1 unit • 8-bit timer/event counter − Medium-voltage pin Timer/counter • 16-bit timer/event counter × 1 unit • 8-bit timer/event counter × 4 units Interrupt × 6 units × 2 units • UART/IOE (3-wire serial I/O) × 2 channels • CSI (3-wire serial I/O, multi-master supporting I2C busNote 2) × 1 channel • UART (time-division transfer function)/IOE (3-wire serial I/O) × 2 channels • CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) × 1 channel • CSI (3-wire serial I/O with automatic transmission/reception function) × 1 channel NMI pin Provided None Macro service Provided None Context switching Provided None Serial interface Programmable priority 4 levels 2 levels Standby function • HALT/STOP/IDLE mode • Power-saving mode: HALT/IDLE Mode HALT/STOP mode ROM correction Provided None Provided Package • 80-pin plastic QFP (14 × 14 mm) • 100-pin plastic QFP (fine pitch) (14 × 14 mm) • 80-pin plastic QFP (14 × 14 mm) • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) • 100-pin plastic QFP (14 × 20 mm) • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Notes 1. Pins with ancillary function are included in the I/O pins. 2. µPD784225Y and 784216Y Subseries only 8 µPD780058Y Subseries Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 3. PIN CONFIGURATION (Top View) • 80-pin plastic QFP (14 × 14 mm) µPD784224GC-×××-8BT, µPD784224YGC-×××-8BT, µPD784225GC-×××-8BT, µPD784225YGC-×××-8BT • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD784224GK-×××-BE9, µPD784224YGK-×××-BE9, P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2/NMI P01/INTP1 P00/INTP0 VSS0 X1 X2 VDD1 XT1 XT2 TESTNote 2 RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RPT2 P121/RTP1 P120/RTP0 P37/EXA P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR P56/A14 P57/A15 P60/A16 P61/A17 P62/A18 P63/A19 P64/RD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS1 P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD2 P71/SO2/TxD2 P72/SCK2/ASCK2 P20/SI1/RxD1 P21/SO1/TxD1 P22/SCK1/ASCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note 1 P26/SO0 P27/SCK0/SCL0Note 1 P40/AD0 P41/AD1 VDD0 A14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVDD µPD784225GK-×××-BE9, µPD784225YGK-×××-BE9 Notes 1. The SCL0 and SDA0 pins are available in µPD784225Y Subseries only. 2. Connect the TEST pin to VSS0 directly or via a pull-down resistor. For the pull-down connection, use of a resistor with a resistance ranging from 470 Ω to 10 kΩ is recommended. Caution Connect the AVSS pin to VSS0. Remark When using in applications where noise from inside the microcomputer has to be reduced, it is recommended to take countermeasures against noise such as supplying power to VDD0 and VDD1 independently, and connecting VSS0 and VSS1 to different ground lines. Data Sheet U12376EJ1V0DS00 9 µPD784224, 784225, 784224Y, 784225Y A8 to A19 : Address Bus P130, P131 AD0 to AD7 : Address/Data Bus PCL : Programmable Clock ANI0 to ANI7 : Analog Input RD : Read Strobe ANO0, ANO1 : Analog Output RESET : Reset ASCK1, ASCK2 : Asynchronous Serial Clock RTP0 to RTP7 : Real-time Output Port ASTB : Address Strobe RxD1, RxD2 : Receive Data AVDD : Analog Power Supply SCK0 to SCK2 : Serial Clock AVREF1 : Analog Reference Voltage SCL0Note : Serial Clock AVSS : Analog Ground SDA0 Note : Serial Data BUZ : Buzzer Clock SI0 to SI2 : Serial Input EXA : External Access Status Output SO0 to SO2 : Serial Output INTP0 to INTP5 : Interrupt from Peripherals TEST : Test NMI : Non-maskable Interrupt TI00, TI01, TI1, TI2 : Timer Input P00 to P05 : Port0 TO0 to TO2 : Timer Output P10 to P17 : Port1 TxD1, TxD2 : Transmit Data P20 to P27 : Port2 VDD0, VDD1 : Power Supply P30 to P37 : Port3 VSS0, VSS1 : Ground P40 to P47 : Port4 WAIT : Wait P50 to P57 : Port5 WR : Write Strobe P60 to P67 : Port6 X1, X2 : Crystal (Main System Clock) P70 to P72 : Port7 XT1, XT2 : Crystal (Subsystem Clock) P120 to P127 : Port12 Note The SCL0 and SDA0 pins are available in µPD784225Y Subseries only. 10 Data Sheet U12376EJ1V0DS00 : Port13 µPD784224, 784225, 784224Y, 784225Y 4. BLOCK DIAGRAM INTP2/NMI INTP0, INTP1, INTP3 to INTP5 PROGRAMMABLE INTERRUPT CONTROLLER UART/IOE1 BAUD-RATE GENERATOR TI00 TI01 TO0 TIMER/EVENT COUNTER (16 BITS) UART/IOE2 BAUD-RATE GENERATOR TI1 TO1 TIMER/EVENT COUNTER1 (8 BITS) CLOCKED SERIAL INTERFACE TI2 TO2 TIMER/EVENT COUNTER2 (8 BITS) RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0Note SO0 SCK0/SCL0Note AD0 to AD7 A8 to A15 A16 to A19 TIMER/COUNTER5 (8 BITS) 78K/IV CPU CORE BUS I/F RD WR WAIT ASTB EXA PORT0 P00 to P05 PORT1 P10 to P17 PORT2 P20 to P27 PORT3 P30 to P37 PORT4 P40 to P47 PORT5 P50 to P57 PORT6 P60 to P67 PORT7 P70 to P72 PORT12 P120 to P127 PORT13 P130, P131 ROM TIMER/COUNTER6 (8 BITS) WATCH TIMER WATCHDOG TIMER RAM RTP0 to RTP7 NMI/INTP2 REAL-TIME OUTPUT PORT ANO0 ANO1 AVREF1 AVSS D/A CONVERTER ANI0 to ANI7 AVDD AVSS P03/INTP3 A/D CONVERTER PCL RESET X1 CLOCK OUTPUT CONTROL SYSTEM CONTROL X2 XT1 BUZ BUZZER OUTPUT XT2 VDD0, VDD1 VSS0, VSS1 TEST Note This function supports the I2C bus interface and is available in µPD784225Y Subseries only. Remark The internal ROM and RAM capacities differ depending on the model. Data Sheet U12376EJ1V0DS00 11 µPD784224, 784225, 784224Y, 784225Y 5. PIN FUNCTION 5.1 Port Pins (1/2) Pin Name P00 I/O I/O Alternate Function INTP0 P01 INTP1 P02 INTP2/NM1 P03 INTP3 P04 INTP4 P05 INTP5 P10 to P17 P20 Input I/O Port 1 (P1): • 8-bit input port RxD1/SI1 Port 2 (P2): • 8-bit I/O port • Can be set in input or output mode bit-wise. • Pins set in input mode can be connected to internal pull-up resistors by software bit-wise. TxD1/SO1 P22 ASCK1/SCK1 P23 PCL P24 BUZ P25 SI0/SDA0Note P26 SO0 P27 SCK0/SCL0Note I/O Port 0 (P0): • 6-bit I/O port • Can be set in input or output mode bit-wise. • Pins set in input mode can be connected to internal pull-up resistors by software bit-wise. ANI0 to ANI7 P21 P30 Function TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 TI00 P36 TI01 P37 EXA Port 3 (P3): • 8-bit I/O port • Can be set in input or output mode bit-wise. • Pins set in input mode can be connected to internal pull-up resistors by software bit-wise. P40 to P47 I/O AD0 to AD7 Port 4 (P4): • 8-bit I/O port • Can be set in input or output mode bit-wise. • All pins set in input mode can be connected to internal pull-up resistors by software. • Can drive LEDs. P50 to P57 I/O A8 to A15 Port 5 (P5): • 8-bit I/O port • Can be set in input or output mode bit-wise. • All pins set in input mode can be connected to internal pull-up resistors by software. • Can drive LEDs. Note This function is available in µPD784255Y Subseries only. 12 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 5.1 Port Pins (2/2) Pin Name P60 I/O I/O Alternate Function A16 P61 A17 P62 A18 P63 A19 P64 RD P65 WR P66 WAIT P67 ASTB P70 I/O RxD2/SI2 P71 TxD2/SO2 P72 ASCK2/SCK2 Function Port 6 (P6): • 8-bit I/O port • Can be set in input or output mode bit-wise. • All pins set in input mode can be connected to internal pull-up resistors by software. Port 7 (P7): • 3-bit I/O port • Can be set in input or output mode bit-wise. • Pins set in input mode can be connected to internal pull-up resistor by software bit-wise. P120 to P127 I/O RTP0 to RTP7 Port 12 (P12): • 8-bit I/O port • Can be set in input or output mode bit-wise. • Pins set in input mode can be connected to internal pull-up resistor by software bit-wise. P130, P131 I/O ANO0, ANO1 Port 13 (P13): • 2-bit I/O port • Can be set in input or output mode bit-wise. Data Sheet U12376EJ1V0DS00 13 µPD784224, 784225, 784224Y, 784225Y 5.2 Pins Other Than Port Pins (1/2) Pin Name TI00 I/O Function P35 External count clock input to 16-bit timer register TI01 P36 Capture trigger signal input to capture/compare register 00 TI1 P33 External count clock input to 8-bit timer register 1 TI2 P34 External count clock input to 8-bit timer register 2 P30 16-bit timer output (shared by 14-bit PWM output) TO1 P31 8-bit timer output (shared by 8-bit PWM output) TO2 P32 TO0 RxD1 Input Alternate Function Output Input P20/SI1 Serial data input (UART1) P70/SI2 Serial data input (UART2) P21/SO1 Serial data output (UART1) P71/SO2 Serial data output (UART2) P22/SCK1 Baud rate clock input (UART1) ASCK2 P72/SCK2 Baud rate clock input (UART2) SI0 P25/SDA0Note Serial data input (3-wire serial clock I/O0) SI1 P20/RxD1 Serial data input (3-wire serial clock I/O1) SI2 P70/RxD2 Serial data input (3-wire serial clock I/O2) P26 Serial data output (3-wire serial I/O0) SO1 P21/TxD1 Serial data output (3-wire serial I/O1) SO2 P71/TxD2 Serial data output (3-wire serial I/O2) RxD2 TxD1 Output TxD2 ASCK1 SO0 Intput Input Output SDA0Note I/O P25/SI0 Serial data input/output (I2C bus) SCK0 I/O P27/SCL0Note Serial clock input/output (3-wire serial I/O0) SCK1 P22/ASCK1 Serial clock input/output (3-wire serial I/O1) SCK2 P72/ASCK2 Serial clock input/output (3-wire serial I/O2) SCL0Note P27/SCK0 Serial clock input/output (I2C bus) P02/INTP2 Non-maskable interrupt request input INTP0 P00 External interrupt request input INTP1 P01 INTP2 P02/NMI INTP3 P03 INTP4 P04 INTP5 P05 NMI Input PCL Output P23 Clock output (for trimming main system clock and subsystem clock) BUZ Output P24 Buzzer output RTP0 to RTP7 Output P120 to P127 Real-time output port that outputs data in synchronization with trigger I/O P40 to P47 Low-order address/data bus when external memory is connected Output P50 to P57 Middle-order address bus when external memory is connected P60 to P63 High-order address bus when external memory is connected AD0 to AD7 A8 to A15 A16 to A19 Note This function is available in µPD784255Y Subseries only. 14 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 5.2 Pins Other Than Port Pins (2/2) Pin Name RD I/O Output WR Alternate Function Function P64 Strobe signal output for read operation of external memory P65 Strobe signal output for write operation of external memory WAIT Input P66 To insert wait state(s) when external memory is accessed ASTB Output P67 Strobe output to externally latch address information output to ports 4 to 6 to access external memory EXA Output P37 External access status output RESET Input − System reset input X1 Input − To connect main system clock oscillation crystal X2 − − To connect subsystem clock oscillation crystal XT1 Input XT2 − ANI0 to ANI7 Input P10 to P17 Analog voltage input for A/D converter ANO0, ANO1 Output P130, P131 Analog voltage output for D/A converter AVREF1 − − To apply reference voltage for D/A converter AVDD Positive power supply for A/D converter. Connected to VDD0. AVSS GND for A/D converter and D/A converter. Connected to VSS0. VDD0 Positive power supply for port block VSS0 GND potential for port block VDD1 Positive power supply (except port block) VSS1 GND potential (except port block) TEST Connect this pin to VSS0 directly or via pull-down resistor. For the pull-down connection, use of a resistor with a resistance ranging from 470 Ω to 10 kΩ is recommended. Data Sheet U12376EJ1V0DS00 15 µPD784224, 784225, 784224Y, 784225Y 5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins Table 5-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection of unused pins. For the circuit diagram of each type of I/O circuit, refer to Figure 5-1. Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2) Pin Name P00/INTP0 I/O Circuit Type I/O 8-K I/O Recommended Connections of Unused Pins Input : Individually connected to VSS0 via resistor Output: Open P01/INTP1 P02/INTP2/NMI P03/INTP3 to P05/INTP5 P10/ANI0 to P17/ANI7 9 P20/RxD1/SI1 10-I P21/TxD1/SO1 10-J P22/ASCK1/SCK1 10-I P23/PCL 10-J Input I/O Connected to VSS0 or VDD0 Input : Individually connected to VSS0 via resistor Output: Open P24/BUZ P25/SDA0Note/SI0 10-I P26/SO0 10-J P27/SCL0Note/SCK0 10-I P30/TO0 to P32/TO2 8-M P33/TI1, P34/TI2 8-K P35/TI00, P36/TI01 8-L P37/EXA 8-M P40/AD0 to P47/AD7 5-H P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 8-K P71/TxD2/SO2 8-L P72/ASCK2/SCK2 8-K Note This function is available in µPD784255Y Subseries only. Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided). 16 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (2/2) Pin Name I/O Circuit Type I/O P120/RTP0 to P127/RTP7 8-K I/O P130/ANO0, P131/ANO1 12-D RESET 2-G XT1 16 Input : Individually connected to VSS0 via resistor Output: Open − Input Connected to VSS0 − XT2 − AVREF1 Recommended Connections of Unused Pins Open Connected to VDD0 AVDD AVSS Connected to VSS0 TEST/VPPNote Directly connected to VSS0 Note VPP pin is available in µPD78F4225, 78F4255Y only. Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided). Data Sheet U12376EJ1V0DS00 17 µPD784224, 784225, 784224Y, 784225Y Figure 5-1. Types of Pin I/O Circuits (1/2) Type 2-G Type 8-M VDD0 pullup enable P-ch VDD0 IN data P-ch IN/OUT Schmitt trigger input with hysteresis characteristics output disable N-ch VSS0 input enable Type 9 VDD0 Type 5-H pullup enable P-ch IN VDD0 data P-ch + − VREF (threshold voltage) IN/OUT output disable Comparator P-ch N-ch N-ch input enable VSS0 input enable Type 8-K Type 10-I VDD0 pullup enable pullup enable P-ch P-ch VDD0 VDD0 data VDD0 data P-ch P-ch IN/OUT IN/OUT output disable open drain output disable N-ch N-ch VSS0 VSS0 Type 8-L Type 10-J VDD0 pullup enable pullup enable P-ch VDD0 data VDD0 P-ch VDD0 data P-ch P-ch IN/OUT open drain output disable N-ch IN/OUT open drain output disable VSS0 18 N-ch VSS0 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Figure 5-1. Types of Pin I/O Circuits (2/2) Type 12-D VDD0 data P-ch IN/OUT output disable N-ch VSS0 input enable P-ch Analog output voltage N-ch VSS0 Type 16 feedback cut-off P-ch XT1 XT2 Data Sheet U12376EJ1V0DS00 19 µPD784224, 784225, 784224Y, 784225Y 6. CPU ARCHITECTURE 6.1 Memory Space A memory space of 1 Mbyte can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after RESET cancellation, and must not be used more than once. (1) When LOCATION 0H instruction is executed • Internal memory The internal data area and internal ROM area are mapped as follows: Part Number Caution Internal Data Area Internal ROM Area µPD784224, µPD784224Y 0F100H to 0FFFFH 00000H to 0F0FFH 10000H to 17FFFH µPD784225, µPD784225Y 0EE00H to 0FFFFH 00000H to 0EDFFH 10000H to 1FFFFH The following areas that overlap the internal data area of the internal ROM cannot be used when the LOCATION 0H instruction is executed. Part Number Unusable Area µPD784224, µPD784224Y 0F100H to 0FFFFH (3,840 bytes) µPD784225, µPD784225Y 0EE00H to 0FFFFH (4,608 bytes) • External memory The external memory is accessed in external memory expansion mode. (2) When LOCATION 0FH instruction is executed • Internal memory The internal data area and internal ROM area are mapped as follows: Part Number Internal Data Area Internal ROM Area µPD784224, µPD784224Y FF100H to FFFFFH 00000H to 17FFFH µPD784225, µPD784225Y FEE00H to FFFFFH 00000H to 1FFFFH • External memory The external memory is accessed in external memory expansion mode. 20 Data Sheet U12376EJ1V0DS00 Internal ROM Data Sheet U12376EJ1V0DS00 Internal ROM (61,696 bytes) Note 4 0 0 0 0 0H 0 0 0 4 0H 0 0 0 3 FH 0 0 0 8 0H 0 0 0 7 FH 0 0 8 0 0H 0 0 7 F FH 0 1 0 0 0H 0 0 F F FH 0 F 0 F FH Note 3 Vector table area (64 bytes) CALLT table area (64 bytes) CALLF entry area (2 Kbytes) Program/data area Note 2 1 7 F F FH 1 7 F F FH 1 0 0 0 0H F FD0 0H F FCF FH FFE0 6H FFE3 9H FFE8 0H F FE 7 FH FF 7 0 0H Program/data area (3,072 bytes) Data area (512 bytes) Macro service control word area (52 bytes) General-purpose registers (128 bytes) F FEF FH 0 F 1 0 0H 0 FD0 0H 0 FCF FH 0 FE0 6H 0 FE3 9H 0 FE8 0H 0 FE 7 FH 0 FEF FH 0 0 0 0 0H 1 8 0 0 0H 1 7 F F FH FF 1 0 0H F F 0 F FH (256 bytes) Internal ROM (96 Kbytes) External memory (980,736 bytes) 21 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. 3. On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes Note 4 Note 1 function registers (SFR) Internal RAM (3,584 bytes) F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH On execution of LOCATION 0FH instruction 2. This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. Notes 1. Accessed in external memory expansion mode. 0 0 0 0 0H 0 F 1 0 0H 0 F 0 F FH Internal RAM (3,584 bytes) (SFR) Note 1 External memory (928 Kbytes) (32,768 bytes) 1 0 0 0 0H 0 F F F FH Special function registers 0 F FDFH Note 1 0 F FD0H (256 bytes) 0 FF 0 0H 0 FEF FH 1 8 0 0 0H 1 7 F F FH F F F F FH On execution of LOCATION 0H instruction Figure 6-1. Memory Map of µPD784224, 784224Y µPD784224, 784225, 784224Y, 784225Y 22 Data Sheet U12376EJ1V0DS00 Internal ROM (60,928 bytes) Note 4 0 0 0 0 0H 0 0 0 4 0H 0 0 0 3 FH 0 0 0 8 0H 0 0 0 7 FH 0 0 8 0 0H 0 0 7 F FH 0 1 0 0 0H 0 0 F F FH 0 EDF FH Note 3 Vector table area (64 bytes) CALLT table area (64 bytes) CALLF entry area (2 Kbytes) Program/data area Note 2 1 F F F FH 1 F F F FH 1 0 0 0 0H F FD0 0H F FCF FH FFE0 6H FFE3 9H FFE8 0H F FE 7 FH FEE 0 0H Program/data area (3,840 bytes) Data area (512 bytes) Macro service control word area (52 bytes) General-purpose registers (128 bytes) F FEF FH 0 EE 0 0H 0 FD0 0H 0 FCF FH 0 FE0 6H 0 FE3 9H 0 FE8 0H 0 FE 7 FH 0 FEF FH 0 0 0 0 0H 2 0 0 0 0H 1 F F F FH FEE 0 0H F EDF FH (256 bytes) Internal ROM (128 Kbytes) External memory (912,896 bytes) 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. 3. On execution of LOCATION 0H instruction: 126,464 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes Note 4 Note 1 function registers (SFR) Internal RAM (4,352 bytes) F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH On execution of LOCATION 0FH instruction 2. This 4,608-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. Notes 1. Accessed in external memory expansion mode. 0 0 0 0 0H 0 EE 0 0H 0 EDF FH Internal RAM (4,352 bytes) (256 bytes) function registers (SFR) Internal ROM (65,536 bytes) Note 1 External memory (896 Kbytes) 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH 2 0 0 0 0H 1 F F F FH F F F F FH On execution of LOCATION 0H instruction Figure 6-2. Memory Map of µPD784225, 784225Y µPD784224, 784225, 784224Y, 784225Y µPD784224, 784225, 784224Y, 784225Y 6.2 CPU Registers 6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers. Eight banks of these registers are available which can be selected by using software or the context switching function. The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-3. General-Purpose Register Format A (R1) X (R0) AX (RP0) B (R3) C (R2) BC (RP1) R5 R4 RP2 R7 R6 RP3 V R9 VP (RP4) VVP (RG4) U R8 R11 R10 T UP (RP5) UUP (RG5) D (R13) E (R12) W DE (RP6) TDE (RG6) H (R15) L (R14) 8 banks HL (RP7) WHL (RG7) Parentheses ( Caution ) indicate an absolute name. Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series. Data Sheet U12376EJ1V0DS00 23 µPD784224, 784225, 784224Y, 784225Y 6.2.2 Control registers (1) Program counter (PC) The program counter is a 20-bit register whose contents are automatically updated when the program is executed. Figure 6-4. Program Counter (PC) Format 19 0 PC (2) Program status word (PSW) This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed. Figure 6-5. Program Status Word (PSW) Format PSWH 15 14 13 12 11 10 9 8 UF RBS2 RBS1 RBS0 – – – – 7 6 5 4 3 2 1 0 AC IE P/V 0 CY PSW PSWL S Z RSS Note Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when the software for the 78K/III Series is used. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer. Figure 6-6. Stack Pointer (SP) Format 23 PC 24 0 20 0 0 0 0 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 6.2.3 Special function registers (SFRs) The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space of addresses 0FF00H to 0FFFFHNote. Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH instruction. Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by mistake, the µPD784225 may be in the deadlock status. This deadlock status can be cleared only by inputting the RESET signal. Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: • Symbol ............................... Symbol indicating an SFR. This symbol is reserved for NEC’s assembler (RA78K4). It can be used an sfr variable by the #pragma sfr directive with the C compiler (CC78K4). • R/W .................................... Indicates whether the SFR is read-only, write-only, or read/write. R/W : Read/write R : Read-only W : Write-only • Bit units for manipulation .. Bit units in which the value of the SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. • At reset .............................. Indicates the status of the register when the RESET signal has been input. Data Sheet U12376EJ1V0DS00 25 µPD784224, 784225, 784224Y, 784225Y Table 6-1. Special Function Register (SFR) List (1/4) AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 8 Bits At Reset 16 Bits 0FF00H Port 0 P0 R/W — 0FF01H Port 1 P1 R — 0FF02H Port 2 P2 R/W — 0FF03H Port 3 P3 — 0FF04H Port 4 P4 — 0FF05H Port 5 P5 — 0FF06H Port 6 P6 — 0FF07H Port 7 P7 — 0FF0CH Port 12 P12 — 0FF0DH Port 13 P13 0FF10H 16-bit timer counter TM0 R — — 0FF12H Capture/compare register 00 CR00 R/W — — 0FF13H (16-bit timer/counter) — — 00HNote 2 — 0000H 0FF11H 0FF14H Capture/compare register 01 0FF15H (16-bit timer/counter) CR01 0FF16H Capture/compare control register 0 CRC0 — 0FF18H 16-bit timer mode control register TMC0 — 0FF1AH 16-bit timer output control register TOC0 — 0FF1CH Prescaler mode register 0 PRM0 — 0FF20H Port 0 mode register PM0 — 0FF22H Port 2 mode register PM2 — 0FF23H Port 3 mode register PM3 — 0FF24H Port 4 mode register PM4 — 0FF25H Port 5 mode register PM5 — 0FF26H Port 6 mode register PM6 — 0FF27H Port 7 mode register PM7 — 0FF2CH Port 12 mode register PM12 — 0FF2DH Port 13 mode register PM13 — 0FF30H Pull-up resistor option register 0 PU0 — 0FF32H Pull-up resistor option register 2 PU2 — 0FF33H Pull-up resistor option register 3 PU3 — 0FF37H Pull-up resistor option register 7 PU7 — 0FF3CH Pull-up resistor option register 12 PU12 — 0FF40H Clock output control register CKS — 00H FFH 00H Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. 2. Because each port is initialized to input mode at reset, “00H” is not actually read. The output latch is initialized to “0”. 26 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Table 6-1. Special Function Register (SFR) List (2/4) AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit R/W 16 Bits 0FF42H Port function control register 0FF4EH Pull-up resistor option register PUO 0FF50H 8-bit timer counter 1 TM1 0FF51H 8-bit timer counter 2 TM2 0FF52H Compare register 10 (8-bit timer/counter 1) CR10 CR1W 0FF53H Compare register 20 (8-bit timer/counter 2) CR20 0FF54H 8-bit timer mode control register 1 TMC1 TMC1W 0FF55H 8-bit timer mode control register 2 TMC2 0FF56H Prescaler mode register 1 PRM1 PRM1W 0FF57H Prescaler mode register 2 PRM2 0FF60H 8-bit timer counter 5 TM5 TM5W R — 0FF61H 8-bit timer counter 6 TM6 — 0FF64H Compare register 50 (8-bit timer/counter 5) CR50 CR5W 0FF65H Compare register 60 (8-bit timer/counter 6) CR60 0FF68H 8-bit timer mode control register 5 TMC5 TMC5W 0FF69H 8-bit timer mode control register 6 TMC6 0FF6CH Prescaler mode register 5 PRM5 PRM5W 0FF6DH Prescaler mode register 6 PRM6 0FF70H Asynchronous serial interface mode register 1 ASIM1 — 0FF71H Asynchronous serial interface mode register 2 ASIM2 — 0FF72H Asynchronous serial interface status register 1 ASIS1 0FF73H Asynchronous serial interface status register 2 ASIS2 0FF74H Transmit shift register 1 TXS1 W — — Receive buffer register 1 RXB1 R — — Transmit shift register 2 TXS2 W — — Receive buffer register 2 RXB2 R — — 0FF76H Baud rate generator control register 1 BRGC1 R/W 0FF77H Baud rate generator control register 2 BRGC2 — 0FF7AH Oscillation mode select register CC — 0FF80H A/D converter mode register ADM — 0FF81H A/D converter input select register ADIS 0FF83H A/D conversion result register ADCR R 0FF84H D/A conversion value setting register 0 DACS0 R/W 0FF85H D/A conversion value setting register 1 DACS1 — 0FF86H D/A converter mode register 0 DAM0 — 0FF87H D/A converter mode register 1 DAM1 — 0FF75H PF2 8 Bits At Reset — 00H — TM1W R — 0000H — R/W — — R/W — — R 00H — — — FFH 00H — — — Undefined — 00H Note When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. Data Sheet U12376EJ1V0DS00 27 µPD784224, 784225, 784224Y, 784225Y Table 6-1. Special Function Register (SFR) List (3/4) AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit 0FF88H ROM correction control register CORC 8 Bits R/W At Reset 16 Bits — 00H 0FF89H ROM correction address pointer H CORAH — 0FF8AH ROM correction address pointer L CORAL — — 0FF8DH External access status enable register EXAE — 0FF90H Serial operation mode register 0 CSIM0 — 0FF91H Serial operation mode register 1 CSIM1 — 0FF92H Serial operation mode register 2 CSIM2 — 0FF94H Serial I/O shift register 0 SIO0 — — 0FF95H Serial I/O shift register 1 SIO1 — — 0FF96H Serial I/O shift register 2 SIO2 — — 0FF98H Real-time output buffer register L RTBL — — 0FF99H Real-time output buffer register H RTBH — — 0FF9AH Real-time output port mode register RTPM — 0FF9BH Real-time output port control register RTPC — 0FF9CH Watch timer mode control register WTM — 0FFA0H External interrupt rising edge enable register EGP0 — 0FFA2H External interrupt falling edge enable register EGN0 — 0FFA8H In-service priority register ISPR R — 0FFA9H Interrupt select control register SNMI R/W — 0FFAAH Interrupt mode control register IMC 0FFACH Interrupt mask flag register 0L MK0L MK0 0FFADH Interrupt mask flag register 0H MK0H 0FFAEH Interrupt mask flag register 1L MK1L MK1 0FFAFH Interrupt mask flag register 1H MK1H 0FFB0H I2C bus control registerNote 2 IICCL0 — 0FFB2H Prescaler mode register for serial clock SPRM0 — 0FFB4H Slave address register SVA0 — 0FFB6H I 2C IICS0 R — 0FFB8H Serial shift register IIC0 R/W — 0FFC0H Standby control register STBC — — 30H 0FFC2H Watchdog timer mode register WDM — — 00H 0FFC4H Memory expansion mode register MM — 20H 0FFC7H Programmable wait control register 1 PWC1 — AAH 0FFC8H Programmable wait control register 2 PWC2 W 00FFCEH Clock status register PCS R — 32H 0FFCFH Oscillation stabilization time specification register OSTS R/W — 00H 0FFD0H to 0FFDFH External SFR area — 0000H 0FF8BH bus status registerNote 2 — 00H 80H FFFFH — — — 00H AAAAH — — Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. 28 2. µPD784225Y Subseries only Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Table 6-1. Special Function Register (SFR) List (4/4) AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 Bit R/W 8 Bits At Reset 16 Bits 0FFE0H Interrupt control register (INTWDTM) WDTIC — 0FFE1H Interrupt control register (INTP0) PIC0 — 0FFE2H Interrupt control register (INTP1) PIC1 — 0FFE3H Interrupt control register (INTP2) PIC2 — 0FFE4H Interrupt control register (INTP3) PIC3 — 0FFE5H Interrupt control register (INTP4) PIC4 — 0FFE6H Interrupt control register (INTP5) PIC5 — 0FFE8H Interrupt control register (INTIIC0/INTCSI0) CSIIC0 — 0FFE9H Interrupt control register (INTSER1) SERIC1 — 0FFEAH Interrupt control register (INTSR1/INTCSI1) SRIC1 — 0FFEBH Interrupt control register (INTST1) STIC1 — 0FFECH Interrupt control register (INTSER2) SERIC2 — 0FFEDH Interrupt control register (INTSR2/INTCSI2) SRIC2 — 0FFEEH Interrupt control register (INTST2) STIC2 — 0FFEFH Interrupt control register (INTTM3) TMIC3 — 0FFF0H Interrupt control register (INTTM00) TMIC00 — 0FFF1H Interrupt control register (INTTM01) TMIC01 — 0FFF2H Interrupt control register (INTTM1) TMIC1 — 0FFF3H Interrupt control register (INTTM2) TMIC2 — 0FFF4H Interrupt control register (INTAD) ADIC — 0FFF5H Interrupt control register (INTTM5) TMIC5 — 0FFF6H Interrupt control register (INTTM6) TMIC6 — 0FFF9H Interrupt control register (INTWT) WTIC — 43H Note When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. Data Sheet U12376EJ1V0DS00 29 µPD784224, 784225, 784224Y, 784225Y 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function of each port. Ports 0, 2 to 7, and 12 can be connected to internal pull-up resistors by software when inputting. Figure 7-1. Port Configuration P50 P60 Port 7 P70 P120 Port 12 Port 13 Port 5 Port 6 P57 P00 P05 P10 to P17 P67 P20 P72 P127 P130 P27 P30 P37 P40 P131 P47 30 Port 0 Data Sheet U12376EJ1V0DS00 8 Port 1 Port 2 Port 3 Port 4 µPD784224, 784225, 784224Y, 784225Y Table 7-1. Port Functions Port Name Pin Name Function Specification of Pull-up Resistor Connection by Software Port 0 P00 to P05 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 1 P10 to P17 • Input port Port 2 P20 to P27 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 3 P30 to P37 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 4 P40 to P47 • Can be set in input or output mode bit-wise • Can directly drive LEDs Can be specified in 1-port units Port 5 P50 to P57 • Can be set in input or output mode bit-wise • Can directly drive LEDs Can be specified in 1-port units Port 6 P60 to P67 • Can be set in input or output mode bit-wise Can be specified in 1-port units Port 7 P70 to P72 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 12 P120 to P127 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 13 P130, P131 • Can be set in input or output mode bit-wise — — 7.2 Clock Generator An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider. If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generator XT1 XT2 Subsystem clock oscillator fXT Watch timer, clock output function X1 X2 Main system clock oscillator fX IDLE controller Frequency divider fX 2 Selector Prescaler Clock to peripheral hardware Prescaler fXX fXX 2 fXX 22 fXX 23 Selector STOP and bit 2 (MCK) of the standby control register (STBC) = 1 when the subsystem clock is selected as CPU clock STOP, IDLE controller HALT controller CPU clock (fCPU) Internal system clock (fCLK) Data Sheet U12376EJ1V0DS00 31 µPD784224, 784225, 784224Y, 784225Y Figure 7-3. Example of Using Main System Clock Oscillator (1) Crystal/ceramic oscillation (2) External clock X2 X2 VSS1 X1 VSS External clock µ PD74HCU04 Crystal resorator or ceramic resonator X1 Figure 7-4. Example of Using Subsystem Clock Oscillator (1) Crystal oscillation 32.768 kHz VSS1 Caution (2) External clock VSS XT2 XT2 External clock XT1 XT1 µPD74HCU04 When using the main system clock and subsystem clock oscillator, wire the dotted portions in Figures 7-3 and 7-4 as follows to avoid adverse influence from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the potential at the ground point of the capacitor in the oscillator the same as VSS1. Do not ground to a ground pattern through which a high current flows. • Do not extract signals from the oscillator. Note that the subsystem clock oscillator has a low amplification factor to reduce the current consumption. 32 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 7.3 Real-Time Output Port The real-time output function is to transfer data set in advance to the real-time output buffer register to the output latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device. The pins that output the data to the external device constitute a port called a real-time output port. Because the real-time output port can output signals without jitter, it is ideal for controlling a stepping motor. Figure 7-5. Block Diagram of Real-Time Output Port Internal bus Real-time output port control register (RTPC) RTPOE BYTE EXTR INTP2TRG INTTM1 Higher 4 bits of real-time output buffer register (RTBH) Output trigger controller INTTM2 Lower 4 bits of real-time output buffer register (RTBL) Real-time output port mode register (RTPM) Port 12 output latch Real-time output port output latch P127······································ P120 RTP7······································ RTP0 RTPOE bit P12n/RTPn pin output (n = 0 to 7) P127/······································ P120/ RTP7 RTP0 Data Sheet U12376EJ1V0DS00 33 µPD784224, 784225, 784224Y, 784225Y 7.4 Timer One unit of 16-bit timers/event counters, two units of timers/event counters, and two 8-bit timers are provided. Because a total of six interrupt requests are supported, these timers/counters and timer can be used as six units of timers/counters. Table 7-2. Operations of Timers Name Item Count width 8 bits 16-Bit 8-Bit 8-Bit Timer/Event Timer/Event Timer/Event Counter Counter 1 Counter 2 8-Bit Timer 5 8-Bit Timer 6 1ch 1ch — — — 16 bits Operation mode Interval timer 1ch 1ch 1ch External event counter Function Timer output 1ch 1ch 1ch — — — — — — PWM output — — Square wave output — — PPG output One-shot pulse output Pulse width measurement Number of interrupt requests 34 — — — — 2 inputs — — — — 2 1 1 1 1 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Figure 7-6. Block Diagram of Timers (1/2) 16-bit timer/event counter Clear Selector fXX/4 fXX/16 INTTM3 16-bit timer counter (TM0) 16 INTTM00 16-bit capture/compare register 00 (CR00) 16 INTTM01 TI00 16-bit capture/compare register 01 (CR01) Edge detector Output controller Edge detector Selector TI01 TO0 8-bit timer/event counter 1 fXX/22 Clear fXX/25 fXX/27 OVF Output controller TO1 8 fXX/29 TI1 8-bit timer counter 1 (TM1) Edge detector Selector fXX/2 4 Selector fXX/23 8-bit compare register 10 (CR10) INTTM1 INTTM2 8-bit timer/event counter 2 TM1 fXX/22 Clear fXX/24 5 fXX/2 Selector fXX/23 7 fXX/2 8-bit timer counter 2 (TM2) OVF Output controller TO2 8 fXX/29 TI2 Edge detector 8-bit compare register 20 (CR20) INTTM2 Remark OVF: Overflow flag Data Sheet U12376EJ1V0DS00 35 µPD784224, 784225, 784224Y, 784225Y Figure 7-6. Block Diagram of Timers (2/2) 8-bit timer 5 fXX/22 Clear Selector fXX/23 fXX/24 fXX/25 8-bit timer counter 5 (TM5) fXX/29 8-bit compare register 50 (CR50) Selector 8 fXX/27 INTTM5 INTTM6 8-bit timer 6 TM5 fXX/22 Clear fXX/2 fXX/24 fXX/25 Selector 3 8-bit timer counter 6 (TM6) 8 7 fXX/2 fXX/29 36 8-bit compare register 60 (CR60) Data Sheet U12376EJ1V0DS00 INTTM6 µPD784224, 784225, 784224Y, 784225Y 7.5 A/D Converter An A/D converter converts an analog input variable into a digital signal. This microcontroller is provided with an A/D converter with a resolution of 8 bits and 8 channels (ANI0 to ANI7). This A/D converter is of successive approximation type and the result of conversion is stored to an 8-bit A/D conversion result register (ADCR). The A/D converter can be started in the following two ways: • Hardware start Conversion is started by trigger input (P03). • Software start Conversion is started by setting the A/D converter mode register. One analog input channel is selected from ANI0 to ANI7 for A/D conversion. When A/D conversion is started by means of hardware start, conversion is stopped after it has been completed. When conversion is started by means of software start, A/D conversion is repeatedly executed, and each time conversion has been completed, an interrupt request (INTAD) is generated. Figure 7-7. Block Diagram of A/D Converter Series resistor string ANI0 AVDD ANI2 ANI4 Voltage comparator Selector ANI3 ANI5 Tap selector Sample & hold circuit ANI1 ANI6 AVSS ANI7 INTP3/P03 Successive approximation register (SAR) Edge detector Edge detector INTAD Controller A/D conversion result register (ADCR) INTP3 Internal bus Data Sheet U12376EJ1V0DS00 37 µPD784224, 784225, 784224Y, 784225Y 7.6 D/A Converter A D/A converter converts an input digital signal into an analog voltage. This microcontroller is provided with a voltage output type D/A converter with a resolution of 8 bits and two channels. The conversion method is of R-2R resistor ladder type. D/A conversion is started by setting DACE0 of the D/A converter mode register 0 (DAM0) and DACE1 of the D/ A converter mode register 1 (DAM1). The D/A converter operates in the following two modes: • Normal mode The converter outputs an analog voltage immediately after it has completed D/A conversion. • Real-time output mode The converter outputs an analog voltage in synchronization with an output trigger after it has completed D/A conversion. Figure 7-8. Block Diagram of D/A Converter DACS0 8 2R ANO0 AVREF1 2R R Selector R 2R DACS1 2R 8 2R ANO1 2R R Selector R 2R AVSS 38 2R Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 7.7 Serial Interface Three independent serial interface channels are provided. • Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2 • Clocked serial interface (CSI) × 1 • 3-wire serial I/O (IOE) • I2C bus interface (I2C) (µPD784225Y Subseries only) Therefore, communication with an external system and local communication within the system can be simultaneously executed (see Figure 7-9). Figure 7-9. Example of Serial Interface (a) UART + I2C µ PD784225Y (master) VDD0 VDD0 µ PD4711A [I C] [UART] RS-232C driver/receiver µPD780078Y (slave) 2 RxD1 SDA0 SDA TxD1 SCL0 SCL Port µ PD780308Y (slave) µ PD4711A SDA [UART] RS-232C driver/receiver LCD SCL RxD2 TxD2 Port (b) UART + 3-wire serial I/O µ PD784225Y (master) µ PD4711A SO1 [UART] RxD2 RS-232C driver/receiver TxD2 Port µ PD753106 (slave) [3-wise serial I/O] SI1 SO SCK1 INTPm SI SCK Note Port Port INT Note Handshake line Data Sheet U12376EJ1V0DS00 39 µPD784224, 784225, 784224Y, 784225Y 7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following the start bit is transferred or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also obtained. Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode Internal bus 8 Receive buffer register 1, 2 (RXB1, RXB2) 8 8 Receive shift register 1, 2 (RX1, RX2) RxD1, RxD2 Transmit shift register 1, 2 (TXS1, TXS2) TxD1, TxD2 Baud rate generator Receive control parity check INTSR1, INTSR2 Transmit control parity addition 5-bit counter × 2 Transmit/receive clock generation ASCK1, ASCK2 40 Data Sheet U12376EJ1V0DS00 INTST1, INTST2 Selector fXX to fXX/25 µPD784224, 784225, 784224Y, 784225Y (2) 3-wire serial I/O mode In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: serial clocks (SCK1 and SCK2), serial data inputs (SI1 and SI2), and serial data outputs (SO1 and SO2). To connect two or more devices, a handshake line is necessary. Figure 7-11. Block Diagram in 3-wire Serial I/O Mode Internal bus 8 Direction controller 8 SI1, SI2 Serial I/O shift register 1, 2 (SIO1, SIO2) SO1, SO2 SCK1, SCK2 Serial clock counter Serial clock controller Data Sheet U12376EJ1V0DS00 Interrupt generator Selector INTCSI1, INTCSI2 TO2 fXX/8 fXX/16 41 µPD784224, 784225, 784224Y, 784225Y 7.7.2 Clocked serial interface (CSI) In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. (1) 3-wire serial I/O mode This mode is to communicate with devices having the conventional clocked serial interface. Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data (SI0 and SO0) lines. Generally, a handshake line is necessary to check the reception status. Figure 7-12. Block Diagram in 3-Wise Serial I/O Mode Internal bus 8 Direction controller 8 SI0 Serial I/O shift register 0 (SIO0) SO0 SCK0 Serial clock counter Serial clock controller Interrupt generator Selector INTCSI0 TO2 fXX/8 fXX/16 (2) I2C (Inter IC) bus mode (supporting multi-master) (µPD784225Y Subseries only) This mode is to communicate with devices conforming to the I2C bus format. This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL0) and serial data bus (SDA0). During transfer, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus. During reception, these data can be automatically detected by hardware. 42 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Figure 7-13. Block Diagram in I2C Bus Mode Internal bus 8 8 Direction controller Slave address register (SVA0) Wakeup controller 8 Serial I/O shift register 0 (SIO0) SDA0 Output latch Acknowledge generator Start condition/ acknowledge detector Stop condition detector Serial clock counter SCL0 Serial clock controller Interrupt generator INTIIC0 Selector TO2/18 to TO2/68 fXX/24 to fXX/178 7.8 Clock Output Function Clocks of the following frequencies can be output. • 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 MHz (main system clock: 12.5 MHz) • 32.768 kHz (subsystem clock: 32.768 kHz) Figure 7-14. Block Diagram of Clock Output Function fXX fXX/2 fXX/23 fXX/24 fXX/25 Selector fXX/22 Synchronizer Output controller PCL fXX/26 fXX/27 fXT Data Sheet U12376EJ1V0DS00 43 µPD784224, 784225, 784224Y, 784225Y 7.9 Buzzer Output Function Clocks of the following frequencies can be output as buzzer output. • 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (main system clock: 12.5 MHz) Figure 7-15. Block Diagram of Buzzer Output Function fXX/211 fXX/212 fXX/213 Selector fXX/210 BUZ Output controller 7.10 Edge Detection Function The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 to INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise. Pin Name NMI Detectable Edge Either or both of rising and falling edges Noise Reduction By analog delay INTP0 to INTP5 — 7.11 Watch Timer The watch timer has the following functions: • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. (1) Watch timer The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds by using the 32.768-kHz subsystem clock. (2) Interval timer The interval timer generates an interrupt request (INTTM3) at predetermined time intervals. 44 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Prescaler fW 25 fW 26 fW 27 fW 28 5-bit counter INTWT fW 25 fW 29 Selector fW 24 fW 214 Selector fXT fW Selector fXX/27 Selector Figure 7-16. Block Diagram of Watch Timer INTTM3 To 16-bit timer/counter 7.12 Watchdog Timer A watchdog timer is provided to detect a hang up of the CPU. This watchdog timer generates a non-maskable or maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified. Figure 7-17. Block Diagram of Watchdog Timer fCLK Timer fCLK/221 fCLK/219 Selector fCLK/220 RUNNote HALT IDLE STOP INTWDT fCLK/217 Note Write 1 to bit 7 (RUN) of the watchdog timer (WDM). Remark fCLK: Internal system clock (fXX to fXX/8) Data Sheet U12376EJ1V0DS00 45 µPD784224, 784225, 784224Y, 784225Y 8. INTERRUPT FUNCTION As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request Servicing Mode Vectored interrupt Entity of Servicing Software Context switching Macro service Firmware Servicing Contents of PC and PSW Branches and executes servicing routine (servicing is arbitrary). Saves to and restores from stack. Automatically switches register bank, branches and executes servicing routine (servicing is arbitrary). Saves to or restores from fixed area in register bank Executes data transfer between memory and I/O (servicing is fixed) Retained 8.1 Interrupt Sources Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 25 types of sources, execution of the BRK instruction, BRKCS instruction, or an operand error. The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service function is used, however, nesting always proceeds. The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (see Table 8-2). 46 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Table 8-2. Interrupt Sources Type Software — Non-maskable Maskable Source Default Priority — Name Trigger BRK instruction Instruction execution BRKCS instruction Instruction execution Operand error If result of exclusive OR between operands byte and byte is not FFH when MOV STBC, #byte instruction or MOV WDM, #byte instruction, LOCATION instruction is executed Internal/ External Macro Service — — — NMI Pin input edge detection External INTWDT Overflow of watchdog timer Internal 0 (highest) INTWDTM Overflow of watchdog timer Internal 1 INTP0 Pin input edge detection External 2 INTP1 3 INTP2 4 INTP3 5 INTP4 6 INTP5 7 INTIIC0Note End of I2C bus transfer by CSI0 Internal INTCSI0 End of 3-wire transfer by CSI0 8 INTSER1 Occurrence of UART reception error in ASI1 9 INTSR1 End of UART reception by ASI1 INTCSI1 End of 3-wire transfer by CSI1 10 INTST1 End of UART transfer by ASI1 11 INTSER2 Occurrence of UART reception error in ASI2 12 INTSR2 End of UART reception by ASI2 INTCSI2 End of 3-wire transfer by CSI2 13 INTST2 End of UART transfer by ASI2 14 INTTM3 Reference time interval signal from watch timer 15 INTTM00 Signal indicating coincidence between 16-bit timer counter and capture/compare register (CR00) 16 INTTM01 Signal indicating coincidence between 16-bit timer counter and capture/compare register (CR01) 17 INTTM1 Occurrence of coincidence signal of 8-bit timer/counter 1 18 INTTM2 Occurrence of coincidence signal of 8-bit timer/counter 2 19 INTAD End of conversion by A/D converter 20 INTTM5 Occurrence of coincidence signal of 8-bit timer/counter 5 21 INTTM6 Occurrence of coincidence signal of 8-bit timer/counter 6 22 (lowest) INTWT Overflow of watch timer Note µPD784255Y Subseries only Remarks 1. ASI : Asynchronous Serial Interface CSI : Clocked Serial Interface 2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and maskable interrupts (INTWDTM). Either one (but not both) should be selected for actual use. Data Sheet U12376EJ1V0DS00 47 µPD784224, 784225, 784224Y, 784225Y 8.2 Vectored Interrupt Execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following operations are performed: • On branching: Saves the status of the CPU (contents of PC and PSW) to stack • On returning : Restores the status of the CPU (contents of PC and PSW) from stack To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH. Table 8-3. Vector Table Address Interrupt Source Vector Table Address Interrupt Source BRK instruction 003EH INTST1 001CH Operand error 003CH INTSER2 001EH NMI 0002H INSR2 0020H INTWDT (non-maskable) 0004H INTCSI2 INTWDTM (maskable) 0006H INTST2 0022H INTP0 0008H INTTM3 0024H INTP1 000AH INTTM00 0026H INTP2 000CH INTTM01 0028H INTP3 000EH INTTM1 002AH INTP4 0010H INTTM2 002CH INTP5 0012H INTAD 002EH INTIIC0 0016H INTTM5 00030H INTTM6 0032H INTWT 0038H INTCSI0 INTSER1 0018H INTSR1 001AH INTCSI1 48 Vector Table Address Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 8.3 Context Switching When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the register bank. The branch address is in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Is Generated Register bank n (0 to 7) 0000B <7> Transfer Register bank n (n = 0 to 7) PC15 to PC0 PC19 to PC16 <2> Save (bits 8 through 11 of temporary register) <6> Exchange <5> Save Temporary register <1> Save X A B C R5 R4 R7 R6 V VP U UP T D E W H L <3> Switching of register bank (RBS0 to RBS2 ← n) <4> RSS ← 0 IE ← 0 PSW 8.4 Macro Service This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it. Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds. Figure 8-2. Macro Service Read CPU Memory Write Write Macro service controller SFR Read Internal bus Data Sheet U12376EJ1V0DS00 49 µPD784224, 784225, 784224Y, 784225Y 8.5 Application Example of Macro Service (1) Transmission of serial interface Transfer data storage buffer (memory) Data n Data n − 1 Data 2 Data 1 Internal bus TxD1, TxD2 Transmit shift register TXS1, TXS2 (SFR) Transfer control INTST1, INTST2 Each time macro service request INTST1 and INTST2 are generated, the next transmit data is transferred from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the transmit data storage buffer has become empty), vectored interrupt request INTST1 and INTST2 are generated. (2) Reception of serial interface Receive data storage buffer (memory) Data n Data n − 1 Data 2 Data 1 Internal bus Receive buffer register RXB1, RXB2 (SFR) RxD1, RxD2 Receive shift register Reception control INTSR1, INTSR2 Each time macro service request INTSR1 and INTSR2 are generated, the receive data is transferred from RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request INTSR1 and INTSR2 are generated. 50 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 9. LOCAL BUS INTERFACE The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space of 1 Mbyte (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface (Multiplexed bus) VDD1 µ PD784225 SRAM CS Data bus RD OE WR WE I/O1 to I/O8 Address bus A8 to A19 A0 to A19 Address latch ASTB AD0 to AD7 LE Q0 to Q7 D0 to D7 OE 9.1 Memory Expansion External program and data memory can be connected in two stages: 256 Kbytes and 1 Mbytes. To connect the external memory, ports 4 to 6 are used. The external memory is connected by using a time-division address/data bus. The number of ports used when the external memory is connected can be reduced in this mode. 9.2 Programmable Wait Wait state(s) can be inserted to the memory space (00000H to FFFFFH) while the RD and WR signals are active. In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address decode time. 9.3 External Access Status Function An active low external access status signal is output from the P37/EXA pin. This signal notifies other devices connected to the external bus of the external access status, to disable data output to the external bus from other devices, or enables reception. The external access status signal is output during external access. Data Sheet U12376EJ1V0DS00 51 µPD784224, 784225, 784224Y, 784225Y 10. STANDBY FUNCTION This function is to reduce the power consumption of the chip, and can be used in the following modes: • HALT mode : Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption. • IDLE mode : Stops the entire system with the oscillator continuing operation. The power consumption in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode. • STOP mode : Stops the main system clock and thereby to stop all the internal operations of the chip. Consequently, the power consumption is minimized with only leakage current flowing. • Power-saving mode : The main system clock is stopped with the subsystem clock used as the system clock. The CPU can operate on the subsystem clock to reduce the current consumption. • Power-saving HALT mode : This is a standby function in the power-saving mode and stops the operation clock of the CPU, to reduce the power consumption of the entire system. • Power-saving IDLE mode : This is a standby function in the power-saving mode and stops the entire system except the oscillator, to reduce the power consumption of the entire system. These modes are programmable. The macro service can be started from the HALT mode and power-saving HALT mode. After executing macro service processing, it returns to the HALT mode. 52 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Figure 10-1. Transition of Standby Status Macro service Interrupt requestNote 1 ES R Interrupt request of masked interrupt Power-saving HALT mode is set. Power-saving IDLE mode is set. PowerPowersaving mode saving IDLE to INTP6 input, (operation on NMI, INTP0 Note 2 mode subsystem INTWT (standby) clock) Pow er-sa Norm ving HAL T mo al op de is erati se on is resto t. red. e rvi on se of d cro Ma En ce pr req oc es sin g ue st t es qu re sing ice es ice rv oc se pr erv ro one ro s ac M d of mac En d of En Powersaving HALT mode (standby) ET Interrupt request of masked interrupt put t pu in T in SE RE Macro service request End of one processing End of macro service Macro service STOP (standby) Interrupt request of masked interrupt IDLE (standby) Interrupt request of masked interrupt Interrupt request of masked interrupt RE HALT (standby) t pu T SE T t pu in NM RE SE INT I, IN Ti WT TP0 np ,k ut t o ey I ret NTP urn 6 i int npu err t, up N t ote M ac En ro s er d of v on ice r e pr equ oc es es t sin g ST t es qu re t pt pu e n ru d er ET i mo Int S T RE AL H ts ts Se mo Se de OP NM Se ts ke I, I ID y r NT LE etu P0 rn m t od int o IN e er TP ru 6 pt No in te pu 2 t, I End of oscilla NT tion stabiliza W tion time T , Normal operation (operation on main system clock) in SE RE Waits for oscillation stabilization 2 Notes 1. Only unmasked interrupt requests 2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87) Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby (HALT mode/STOP mode/IDLE mode). Data Sheet U12376EJ1V0DS00 53 µPD784224, 784225, 784224Y, 784225Y 11. RESET FUNCTION When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset). During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the current consumption of the entire system can be reduced. When the RESET signal goes high, the reset status is cleared, oscillation stabilization time (41.9 ms at 12.5 MHz) elapses, the contents of the reset vector table are set to the program counter (PC), execution branches to an address set to the PC, and program execution is started from that branch address. Therefore, the program can be reset and started from any address. Figure 11-1. Oscillation of Main System Clock during Reset Period Main system clock oscillator Oscillation is unconditionally stopped during rest period fCLK RESET input Oscillation stabilization time The RESET input pin has an analog delay noise eliminator to prevent malfunctioning due to noise. Figure 11-2. Accepting Reset Signal Time until the clock starts oscillation Analog delay Analog delay RESET input Internal reset signal Internal clock 54 Data Sheet U12376EJ1V0DS00 Analog delay Oscillation stabilization time µPD784224, 784225, 784224Y, 784225Y 12. ROM CORRECTION ROM correction is a function to replace part of the program in the internal ROM with a program in the internal RAM. By using the ROM correction function, instruction bugs found in the internal ROM can be avoided or the flow of the program can be changed. ROM correction can be used at up to four places in the internal ROM (program). Figure 12-1. Block Diagram of ROM Correction Program counter (PC) Coincidence Correction branch processing request signal (CALLT instruction) Comparator Correction address pointer n Correction address registers (CORAH, CORAL) CORENn CORCHm ROM correction control register (CORC) Internal bus Remark n = 0 to 3, m = 0 or 1 Data Sheet U12376EJ1V0DS00 55 µPD784224, 784225, 784224Y, 784225Y 13. INSTRUCTION SET (1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 13-1. Instruction List by 8-Bit Addressing Second Operand #byte A r saddr r' saddr' sfr !addr16 !!addr24 First Operand A (MOV) ADD Note 1 MOV ADD Note 1 r3 [WHL+] [WHL–] [saddrp] PSWL [%saddrg] PSWH MOV (MOV) MOV (MOV)Note 6 MOV (MOV) MOV (XCH) XCH (XCH)Note 6 (XCH) (XCH) XCH (XCH) ADDNote 1 (ADD)Note 1 (ADD)Note 1 (ADD)Note 1 (ADD)Note 1,6 (ADD)Note 1 ADDNote 1 r mem (MOV) MOV MOV MOV MOV (XCH) XCH XCH XCH XCH ADDNote 1 ADDNote 1 (ADD)Note 1 ADDNote 1 n NoneNote 2 (MOV) ROR Note 3 MULU DIVUW INC DEC saddr MOV ADD sfr Note 1 MOV (MOV) Note 6 MOV (ADD)Note 1 ADDNote 1 MOV MOV INC XCH DEC ADDNote 1 DBNZ MOV PUSH ADDNote 1 (ADD)Note 1 ADDNote 1 POP CHKL CHKLA !addr16 MOV (MOV) MOV ADDNote 1 !!addr24 mem MOV ADDNote 1 [saddrp] [%saddrg] mem3 ROR4 ROL4 r3 MOV MOV PSWL PSWH B, C DBNZ STBC, WDM MOV [TDE+] MOVBKNote 5 (MOV) [TDE–] (ADD) Note 1 MOVMNote 4 Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR. 4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM. 5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK. 6. The code length of some instructions having saddr2 as saddr in this combination is short. 56 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y (2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 13-2. Instruction List by 16-Bit Addressing Second Operand #word AX rp saddrp rp' saddrp' sfrp !addr16 mem !!addr24 [saddrp] First Operand AX [WHL+] byte n NoneNote 2 SHRW MULW Note 4 SHLW INCW [%saddrg] (MOVW) ADDW Note 1 (MOVW) (XCHW) Note 3 MOVW (MOVW) MOVW (MOVW) Note 3 (XCHW) XCHW XCHW (XCHW) (MOVW) (MOVW) (XCHW) (XCHW) (ADD)Note 1 (ADDW)Note 1 (ADDW)Note 1,3 (ADDW)Note 1 rp MOVW ADDW Note 1 (MOVW) MOVW MOVW MOVW (XCHW) XCHW XCHW XCHW (ADDW) Note 1 ADDW Note 1 MOVW (MOVW)Note 3 MOVW saddrp ADDW Note 1 (ADDW) Note 1 ADDW Note 1 ADDW Note 1 ADDW MOVW Note 1 DECW MOVW INCW XCHW DECW ADDWNote 1 sfrp MOVW MOVW MOVW PUSH ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 MOVW (MOVW) POP MOVW MOVTBLW !!addr24 mem MOVW [saddrp] [%saddrg] PSW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] (MOVW) SACW byte MACW MACSW Notes 1. The operands of SUBW and CMPW are the same as that of ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The code length of some instructions having saddrp2 as saddrp in this combination is short. 4. The operands of MULUW and DIVUX are the same as that of MULW. Data Sheet U12376EJ1V0DS00 57 µPD784224, 784225, 784224Y, 784225Y (3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 13-3. Instruction List by 24-Bit Addressing Second Operand #imm24 WHL rg saddrg !!addr24 mem1 [%saddrg] SP (MOVG) MOVG MOVG MOVG None Note rg' First Operand WHL rg (MOVG) (MOVG) (MOVG) (MOVG) (ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG MOVG (MOVG) MOVG MOVG ADDG (ADDG) ADDG DECG SUBG (SUBG) SUBG PUSH MOVG INCG POP saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG [%saddrg] MOVG SP MOVG MOVG INCG DECG Note Either the second operand is not used, or the second operand is not an operand address. 58 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 13-4. Bit Manipulation Instructions Second Operand CY saddr.bit sfr.bit /saddr.bit /sfr. bit A.bit X.bit /A.bit /X.bit PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit mem2.bit /mem2.bit First Operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit CY MOV1 AND1 AND1 OR1 OR1 None Note NOT1 SET1 CLR1 XOR1 saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit Note Either the second operand is not used, or the second operand is not an operand address. Data Sheet U12376EJ1V0DS00 59 µPD784224, 784225, 784224Y, 784225Y (5) Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 13-5. Call and Return/Branch Instructions Operand of Instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None Address Basic instruction Compound instruction BCNote CALL BR BR CALL CALL CALL CALL CALL CALL BR BR BR BR BR BR CALLF CALLF BRKCS BRK RET RETCS RETI RETCSB RETB BF BT BTCLR BFSET DBNZ Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS 60 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 14. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Ratings Unit VDD0 −0.3 to +6.5 V AVDD −0.3 to VDD0 + 0.3 V AVSS −0.3 to VSS0 + 0.3 V −0.3 to VDD0 + 0.3 V −0.3 to VDD0 + 0.3 V AVSS − 0.3 to AVREF1 + 0.3 V −0.3 to VDD + 0.3 V Per pin 15 mA Total of all pins 100 mA Per pin −10 mA Total of all pins −40 mA AVREF1 Input voltage D/A converter reference voltage input VI Analog input voltage VAN Output voltage VO Output current, low IOL Output current, high Conditions IOH Analog input pin Operating ambient temperature TA −40 to +85 °C Storage temperature Tstg −65 to +150 °C Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. Data Sheet U12376EJ1V0DS00 61 µPD784224, 784225, 784224Y, 784225Y Operating Conditions • Operating ambient temperature (TA): −40°C to +85°C • Power supply voltage and clock cycle time: see Figure 14-1 • Operating voltage when the subsystem clock is operating: VDD = 1.8 to 5.5 V Figure 14-1. Power Supply Voltage and Clock Cycle Time (CPU Clock Frequency: fCPU) 10,000 8,000 Clock cycle time tCYK [ns] 500 400 Guaranteed operation range 320 300 200 160 100 80 0 0 1 1.8 2 2.7 3 4 4.5 5 5.5 6 Supply voltage [V] Capacitance (TA = 25°C, VDD = V DD0 = VDD1 = VSS = 0 V) Parameter Input capacitance Symbol Conditions MIN. TYP. MAX. Unit CI f = 1 MHz 15 pF Output capacitance CO Unmeasured pins returned to 0 V. 15 pF I/O capacitance CIO 15 pF 62 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Main System Clock Oscillator Characteristics (TA = −40°C to +85°C, VDD = V DD0 = VDD1) Resonator Recommended Circuit Ceramic resonator Parameter Oscillation frequency (fX) X2 X1 VSS or crystal resonator External X1 input frequency (fX) clock X2 X1 Conditions MIN. MAX. Unit MHz 4.5 V ≤ VDD ≤ 5.5 V 2 12.5 2.7 V ≤ VDD < 4.5 V 2 6.25 2.0 V ≤ VDD < 2.7 V 2 3.125 1.8 V ≤ VDD < 2.0 V 2 2 4.5 V ≤ VDD ≤ 5.5 V 2 12.5 2.7 V ≤ VDD < 4.5 V 2 6.25 2.0 V ≤ VDD < 2.7 V 2 3.125 1.8 V ≤ VDD < 2.0 V 2 2 15 250 ns ns X1 input high-/lowlevel width (tWXH, tWXL) µ PD74HCU04 TYP. X1 input rising/falling 4.5 V ≤ VDD ≤ 5.5 V 0 5 time (tXR, tXF) 2.7 V ≤ VDD < 4.5 V 0 10 2.0 V ≤ VDD < 2.7 V 0 20 1.8 V ≤ VDD < 2.0 V 0 30 MHz Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U12376EJ1V0DS00 63 µPD784224, 784225, 784224Y, 784225Y Subsystem Clock Oscillator Characteristics (TA = −40°C to +85°C, VDD = VDD0 = V DD1) Resonator Recommended Circuit Crystal resonator External clock Parameter Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s Oscillation frequency (fXT) VSS XT2 XT2 XT1 XT1 Oscillation stabilization 4.5 V ≤ VDD ≤ 5.5 V timeNote 1.8 V ≤ VDD < 4.5 V 10 XT1 input frequency (fXT) 32 35 kHz XT1 input high-/low-level width (tXTH, tXTL) 14.3 15.6 µs µ PD74HCU04 Note Time required to stabilize oscillation after applying supply voltage (VDD). Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 64 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y DC Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = V SS0 = V SS1 = AVSS = 0 V) (1/2) Parameter Input voltage, low Symbol VIL1 VIL2 VIL4 VIL5 VIL6 Input voltage, high VIH1 VIH2 VIH4 VIH5 VIH6 Output voltage, low Output voltage, high VOL1 Conditions V 1.8 V ≤ VDD < 2.2 V 0 0.2VDD P00 to P05, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V 0 0.2VDD P34, P70, P72, RESET 1.8 V ≤ VDD < 2.2 V 0 0.15VDD P10 to P17, P130, P131 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDD 1.8 V ≤ VDD < 2.2 V 0 0.2VDD 2.2 V ≤ VDD ≤ 5.5 V 0 0.2VDD 1.8 V ≤ VDD < 2.2 V 0 0.1VDD 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDD 1.8 V ≤ VDD < 2.2 V 0 0.2VDD 2.2 V ≤ VDD ≤ 5.5 V 0.7VDD VDD 1.8 V ≤ VDD < 2.2 V 0.8VDD VDD P00 to P05, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V 0.8VDD VDD P34, P70, P72, RESET 1.8 V ≤ VDD < 2.2 V 0.85VDD VDD P10 to P17, P130, P131 2.2 V ≤ VDD ≤ 5.5 V 0.7VDD VDD 1.8 V ≤ VDD < 2.2 V 0.8VDD VDD 2.2 V ≤ VDD ≤ 5.5 V 0.8VDD VDD 1.8 V ≤ VDD < 2.2 V 0.85VDD VDD 2.2 V ≤ VDD ≤ 5.5 V 0.7VDD VDD 1.8 V ≤ VDD < 2.2 V 0.8VDD VDD X1, X2, XT1, XT2 P25, P27 Note 1 X1, X2, XT1, XT2 P25, P27 V V V V V V V V V For pins other than P40 to P47, P50 to P57, IOL = 1.6 mANote 2 4.5 V ≤ VDD ≤ 5.5 V 0.4 V P40 to P47, P50 to P57 IOL = 8 mANote 2 4.5 V ≤ VDD ≤ 5.5 V 1.0 V 0.5 V IOL = 400 µANote 2 VOH1 IOH = −1 ILIH1 Unit 0.3VDD mANote 2 VIN = 0 V ILIL2 Input leakage current, high MAX. 0 VOL2 ILIL1 TYP. 2.2 V ≤ VDD ≤ 5.5 V Note 1 IOH = −100 Input leakage current, low MIN. VIN = VDD0 ILIH2 4.5 V ≤ VDD ≤ 5.5 V VDD − 1.0 V VDD − 0.5 V µANote 2 Except X1, X2, XT1, XT2 −3 µA X1, X2, XT1, XT2 −20 µA Except X1, X2, XT1, XT2 3 µA X1, X2, XT1, XT2 20 µA Output leakage current, low ILOL1 VOUT = 0 V −3 µA Output leakage current, high ILOH1 VOUT = VDD 3 µA Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87, P120 to P127 2. Per pin Data Sheet U12376EJ1V0DS00 65 µPD784224, 784225, 784224Y, 784225Y DC Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = V SS0 = V SS1 = AVSS = 0 V) (2/2) Parameter Supply voltage Symbol IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Conditions MAX. Unit fXX = 12.5 MHz, VDD = 5.0 V ±10% 17 40 mA mode fXX = 6 MHz, VDD = 3.0 V ±10% 5 17 mA fXX = 2 MHz, VDD = 2.0 V ±10% 2 8 mA fXX = 12.5 MHz, VDD = 5.0 V ±10% 7 20 mA fXX = 6 MHz, VDD = 3.0 V ±10% 2 8 mA fXX = 2 MHz, VDD = 2.0 V ±10% 0.5 3.5 mA 1 2.5 mA fXX = 6 MHz, VDD = 3.0 V ±10% 0.4 1.3 mA fXX = 2 MHz, VDD = 2.0 V ±10% 0.2 0.9 mA Operation fXX = 32 kHz, VDD = 5.0 V ±10% 80 200 µA modeNote fXX = 32 kHz, VDD = 3.0 V ±10% 60 110 µA fXX = 32 kHz, VDD = 2.0 V ±10% 30 100 µA HALT fXX = 32 kHz, VDD = 5.0 V ±10% 60 160 µA modeNote fXX = 32 kHz, VDD = 3.0 V ±10% 20 80 µA fXX = 32 kHz, VDD = 2.0 V ±10% 10 70 µA IDLE fXX = 32 kHz, VDD = 5.0 V ±10% 50 150 µA modeNote fXX = 32 kHz, VDD = 3.0 V ±10% 15 70 µA fXX = 32 kHz, VDD = 2.0 V ±10% 5 60 µA 5.5 V HALT mode IDLE mode fXX = 12.5 MHz, VDD = 5.0 V ±10% VDDDR HALT, IDLE modes Data retention current IDDDR STOP mode RL TYP. Operation Data retention voltage Pull-up resistor MIN. 1.8 VDD = 2.0 V ±10% 2 10 µA VDD = 5.0 V ±10% 10 50 µA 30 100 kΩ VIN = 0 V 10 Note When main system clock is stopped. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 66 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y AC Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = V SS0 = V SS1 = AVSS = 0 V) (1) Read/write operation (1/3) Parameter Cycle time Address setup time Symbol Conditions MIN. tCYK 4.5 V ≤ VDD ≤ 5.5 V 80 ns 2.7 V ≤ VDD < 4.5 V 160 ns 2.0 V ≤ VDD < 2.7 V 320 ns 1.8 V ≤ VDD < 2.0 V 500 ns VDD = 5.0 V ±10% (0.5 + a) T − 20 ns VDD = 3.0 V ±10% (0.5 + a) T − 40 ns VDD = 2.0 V ±10% (0.5 + a) T − 80 ns VDD = 5.0 V ±10% 0.5T − 19 ns VDD = 3.0 V ±10% 0.5T − 24 ns VDD = 2.0 V ±10% 0.5T − 34 ns VDD = 5.0 V ±10% (0.5 + a) T − 17 ns VDD = 3.0 V ±10% (0.5 + a) T − 40 ns VDD = 2.0 V ±10% (0.5 + a) T − 110 ns VDD = 5.0 V ±10% 0.5T − 14 ns VDD = 3.0 V ±10% 0.5T − 14 ns VDD = 2.0 V ±10% 0.5T − 14 ns VDD = 5.0 V ±10% (1 + a) T − 24 ns VDD = 3.0 V ±10% (1 + a) T − 35 ns VDD = 2.0 V ±10% (1 + a) T − 80 ns tSAST (to ASTB↓) Address hold time tHSTLA (from ASTB↓) ASTB high-level width Address hold time tWSTH tHRA (from RD↑) Delay time from address to tDAR RD↓ Address float time tFAR (from RD↓) Data input time from tDAID address Data input time from ASTB↓ Data input time from RD↓ tDSTID tDRID TYP. MAX. Unit VDD = 5.0 V ±10% 0 ns VDD = 3.0 V ±10% 0 ns VDD = 2.0 V ±10% 0 ns VDD = 5.0 V ±10% (2.5 + a + n) T − 37 ns VDD = 3.0 V ±10% (2.5 + a + n) T − 52 ns VDD = 2.0 V ±10% (2.5 + a + n) T − 120 ns VDD = 5.0 V ±10% (2 + n) T − 35 ns VDD = 3.0 V ±10% (2 + n) T − 50 ns VDD = 2.0 V ±10% (2 + n) T − 80 ns VDD = 5.0 V ±10% (1.5 + n) T − 40 ns VDD = 3.0 V ±10% (1.5 + n) T − 50 ns VDD = 2.0 V ±10% (1.5 + n) T − 90 ns Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) Data Sheet U12376EJ1V0DS00 67 µPD784224, 784225, 784224Y, 784225Y AC Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = V SS0 = V SS1 = AVSS = 0 V) (1) Read/write operation (2/3) Parameter Delay time from ASTB↓ Symbol tDSTR to RD↓ Data hold time (from RD↑) Address active time from tHRID tDRA RD↑ Delay time from RD↑ to tDRST ASTB↑ RD low-level width Delay time from address to tWRL tDAW WR↓ Address hold time tHRD (from WR↑) Delay time from ASTB↓ to tDSTOD data output Delay time from WR↓ to tDWOD data output Delay time from ASTB↓ to tDSTW WR↓ Data setup time (to WR↑) tSODWR Conditions MIN. MAX. Unit VDD = 5.0 V ±10% 0.5T − 9 ns VDD = 3.0 V ±10% 0.5T − 9 ns VDD = 2.0 V ±10% 0.5T − 20 ns VDD = 5.0 V ±10% 0 ns VDD = 3.0 V ±10% 0 ns VDD = 2.0 V ±10% 0 ns VDD = 5.0 V ±10% 0.5T − 2 ns VDD = 3.0 V ±10% 0.5T − 12 ns VDD = 2.0 V ±10% 0.5T − 35 ns VDD = 5.0 V ±10% 0.5T − 9 ns VDD = 3.0 V ±10% 0.5T − 9 ns VDD = 2.0 V ±10% 0.5T − 40 ns VDD = 5.0 V ±10% (1.5 + n) T − 25 ns VDD = 3.0 V ±10% (1.5 + n) T − 30 ns VDD = 2.0 V ±10% (1.5 + n) T − 25 ns VDD = 5.0 V ±10% (1 + a) T − 24 ns VDD = 3.0 V ±10% (1 + a) T − 34 ns VDD = 2.0 V ±10% (1 + a) T − 70 ns VDD = 5.0 V ±10% 0.5T − 14 ns VDD = 3.0 V ±10% 0.5T − 14 ns VDD = 2.0 V ±10% 0.5T − 14 ns VDD = 5.0 V ±10% 0.5T + 15 ns VDD = 3.0 V ±10% 0.5T + 30 ns VDD = 2.0 V ±10% 0.5T + 240 ns VDD = 5.0 V ±10% 0.5T − 30 ns VDD = 3.0 V ±10% 0.5T − 30 ns VDD = 2.0 V ±10% 0.5T − 30 ns VDD = 5.0 V ±10% 0.5T − 9 ns VDD = 3.0 V ±10% 0.5T − 9 ns VDD = 2.0 V ±10% 0.5T − 20 ns VDD = 5.0 V ±10% (1.5 + n) T − 20 ns VDD = 3.0 V ±10% (1.5 + n) T − 25 ns VDD = 2.0 V ±10% (1.5 + n) T − 70 ns Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) 68 TYP. Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y AC Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = V SS0 = V SS1 = AVSS = 0 V) (1) Read/write operation (3/3) Parameter Data hold time (from WR↑) Delay time from WR↑ to Symbol tHWOD tDWST ASTB↑ WR low-level width tWWL Conditions MIN. TYP. MAX. Unit VDD = 5.0 V ±10% 0.5T − 14 ns VDD = 3.0 V ±10% 0.5T − 14 ns VDD = 2.0 V ±10% 0.5T − 50 ns VDD = 5.0 V ±10% 0.5T − 9 ns VDD = 3.0 V ±10% 0.5T − 9 ns VDD = 2.0 V ±10% 0.5T − 30 ns VDD = 5.0 V ±10% (1.5 + n) T − 25 ns VDD = 3.0 V ±10% (1.5 + n) T − 30 ns VDD = 2.0 V ±10% (1.5 + n) T − 30 ns Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) Data Sheet U12376EJ1V0DS00 69 µPD784224, 784225, 784224Y, 784225Y AC Characteristics (TA = −40°C to +85°C, V DD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (2) External wait timing (1/2) Parameter Input time from address to Symbol tDAWT WAIT↓ Input time from ASTB↓ to tDSTWT WAIT↓ Hold time from ASTB↓ to tHSTWT WAIT Delay time from ASTB↓ to tDSTWTH WAIT↑ Input time from RD↓ to tDRWTL WAIT↓ Hold time from RD↓ to tHRWT WAIT↓ Delay time from RD↓ to tDRWTH WAIT↑ Input time from WAIT↑ to tDWTID data Delay time from WAIT↑ to tDWTR RD↑ Delay time from WAIT↑ to tDWTW WR↑ Delay time from WR↓ to WAIT↓ tDWWTL Conditions MIN. MAX. Unit VDD = 5.0 V ±10% (2 + a) T − 40 ns VDD = 3.0 V ±10% (2 + a) T − 60 ns VDD = 2.0 V ±10% (2 + a) T − 300 ns VDD = 5.0 V ±10% 1.5T − 40 ns VDD = 3.0 V ±10% 1.5T − 60 ns VDD = 2.0 V ±10% 1.5T − 260 ns VDD = 5.0 V ±10% (0.5 + n) T + 5 ns VDD = 3.0 V ±10% (0.5 + n) T + 10 ns VDD = 2.0 V ±10% (0.5 + n) T + 30 ns VDD = 5.0 V ±10% (1.5 + n) T − 40 ns VDD = 3.0 V ±10% (1.5 + n) T − 60 ns VDD = 2.0 V ±10% (1.5 + n) T − 90 ns VDD = 5.0 V ±10% T − 40 ns VDD = 3.0 V ±10% T − 60 ns VDD = 2.0 V ±10% T − 70 ns VDD = 5.0 V ±10% nT + 5 ns VDD = 3.0 V ±10% nT + 10 ns VDD = 2.0 V ±10% nT + 30 ns VDD = 5.0 V ±10% (1 + n) T − 40 ns VDD = 3.0 V ±10% (1 + n) T − 60 ns VDD = 2.0 V ±10% (1 + n) T − 90 ns VDD = 5.0 V ±10% 0.5T − 5 ns VDD = 3.0 V ±10% 0.5T − 10 ns VDD = 2.0 V ±10% 0.5T − 30 ns VDD = 5.0 V ±10% 0.5T ns VDD = 3.0 V ±10% 0.5T ns VDD = 2.0 V ±10% 0.5T + 5 ns VDD = 5.0 V ±10% 0.5T ns VDD = 3.0 V ±10% 0.5T ns VDD = 2.0 V ±10% 0.5T + 5 ns VDD = 5.0 V ±10% T − 40 ns VDD = 3.0 V ±10% T − 60 ns VDD = 2.0 V ±10% T − 90 ns Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) 70 TYP. Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y (2) External wait timing (2/2) Parameter Hold time from WR↓ to Symbol tHWWT WAIT Delay time from WR↓ to WAIT↑ tDWWTH Conditions MIN. TYP. MAX. Unit VDD = 5.0 V ±10% nT + 5 ns VDD = 3.0 V ±10% nT + 10 ns VDD = 2.0 V ±10% nT + 30 ns VDD = 5.0 V ±10% (1 + n) T − 40 ns VDD = 3.0 V ±10% (1 + n) T − 60 ns VDD = 2.0 V ±10% (1 + n) T − 90 ns Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) Data Sheet U12376EJ1V0DS00 71 µPD784224, 784225, 784224Y, 784225Y Serial Operation (T A = −40°C to +85°C, V DD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, V SS = VSS0 = VSS1 = AVSS = 0 V) (a) 3-wire serial I/O mode (SCK: Internal clock output) Parameter SCK cycle time Symbol tKCY1 SCK high-/low-level tKH1, width tKL1 SI setup time (to SCK↑) tSIK1 SI hold time (from SCK↑) tKSI1 SO output delay time (from SCK↓) tKSO1 Conditions 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V MIN. TYP. MAX. Unit 800 ns 3,200 ns 350 ns 1,500 ns 10 ns 30 ns 40 ns 30 ns MAX. Unit (b) 3-wire serial I/O mode (SCK: External clock input) Parameter SCK cycle time Symbol tKCY2 SCK high-/low-level tKH2 width tKL2 SI setup time (to SCK↑) tSIK2 SI hold time (from SCK↑) tKSI2 SO output delay time (from SCK↓) tKSO2 Conditions 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V MIN. TYP. 800 ns 3,200 ns 400 ns 1,600 ns 10 ns 30 ns 40 ns 30 ns MAX. Unit (c) UART mode Parameter ASCK cycle time Symbol tKCY3 Conditions MIN. TYP. 4.5 V ≤ VDD ≤ 5.5 V 417 ns 2.7 V ≤ VDD < 4.5 V 833 ns 1,667 ns ASCK high-/low-level tKH3 4.5 V ≤ VDD ≤ 5.5 V 208 ns width tKL3 2.7 V ≤ VDD < 4.5 V 416 ns 833 ns 72 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y (d) I2C bus mode (µPD784225Y only) Parameter Symbol Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. SCL0 clock frequency fCLK 0 100 0 400 kHz Bus free time (between stop and start conditions) tBUF 4.7 − 1.3 − µs tHD : STA 4.0 − 0.6 − µs Low-level width of SCL0 clock tLOW 4.7 − 1.3 − µs High-level width of SCL0 clock tHIGH 4.0 − 0.6 − µs Setup time of start/restart conditions tSU : STA 4.7 − 0.6 − µs Data hold When using time CBUS-compatible master tHD : DAT 5.0 − − − µs 0Note 2 − 0Note 2 0.9Note 3 µs tSU : DAT 250 − 100Note 4 − ns Rising time of SDA0 and SCL0 signals tR − 1,000 20 + 0.1CbNote 5 300 ns Falling time of SDA0 and tF − 300 20 + 0.1CbNote 5 300 ns tSU : STO 4.0 − 0.6 − µs Pulse width of spike restricted by input filter tSP − − 0 50 ns Load capacitance of each bus line Cb − 400 − 400 pF Hold timeNote1 When using I2C bus Data setup time SCL0 signals Setup time of stop condition Notes 1. For the start condition, the first clock pulse is generated after the hold time. 2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal SDA0 signal (on VIHmin.) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low-level hold time (t LOW), only the maximum data hold time tHD : DAT needs to be satisfied. 4. The high-speed mode I2C bus can be used in a standard mode I2C bus system. In this case, the conditions described below must be satisfied. • If the device does not extend the SCL0 signal low-level hold time tSU : DAT ≥ 250 ns • If the device extends the SCL0 signal low-level hold time Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + t SU : DAT = 1,000 + 250 = 1,250 ns by standard mode I2C bus specification) 5. Cb: Total capacitance per bus line (unit: pF) Data Sheet U12376EJ1V0DS00 73 µPD784224, 784225, 784224Y, 784225Y Other Operations (T A = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, V SS = VSS0 = VSS1 = AV SS = 0 V) Parameter Symbol NMI high-/low-level width tWNIL tWNIH INTP input high-/lowlevel width tWITL tWITH RESET high-/low-level width tWRSL tWRSH Conditions INTP0 to INTP6 MIN. TYP. MAX. Unit 10 µs 100 ns 10 µs Clock Output Operation (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit PCL cycle time tCYCL 4.5 V ≤ VDD ≤ 5.5 V, nT 80 31,250 ns PCL high-/low-level width tCLL tCLH 4.5 V ≤ VDD ≤ 5.5 V, 0.5T − 10 30 15,615 ns PCL rising/falling time tCLR 4.5 V ≤ VDD ≤ 5.5 V 5 ns tCLF 2.7 V ≤ VDD < 4.5 V 10 ns 1.8 V ≤ VDD < 2.7 V 20 ns Remark T: tCYK = 1/fXX (fXX: Main system clock frequency) n: Divided frequency ratio set by software in the CPU • When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 • When using the subsystem clock: n = 1 74 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y A/D Converter Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = V SS0 = V SS1 = AVSS = 0 V) Parameter Symbol Conditions Resolution Overall errorNote MIN. TYP. MAX. Unit 8 8 8 bit 6.25 MHz < fXX ≤ 12.5 MHz, 4.5 V ≤ VDD ≤ 5.5 V, AVDD = VDD0 ±1.2 %FSR 3.125 MHz < fXX ≤ 6.25 MHz, 2.7 V ≤ VDD ≤ 5.5 V, AVDD = VDD0 ±1.2 %FSR 2 MHz < fXX ≤ 3.125 MHz, 2.0 V ≤ VDD ≤ 5.5 V, AVDD = VDD0 ±1.6 %FSR fXX = 2 MHz, 1.8 V ≤ VDD ≤ 5.5 V AVDD = VDD0 ±1.6 %FSR Conversion time tCONV 14 Sampling time tSAMP 24/fXX Analog input voltage VIAN AVSS Reference voltage AVDD VDD Resistance between AVDD and AVSS RAVREF0 A/D conversion is not performed 144 µs µs VDD AVDD V VDD V 40 kΩ Note Excludes quantization error (±0.2%FSR). Remark FSR: Full-scale range D/A Converter Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = V SS0 = V SS1 = AVSS = 0 V) Parameter Symbol Conditions Resolution Overall errorNote Settling time Output resistance RO Reference voltage AVREF1 AVREF1 current AIREF1 MIN. TYP. MAX. Unit 8 8 8 bit 2.0 V ≤ VDD ≤ 5.5 V R = 10 MΩ, 2.0 V ≤ AVREF1 ≤ 5.5 V ±0.6 %FSR 1.8 V ≤ VDD ≤ 2.0 V R = 10 MΩ, 1.8 V ≤ AVREF1 ≤ 5.5 V ±1.2 %FSR Load conditions: 4.5 V ≤ AVREF1 ≤ 5.5 V 10 µs C = 30 pF 2.7 V ≤ AVREF1 < 4.5 V 15 µs 1.8 V ≤ AVREF1 < 2.7 V 20 µs DACS0, 1 = 55H 8 1.8 For only 1 channel kΩ VDD0 V 2.5 mA Note Excludes quantization error (±0.2%FSR). Remark FSR: Full-scale range Data Sheet U12376EJ1V0DS00 75 µPD784224, 784225, 784224Y, 784225Y Data Retention Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AV DD = 1.8 to 5.5 V, VSS = V SS0 = V SS1 = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. 1.8 MAX. Unit 5.5 V Data retention voltage VDDDR STOP mode Data retention current IDDDR VDDDR = 5.0 V ±10% 10 50 µA VDDDR = 2.0 V ±10% 2 10 µA VDD rise time tRVD 200 µs VDD fall time tFVD 200 µs VDD hold time (from STOP mode setting) tHVD 0 ms STOP release signal input time tDREL 0 ms Oscillation stabilization tWAIT Crystal resonator 30 ms Ceramic resonator 5 ms RESET, P00/INTP0 to P06/INTP6 0 0.1VDDDR V 0.9VDDDR VDDDR V wait time Low-level input voltage VIL High-level input voltage VIH AC Timing Measurement Points VDD − 1 V 0.45 V 76 0.8VDD or 1.8 V 0.8 V Points of measurement Data Sheet U12376EJ1V0DS00 0.8VDD or 1.8 V 0.8 V µPD784224, 784225, 784224Y, 784225Y Timing Waveform (1) Read operation (CLK) tCYK A0 to A7 (Output) Lower address Lower address A8 to A19 (Output) Higher address Higher address tDAID tHRA tDRA tDSTID AD0 to AD7 (Input/output) Hi-Z Hi-Z Lower address (Output) tSAST Data (Input) Hi-Z Lower address (Output) tHRID tHSTLA tFAR ASTB (Output) tWSTH tDSTR tDAR tDRST tDRID RD (Output) tWRL tDRWTL tDAWT tDRWTH tHRWT tDWTR tDWTID WAIT (Input) tDSTWT tDSTWTH tHSTWT Data Sheet U12376EJ1V0DS00 77 µPD784224, 784225, 784224Y, 784225Y (2) Write operation (CLK) tCYK A0 to A7 (Output) Lower address Lower address A8 to A19 (Output) Higher address Higher address tDAID tHWA tDAW tDSTOD AD0 to AD7 (Output) Hi-Z Lower address (Output) tSAST Hi-Z Data (Output) tHWOD tHSTLA tSODWR tFAR ASTB (Output) tWSTH tDSTW tDAW tDWST tDWOD WR (Output) tWWL tDWWTL tDAWT tDWWTH tHWWT WAIT (Input) tDSTWT tDSTWTH tHSTWT 78 Hi-Z Data Sheet U12376EJ1V0DS00 tDWTW tDWTID Lower address (Output) µPD784224, 784225, 784224Y, 784225Y Serial Operation (1) 3-wire serial I/O mode tKCY1, 2 tKH1, 2 tKL1, 2 SCK tKSO1, 2 tKSI1, 2 tSIK1, 2 SI/SO (2) UART mode tKCY3 tKH3 tKL3 ASCK (3) I2C bus mode (µPD784255Y Subseries only) tLOW tR SCL0 tHD : DAT tHD : STA tHIGH tSU : DAT tF tSU : STA tHD : STA tSP tSU : STO SDA0 tBUF Stop condition Start condition Restart condition Data Sheet U12376EJ1V0DS00 Stop condition 79 µPD784224, 784225, 784224Y, 784225Y Clock Output Timing tCLH tCLL CLKOUT tCLR tCLF tCYCL Interrupt Input Timing tWNIH tWNIL tWITH tWITL NMI INTP0 to INTP6 Reset Input Timing tWRSH tWRSL RESET 80 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Clock Timing tWXH tWXL X1 tXR tXF 1/fX tXTH tXTL XT1 1/fXT Data Retention Characteristics STOP mode setting VDD VDDDR tHVD tFVD tRVD tDREL tWAIT RESET NMI (Cleared by falling edge) NMI (Cleared by rising edge) Data Sheet U12376EJ1V0DS00 81 µPD784224, 784225, 784224Y, 784225Y 15. PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G I H M P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 17.20±0.20 B 14.00±0.20 C 14.00±0.20 D 17.20±0.20 F 0.825 G 0.825 H I 0.32±0.06 0.13 J 0.65 (T.P.) K 1.60±0.20 L 0.80±0.20 M 0.17 +0.03 −0.07 N P 0.10 1.40±0.10 Q 0.125±0.075 R 3 +7 −3 S 1.70 MAX. P80GC-65-8BT-1 82 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 41 61 40 detail of lead end S C D P T 80 R 21 1 20 U Q F G L H I J M K S N S M NOTE ITEM Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A B 14.0±0.2 12.0±0.2 C 12.0±0.2 D F 14.0±0.2 1.25 G 1.25 H 0.22±0.05 I 0.08 J 0.5 (T.P.) K L 1.0±0.2 0.5 M 0.145±0.05 N 0.08 P 1.0 Q 0.1±0.05 R 3 +4 −3 S 1.1±0.1 T 0.25 U 0.6±0.15 P80GK-50-9EU-1 Data Sheet U12376EJ1V0DS00 83 µPD784224, 784225, 784224Y, 784225Y 16. RECOMMENDED SOLDERING CONDITIONS The µPD784225 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Caution Soldering conditions for the µPD784224GC-×××-8BT, µPD784225YGC-×××-8BT, and µPD784225YGK×××-9EU are undetermined because these products are under development. Table 16-1. Soldering Conditions for Surface Mount Type (1) µPD784225GC-×××-8BT: 80-pin plastic QFP (14 × 14 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours) IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours) VP15-00-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) — Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours) Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) — Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). (2) µPD784224GK-×××-9EU: 80-pin plastic TQFP (fine pitch) (14 × 20 mm) µPD784225GK-×××-9EU: 80-pin plastic TQFP (fine pitch) (14 × 20 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours) IR35-103-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours) VP15-103-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) — Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) — Caution 84 Do not use different soldering methods together (except for partial heating). Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD784225. Also see (5). (1) Language Processing Software RA78K4 Assembler package common to 78K/IV Series CC78K4 C compiler package common to 78K/IV Series DF784225 Device file common to µPD784225, 784225Y Subseries CC78K4-L C compiler library source file common to 78K/IV Series (2) Flash Memory Writing Tools Flashpro II (Part No.: FL-PR2), Flashpro III (Part No.: FL-PR3, PG-FP3) Dedicated flash programmer for microcontroller incorporating flash memory FA-80GC Adapter for writing 80-pin plastic QFP (GC-8BT type) flash memory. FA-80GK Adapter for writing 80-pin plastic LQFP (GK-BE9 type) flash memory. (3) Debugging Tools • When IE-78K4-NS in-circuit emulator is used IE-78K4-NS In-circuit emulator common to 78K/IV Series IE-70000-MC-PS-B Power supply unit for IE-78K4-NS IE-70000-98-IF-C Interface adapter used when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) IE-70000-CD-IF-A PC card and cable when notebook PC is used as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/ATTM or compatible as host machine (ISA bus supported) IE-70000-PCI-IF Interface adapter when using PC that incorporates PCI bus as host machine IE-784225-NS-EM1 Emulation board to emulate µPD784225, 784225Y Subseries NP-100GF Emulation probe for 100-pin plastic QFP (GF-3BA type) NP-100GC Emulation probe for 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) TGC-100SDW Conversion adapter to connect the NP-100GC and a target system board on which a 100pin plastic LQFP (GC-8EU type) can be mounted ID78K4-NS Integrated debugger for IE-78K4-NS SM78K4 System simulator common to 78K/IV Series DF784225 Device file common to µPD784225, 784225Y Subseries Data Sheet U12376EJ1V0DS00 85 µPD784224, 784225, 784224Y, 784225Y • When IE-784000-R in-circuit emulator is used IE-784000-R In-circuit emulator common to 78K/IV Series IE-70000-98-IF-C Interface adapter used when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported) IE-70000-PCI-IF Interface adapter when using PC that incorporates PCI bus as host machine IE-78000-R-SV3 Interface adapter and cable used when EWS is used as host machine IE-784225-NS-EM1 IE-784218-R-EM1 Emulation board to emulate µPD784225, 784225Y Subseries IE-784000-R-EM Emulation board common to 78K/IV Series IE-78K4-R-EX3 Emulation probe conversion board necessary when using IE-784225-NS-EM1 on IE784000-R. Not necessary when IE-784216-R-EM1 is used. EP-78064GF-R Emulation probe for 100-pin plastic QFP (GF-3BA type) EP-78064GC-R Emulation probe for 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) TGC-100SDW Conversion adapter to connect the NP-100GC and a target system board on which a 100pin plastic LQFP (GC-8EU type) can be mounted ID78K4 Integrated debugger for IE-784000-R SM78K4 System simulator common to 78K/IV Series DF784225 Device file common to µPD784225, 784225Y Subseries (4) Real-time OS RX78K/IV Real-time OS for 78K/IV Series MX78K4 OS for 78K/IV Series 86 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y (5) Cautions on Using Development Tools • The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784225. • The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218. • The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). • The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672) • For third-party development tools, see the 78K/IV Series Selection Guide (U13355E). • The host machine and OS suitable for each software are as follows: Host Machine [OS] Software PC EWS PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows] HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] RA78K4 Note CC78K4 Note ID78K4-NS – ID78K4 SM78K4 – RX78K/IV Note MX78K4 Note Note DOS-based software Data Sheet U12376EJ1V0DS00 87 µPD784224, 784225, 784224Y, 784225Y APPENDIX B. RELATED DOCUMENTS Documents related to device Document Name Document No. Japanese English µPD784224, 784225, 784224Y, 784225Y Data Sheet U12376J This document µPD78F4225, 78F4225Y Data Sheet U12377J Planned µPD784225, 784225Y Subseries User’s Manual - Hardware Planned Planned µPD784225Y Subseries Special Function Register Table Planned – 78K/IV Series User’s Manual - Instruction U10905J U10905E 78K/IV Series Instruction Table U10594J – 78K/IV Series Instruction Set U10595J – 78K/IV Series Application Note - Software Basics U10095J U10095E Documents related to development tools (User’s Manuals) Document Name Document No. Japanese English Operation U11334J U11334E Language U11162J U11162E U11743J U11743E Operation U11572J U11572E Language U11571J U11571E IE-78K4-NS U13356J U13356E IE-784000-R U12903J U12903E IE-784218-R-EM1 U12155J U12155E IE-784225-NS-EM1 U13742J U13742E EP-78064 EEU-934 EEU-1469 RA78K4 Assembler Package RA78K Series Structured Assembler Preprocessor CC78K4 C Compiler SM78K4 System Simulator - Windows Base Reference U10093J U10093E SM78K Series System Simulator External component user open interface specification U10092J U10092E ID78K4-NS Integrated Debugger - PC Base Reference U12796J U12796E ID78K4 Integrated Debugger - Windows Base Reference U10440J U10440E ID78K4 Integrated Debugger - HP-UX, SunOS, NEWS-OS Base Reference U11960J U11960E Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of a document for designing. 88 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Documents related to embedded software (User’s Manual) Document Name Document No. 78K/IV Series Real-Time OS 78K/IV Series OS MX78K4 Japanese English Basics U10603J U10603E Installation U10604J U10604E Debugger U10364J – Basics U11779J – Other documents Document Name Document No. Japanese English SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Semiconductor Device Quality Control/Reliability Handbook C12769J MEI-1202 Guide for Products Related to Micro-Computer: Other Companies U11416J – Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of a document for designing. Data Sheet U12376EJ1V0DS00 89 µPD784224, 784225, 784224Y, 784225Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Caution This product contains an I2C bus interface circuit. When using the I2C bus interface, notify its use to NEC when ordering custom code. NEC can guarantee the following only when the customer informs NEC of the use of the interface: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. IEBus is a trademark of NEC Corporation. Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 90 Data Sheet U12376EJ1V0DS00 µPD784224, 784225, 784224Y, 784225Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Hong Kong Ltd. NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U12376EJ1V0DS00 91 µPD784224, 784225, 784224Y, 784225Y The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7D 98. 12 92