NEC UPD78P4038YGK-BE9

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78P4038Y
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD78P4038Y, 78K/IV Series' product, is a one-time PROM or EPROM version of the µPD784035Y,
µPD784036Y, µPD784037Y, and µPD784038Y with internal masked ROM.
Since user programs can be written to PROM, this microcontroller is best suited for evaluation in system
development, manufacture of small quantities of multiple products, and fast start-up of applications.
For specific functions and other detailed information, consult the following user's manual.
This manual is required reading for design work.
µPD784038, 784038Y Sub-Series User's Manual, Hardware : U11316E
78K/IV Series User's Manual, Instruction
: U10905E
FEATURES
• Compatible with the µPD78P238, µPD78P4026, and µPD78P4038
• Internal PROM: 128 Kbytes
• µPD78P4038YKK-T : EPROM (best suited for system evaluation)
• µPD78P4038YGC-3B9 : PROM (best suited for manufacture of small quantities)
µPD78P4038YGC-8BT : PROM (best suited for manufacture of small quantities)
µPD78P4038YGK-BE9 : PROM (best suited for manufacture of small quantities)
• Internal RAM: 4,352 bytes
• Supply voltage: VDD = 2.7 to 5.5 V
• QTOPTM microcomputer
Remark The QTOP microcomputer is a microcomputer with a built-in one-time PROM that is totally supported
by NEC. The support includes writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part number
Package
Internal ROM
µPD78P4038YGC-3B9
80-pin plastic QFP (14 × 14 × 2.7 mm)
µPD78P4038YGC-8BT
80-pin plastic QFP (14 × 14 × 1.4 mm)
One-time PROM
µPD78P4038YGC-×××-3B9
80-pin plastic QFP (14 × 14 mm)
One-time PROM (QTOP microcomputer)
µPD78P4038YGK-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
One-time PROM
µPD78P4038YGK-×××-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
One-time PROM (QTOP microcomputer)
µPD78P4038YKK-T
80-pin ceramic WQFN (14 × 14 mm)
EPROM
One-time PROM
In this reference, all ROM components that are common to one-time PROM and EPROM are referred to as
PROM.
The information in this document is subject to change without notice.
Document No. U10742EJ2V0DS00 (2nd edition)
Date Published July 1998 J CP(K)
Printed in Japan
The mark
shows major revised points.
©
1995
µPD78P4038Y
QUALITY GRADE
Part number
Package
Quality grade
µPD78P4038YGC-3B9
80-pin plastic QFP (14 × 14 × 2.7 mm)
Standard (for general electronic equipment)
µPD78P4038YGC-8BT
80-pin plastic QFP (14 × 14 × 1.4 mm)
Standard (for general electronic equipment)
µPD78P4038YGC-×××-3B9 80-pin plastic QFP (14 × 14 × 1.4 mm)
Standard (for general electronic equipment)
µPD78P4038YGK-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard (for general electronic equipment)
µPD78P4038YGK-×××-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard (for general electronic equipment)
µPD78P4038YKK-T
Not applied (for function evaluation)
80-pin ceramic WQFN (14 × 14 mm)
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation
to know the specification of quality grade on the devices and its recommended applications.
Caution The EPROM versions of the µPD78P4038Y are not intended for use in mass-produced products;
they do not have reliability high enough for such purposes. Their use should be restricted to
functional evaluation in experiment or trial manufacture.
Remark ××× is ROM code suffix.
2
µPD78P4038Y
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
: Product under mass production
: Product under preparation
Standard Products Development
Connectable to the I2C bus
µ PD784038Y
Connectable to the multimaster I2C bus
µPD784225Y
µPD784038
µ PD784026
A/D converters,
16-bit timers, and
power management
functions have been
enhanced.
Internal memory has been expanded.
Pin-compatible with the µ PD784026
Connectable to the multimaster I2C bus
µ PD784225
80 pins
ROM correction function has been added.
Connectable to the multimaster I2C bus
µPD784216Y
µPD784218Y
µ PD784216
µ PD784218
100 pins
I/O has been enhanced.
Internal memory has been expanded.
Internal memory has been expanded.
ROM correction function has been added.
µ PD784054
µ PD784046
Built-in 10-bit A/D converter
ASSP Development
µ PD784955
DC inverter control
µ PD784908
Built-in IEBusTM controller
µ PD784937
Functions of the µ PD784908 have been enhanced.
Internal memory has been expanded.
ROM correction function has been added.
Connectable to the multimaster I2C bus
µ PD784928Y
µ PD784915
µ PD784928
Functions of the µ PD784915 have been enhanced.
Software servo control
Built-in analog circuit for VCR
Timers have been enhanced.
3
µPD78P4038Y
FUNCTIONS
(1/2)
Item
Functions
Number of basic instructions
(mnemonics)
113
General-purpose register
8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction
execution time
125 ns/250 ns/500 ns/1,000 ns (at 32 MHz)
Internal
memory
PROM
128 Kbytes (Can be changed to 48 K, 64 K, or 96 Kbytes by software)
RAM
4,352 bytes (Can be changed to 2,048 or 3,584 bytes by software)
Memory space
I/O ports
Additional
function
pinsNote
Program and data: 1 Mbyte
Total
64
Input
8
Input/output
56
Pins with pull- 54
up resistor
LED direct
drive outputs
24
Transistor
direct drive
8
Real-time output ports
4 bits × 2, or 8 bits × 1
Timer/counter
Timer/counter 0: Timer register × 1
Capture register × 1
Compare register × 2
Pulse output capability
• Toggle output
• PWM/PPG output
• One-shot pulse output
Timer/counter 1: Timer register × 1
Capture register × 1
Capture/compare register × 1
Compare register × 1
Pulse output capability
• Real-time output (4 bits × 2)
Timer/counter 2: Timer register × 1
Capture register × 1
Capture/compare register × 1
Compare register × 1
Pulse output capability
• Toggle output
• PWM/PPG output
Timer 3
: Timer register × 1
Compare register × 1
PWM outputs
12-bit resolution × 2 channels
Serial interface
UART/IOE (3-wire serial I/O): 2 channels (incorporating baud rate generator)
CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus): 1 channel
A/D converter
8-bit resolution × 8 channels
D/A converter
8-bit resolution × 2 channels
Note Additional function pins are included in the I/O pins.
4
µPD78P4038Y
(2/2)
Item
Functions
Clock output
Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port)
Watchdog timer
1 channel
Standby
HALT/STOP/IDLE mode
Interrupt
Hardware source 24 (17 internal, 7 external (sampling clock variable input: 1))
Software source
BRK instruction, BRKCS instruction, operand error
Nonmaskable
1 internal, 1 external
Maskable
16 internal, 6 external
• 4-level programmable priority
• 3 operation statuses: vectored interrupt, macro service, context switching
Supply voltage
VDD = 2.7 to 5.5 V
Package
80-pin
80-pin
80-pin
80-pin
plastic QFP (14 × 14 × 2.7 mm)
plastic QFP (14 × 14 × 1.4 mm)
plastic TQFP (fine pitch) (12 × 12 mm)
ceramic WQFN (14 × 14 mm)
5
µPD78P4038Y
CONTENTS
1.
DIFFERENCES BETWEEN µPD78P4038Y AND MASKED ROM PRODUCTS ....................
7
2.
PIN CONFIGURATION (TOP VIEW) .........................................................................................
8
3.
BLOCK DIAGRAM .....................................................................................................................
11
4.
LIST OF PIN FUNCTIONS .........................................................................................................
12
4.1
Pins for Normal Operating Mode .................................................................................................
12
4.2
Pins for PROM Programming Mode (VPP ≥ +5 V or +12.5 V, RESET = L) ..............................
15
4.2.1
Pin functions ..................................................................................................................
15
4.2.2
Pin functions ..................................................................................................................
16
I/O Circuits for Pins and Handling of Unused Pins ..................................................................
17
5.
INTERNAL MEMORY SWITCHING (IMS) REGISTER ............................................................
20
6.
PROM PROGRAMMING ............................................................................................................
21
6.1
Operation Mode ..............................................................................................................................
21
6.2
PROM Write Sequence ..................................................................................................................
23
6.3
PROM Read Sequence ..................................................................................................................
27
7.
ERASURE CHARACTERISTICS (µPD78P4038YKK-T ONLY) ...............................................
28
8.
PROTECTIVE FILM COVERING THE ERASURE WINDOW (µPD78P4038YKK-T ONLY) ..
28
9.
QUALITY .....................................................................................................................................
28
10. SCREENING ONE-TIME PROM PRODUCTS ..........................................................................
28
11. ELECTRICAL CHARACTERISTICS .........................................................................................
29
12. PACKAGE DRAWINGS .............................................................................................................
55
13. RECOMMENDED SOLDERING CONDITIONS ........................................................................
59
APPENDIX A DEVELOPMENT TOOLS ..........................................................................................
61
APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER
(TGK-080SDW)..........................................................................................................
64
APPENDIX C RELATED DOCUMENTS ..........................................................................................
67
4.3
6
µPD78P4038Y
1. DIFFERENCES BETWEEN µPD78P4038Y AND MASKED ROM PRODUCTS
The µPD78P4038Y is produced by replacing the masked ROM in the µPD784035Y, µPD784036Y, µPD784037Y,
or µPD784038Y with PROM to which data can be written. The functions of the µPD78P4038Y are the same as those
of the µPD784035Y, µPD784036Y, µPD784037Y, or µPD784038Y except for the PROM specification such as writing
and verification, except that the PROM size can be changed to 48 K, 64 K, or 96 Kbytes, and except that the internal
RAM size can be changed to 2,048 or 3,584 bytes.
Table 1-1 shows the differences between these products.
Table 1-1. Differences between the µPD78P4038Y and Masked ROM Products
Product Name
µPD78P4038Y
µPD784035Y
µPD784036Y
µPD784037Y
µPD784038Y
• 48-Kbyte
masked ROM
• 64-Kbyte
masked ROM
• 96-Kbyte
masked ROM
• 128-Kbyte
masked ROM
• 3,584-byte
internal RAM
• 4,352-byte
internal RAM
Item
Internal program
memory
• 128-Kbyte
PROM
• Can be changed
to 48 K, 64 K, or
96 Kbytes by
IMS
Internal RAM
• 4,352-byte
• 2,048-byte internal RAM
internal RAM
• Can be changed
to 2,048 or 3,584
bytes by IMS
Package
• 80-pin plastic QFP (14 × 14 × 2.7 mm)
• 80-pin plastic QFP (14 × 14 × 1.4 mm)
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin ceramic
WQFN
(14 × 14 mm)
7
µPD78P4038Y
2. PIN CONFIGURATION (TOP VIEW)
(1) Normal operating mode
• 80-pin plastic QFP (14 × 14 × 2.7 mm)
µPD78P4038YGC-3B9, µPD78P4038YGC-×××-3B9
• 80-pin plastic QFP (14 × 14 × 1.4 mm)
µPD78P4038YGC-8BT
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD78P4038YGK-BE9, µPD78P4038YGK-×××-BE9
• 80-pin ceramic WQFN (14 × 14 mm)
Note
8
P75/ANI5
P76/ANI6
P77/ANI7
AVDD
AVREF1
AVSS
ANO0
ANO1
AVREF3
P20/NMI
P21/INTP0
P22/INTP1
P23/INTP2/CI
P24/INTP3
P25/INTP4/ASCK/SCK1
P26/INTP5
P27/SI0
AVREF2
Connect the TEST pin to VSS0 directly.
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P60/A16
P61/A17
P62/A18
P63/A19
P64/RD
P65/ WR
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P66/ WAIT/HLDRQ
P32/SCK0/SCL
P33/SO0/SDA
P34/ TO0
P35/ TO1
P36/ TO2
P37/ TO3
RESET
VDD1
X2
X1
VSS1
P00
P01
P02
P03
P04
P05
P06
P07
P67/REFRQ/HLDAK
P30/RxD/SI1
P31/ TxD/SO1
µPD78P4038YKK-T
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
VDD0
P17
P16
P15
P14/TXD2/SO2
P13/RXD2/SI2
P12/ASCK2/SCK2
P11/PWM1
P10/PWM0
TESTNote
VSS0
ASTB/CLKOUT
P40/AD0
P41/AD1
P42/AD2
µPD78P4038Y
A8-A19
: Address bus
P60-P67
: Port 6
AD0-AD7
: Address/data bus
P70-P77
: Port 7
ANI0-ANI7
: Analog input
PWM0, PWM1 : Pulse width modulation output
ANO0, ANO1 : Analog output
RD
: Read strobe
ASCK, ASCK2 : Asynchronous serial clock
REFRQ
: Refresh request
ASTB
: Address strobe
RESET
: Reset
AVDD
: Analog power supply
RxD, RxD2
: Receive data
AVREF1-AVREF3 : Reference voltage
SCK0-SCK2
: Serial clock
AVSS
: Analog ground
SCL
: Serial clock
CI
: Clock input
SDA
: Serial data
CLKOUT
: Clock output
SI0-SI2
: Serial input
HLDAK
: Hold acknowledge
SO0-SO2
: Serial output
HLDRQ
: Hold request
TEST
: Test
INTP0-INTP5 : Interrupt from peripherals
TO0-TO3
: Timer output
NMI
: Non-maskable interrupt
TxD, TxD2
: Transmit data
P00-P07
: Port 0
VDD0, VDD1
: Power supply
P10-P17
: Port 1
VSS0, VSS1
: Ground
P20-P27
: Port 2
WAIT
: Wait
P30-P37
: Port 3
WR
: Write strobe
P40-P47
: Port 4
X1, X2
: Crystal
P50-P57
: Port 5
9
µPD78P4038Y
(2) PROM programming mode
• 80-pin plastic QFP (14 × 14 × 2.7 mm)
µPD78P4038YGC-3B9, µPD78P4038YGC-×××-3B9
• 80-pin plastic QFP (14 × 14 × 1.4 mm)
µPD78P4038YGC-8BT
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD78P4038YGK-BE9, µPD78P4038YGK-×××-BE9
• 80-pin ceramic WQFN (14 × 14 mm)
VSS
Open
VDD
VSS
Open
VSS
A9
VDD
(L)
Open
VPP
VSS
Open
A0
A1
A2
: Connect these pins separately to the VSS pins through 10-kΩ pull-down resistors.
: To be connected to the ground.
Open : Nothing should be connected on these pins.
RESET: Set a low-level input.
10
Open
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
A14
A15
(L)
PGM
RESET
VDD
Open
(L)
VSS
D0
D1
D2
D3
D4
D5
D6
D7
(L)
OE
Open
CE
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(L)
Caution L
VSS
Open
µPD78P4038YKK-T
A0-A16
: Address bus
RESET
: Reset
CE
: Chip enable
VDD
: Power supply
D0-D7
: Data bus
VPP
: Programming power supply
OE
: Output enable
VSS
: Ground
PGM
: Program
µPD78P4038Y
3. BLOCK DIAGRAM
NMI
INTP0-INTP5
Baud-rate
generator
UART/IOE1
INTP3
TO0
TO1
Timer/counter 0
(16 bits)
INTP0
Timer/counter 1
(16 bits)
INTP1
INTP2/CI
TO2
TO3
UART/IOE2
Programmable
interrupt
controller
Timer/counter 2
(16 bits)
78 K/IV
CPU core
(RAM 512 bytes)
P00-P03
P04-P07
PWM
SCK0/SCL
SO0/SDA
SI0
Clock output
ASTB/CLKOUT
AD0-AD7
A8-A15
A16-A19
RD
WR
WAIT/HLDRQ
REFRQ/HLDAK
D0-D7Note
A0-A16Note
CENote
OENote
PGMNote
RAM
(3,840 bytes)
ANO0
ANO1
Clocked
serial
interface
Bus
interface
PWM1
AVREF2
RXD2/SI2
TXD2/SO2
ASCK2/SCK2
Real-time
output port
PWM0
ASCK/SCK1
Baud-rate
generator
PROM
(128 Kbytes)
Timer 3
(16 bits)
RXD/SI1
TXD/SO1
D/A
converter
AVREF3
Port 0
P00-P07
Port 1
P10-P17
Port 2
P20-P27
Port 3
P30-P37
Port 4
P40-P47
Port 5
P50-P57
Port 6
P60-P67
Port 7
P70-P77
ANI0-ANI7
AVDD
AVREF1
A/D
converter
AVSS
Watchdog
timer
INTP5
Note
System
control
RESET
TEST
X1
X2 Note
VPP
VDD0, VDD1
VSS0, VSS1
In the PROM programming mode.
11
µPD78P4038Y
4. LIST OF PIN FUNCTIONS
4.1
Pins for Normal Operating Mode
(1) Port pins (1/2)
Pin
I/O
Alternate-Function
Function
P00-P07
I/O
–
Port 0 (P0):
• 8-bit I/O port.
• Functions as a real-time output port (4 bits × 2).
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive a transistor.
P10
I/O
PWM0
P11
PWM1
P12
ASCK2/SCK2
P13
RXD2/SI2
P14
TXD2/SO2
P15-P17
Port 1 (P1):
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive LED.
–
P26
Port 2 (P2):
• 8-bit input-only port.
INTP0
• P20 does not function as a general-purpose port (nonmaskable
INTP1
interrupt). However, the input level can be checked by an interrupt
service routine.
INTP2/CI
•
The use of the pull-up resistors can be specified by software for pins
INTP3
P22 to P27 (in units of 6 bits).
INTP4/ASCK/SCK1
• The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by
INTP5
CSIM1.
P27
SI0
P20
Input
P21
P22
P23
P24
P25
P30
I/O
NMI
RXD/SI1
P31
TXD/SO1
P32
SCK0/SCL
P33
SO0/SDA
P34-P37
TO0-TO3
P40-P47
12
I/O
AD0-AD7
Port 3 (P3):
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
Port 4 (P4):
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive LED.
µPD78P4038Y
(1) Port pins (2/2)
Pin
I/O
Alternate-Function
P50-P57
I/O
A8-A15
Port 5 (P5):
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive LED.
P60-P63
I/O
A16-A19
Port 6 (P6):
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
P64
RD
P65
WR
P66
WAIT/HLDRQ
P67
REFRQ/HLDAK
P70-P77
I/O
ANI0-ANI7
Function
Port 7 (P7):
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
13
µPD78P4038Y
(2) Non-port pins (1/2)
Pin
TO0-TO3
I/O
Output
Function
Alternate-Function
P34-P37
Timer output
CI
Input
P23/INTP2
Input of a count clock for timer/counter 2
R XD
Input
P30/SI1
Serial data input (UART0)
P13/SI2
Serial data input (UART2)
P31/SO1
Serial data output (UART0)
P14/SO2
Serial data output (UART2)
P25/INTP4/SCK1
Baud rate clock input (UART0)
P12/SCK2
Baud rate clock input (UART2)
P33/SO0
Serial data I/O (2-wire serial I/O, I2C bus)
P27
Serial data input (3-wire serial I/O0)
SI1
P30/RXD
Serial data input (3-wire serial I/O1)
SI2
P13/RXD2
Serial data input (3-wire serial I/O2)
P33/SDA
Serial data output (3-wire serial I/O0)
SO1
P31/TXD
Serial data output (3-wire serial I/O1)
SO2
P14/TXD2
Serial data output (3-wire serial I/O2)
P32/SCL
Serial clock I/O (3-wire serial I/O0)
SCK1
P25/INTP4/ASCK
Serial clock I/O (3-wire serial I/O1)
SCK2
P12/ASCK2
Serial clock I/O (3-wire serial I/O2)
SCL
P32/SCK0
Serial clock I/O (2-wire serial I/O, I2C bus)
P20
External interrupt request
RXD2
TX D
Output
TXD2
ASCK
Input
ASCK2
SDA
I/O
SI0
Input
SO0
SCK0
NMI
Output
I/O
Input
–
INTP0
P21
• Input of a count clock for timer/counter 1
• Capture/trigger signal for CR11 or CR12
INTP1
P22
• Input of a count clock for timer/counter 2
• Capture/trigger signal for CR22
INTP2
P23/CI
• Input of a count clock for timer/counter 2
• Capture/trigger signal for CR21
INTP3
P24
• Input of a count clock for timer/counter 0
• Capture/trigger signal for CR02
INTP4
P25/ASCK/SCK1
INTP5
P26
–
Input of a conversion start trigger for A/D converter
I/O
P40-P47
Time multiplexing address/data bus (for connecting external memory)
A8-A15
Output
P50-P57
High-order address bus (for connecting external memory)
A16-A19
Output
P60-P63
High-order address bus during address expansion (for connecting external memory)
RD
Output
P64
Strobe signal output for reading the contents of external memory
WR
Output
P65
Strobe signal output for writing on external memory
Input
P66/HLDRQ
Wait signal insertion
REFRQ
Output
P67/HLDAK
Refresh pulse output to external pseudo static memory
HLDRQ
Input
P66/WAIT
Input of bus hold request
HLDAK
Output
P67/REFRQ
Output of bus hold response
ASTB
Output
CLKOUT
Latch timing output of time multiplexing address (A0-A7) (for connecting
external memory)
CLKOUT
Output
ASTB
Clock output
AD0-AD7
WAIT
14
µPD78P4038Y
(2) Non-port pins (2/2)
Pin
I/O
Alternate-Function
RESET
Input
–
Chip reset
X1
Input
–
X2
–
Crystal input for system clock oscillation (A clock pulse can also be input
to the X1 pin.)
ANI0-ANI7
ANO0, ANO1
AVREF1
Input
Function
Analog voltage inputs for the A/D converter
P70-P77
Output
–
Analog voltage inputs for the D/A converter
–
–
Application of A/D converter reference voltage
AVREF2, AVREF3
Application of D/A converter reference voltage
AVDD
Positive power supply for the A/D converter
AVSS
Ground for the A/D converter
VDD0Note 1
Positive power supply of the port part
VDD1Note 1
Positive power supply except for the port part
VSS0Note 2
Ground of the port part
VSS1Note 2
Ground except for the port part
TEST
Directly connect to VSS0. (The TEST pin is for the IC test.)
Notes 1. The potential of the VDD0 pin must be equal to that of the VDD1 pin.
2. The potential of the VSS0 pin must be equal to that of the VSS1 pin.
Pins for PROM Programming Mode (VPP ≥ +5 V or +12.5 V, RESET = L)
4.2
4.2.1 Pin functions
Pin Name
VPP
I/O
–
Function
PROM programming mode selection
High voltage input during program write or verification
RESET
Input
Address bus
A0-A16
D0-D7
CE
PROM programming mode selection
I/O
Input
Data bus
PROM enable input/program pulse input
OE
Read strobe input to PROM
PGM
Program/program inhibit input during PROM programming mode
VDD
–
Positive power supply
VSS
–
GND
15
µPD78P4038Y
4.2.2
Pin functions
(1) VPP (Programming power supply): Input
Input pin for setting the µPD78P4038Y to the PROM programming mode. When the input voltage on this pin
is +5 V or more and when RESET input goes low, the µPD78P4038Y enters the PROM programming mode.
When CE is made low for VPP = +12.5 V and OE = high, program data on D0 to D7 can be written into the internal
PROM cell selected by A0 to A16.
(2) RESET (Reset): Input
Input pin for setting the µPD78P4038Y to the PROM programming mode. When input on this pin is low, and
when the input voltage on the VPP pin goes +5 V or more, the µPD78P4038Y enters the PROM programming
mode.
(3) A0 to A16 (Address bus): Input
Address bus that selects an internal PROM address (0000H to 1FFFFH)
(4) D0 to D7 (Data bus): I/O
Data bus through which a program is written on or read from internal PROM
(5) CE (Chip enable): Input
This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or
read.
(6) OE (Output enable): Input
This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a onebyte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7.
(7) PGM (Program): Input
The input pin for the operation mode control signal of the internal PROM.
Upon activation, writing to the internal PROM is enabled.
Upon inactivation, reading from the internal PROM is enabled.
(8) VDD
Positive power supply pin
(9) VSS
Ground potential pin
16
µPD78P4038Y
4.3
I/O Circuits for Pins and Handling of Unused Pins
Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins.
Figure 4-1 shows the configuration of these various types of I/O circuits.
Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)
Pin
P00-P07
I/O Circuit Type
I/O
5-H
I/O
P10/PWM0
P11/PWM1
P12/ASCK2/SCK2
8-C
P13/RXD2/SI2
5-H
Recommended Connection Method for Unused Pins
Input state: To be connected to VDD0
Output state: To be left open
P14/TXD2/SO2
P15-P17
P20/NMI
2
Input
To be connected to VDD0 or VSS0
P21/INTP0
P22/INTP1
2-C
To be connected to VDD0
P23/INTP2/CI
P24/INTP3
P25/INTP4/ASCK/SCK1
8-C
I/O
P26/INTP5
2-C
Input
5-H
I/O
Input state: To be connected to VDD0
Output state: To be left open
I/O
Input state: To be connected to VDD0 or VSS0
Output state: To be left open
Input state: To be connected to VDD0
Output state: To be left open
To be connected to VDD0
P27/SI0
P30/RXD/SI1
P31/TXD/SO1
P32/SCK0/SCL
10-B
P33/SO0/SDA
P34/TO0-P37/TO3
5-H
P40/AD0-P47/AD7
P50/A8-P57/A15
P60/A16-P63/A19
P64/RD
P65/WR
P66/WAIT/HLDRQ
P67/REFRQ/HLDAK
P70/ANI0-P77/ANI7
20-A
ANO0, ANO1
12
ASTB/CLKOUT
4-B
Output
To be left open
17
µPD78P4038Y
Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)
Pin
I/O Circuit Type
RESET
2
TEST
1-A
AVREF1-AVREF3
I/O
Recommended Connection Method for Unused Pins
Input
–
To be connected to VSS0 directly
–
To be connected to VSS0
AVSS
AVDD
To be connected to VDD0
Caution When the I/O mode of an I/O alternate-function pin is unpredictable, connect the pin to VDD0
through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin
becomes higher than that of the low level input at power-on or when I/O is switched by software).
Remark Since type numbers are consistent in the 78K Series, those numbers are not always serial in each
product. (Some circuits are not included.)
18
µPD78P4038Y
Figure 4-1. I/O Circuits for Pins
Type 1-A
Type 2-C
VDD0
VDD0
P
Pull-up
enable
P
IN
N
IN
VSS0
Type 2
IN
Schmitt trigger input with hysteresis characteristics
Type 5-H
Schmitt trigger input with hysteresis characteristics
Type 4-B
VDD0
Pull-up
enable
VDD0
Data
P
P
VDD0
P
Data
OUT
Output
disable
IN/OUT
Output
disable
N
N
VSS0
VSS0
Input
enable
Push-pull output which can output high impedance
(both the positive and negative channels are off.)
Type 8-C
Type 12
VDD0
Pull-up
enable
P
VDD0
P
Data
Analog output
voltage
P
OUT
N
IN/OUT
Output
disable
N
VSS0
Type 10-B
Type 20-A
VDD0
VDD0
Pull-up
enable
P
IN/OUT
P
Output
disable
VDD0
P
Data
Open
drain
Output
disable
Data
N
VSS0
Comparator
IN/OUT
+
–
N
AVSS
AVREF
(Threshold voltage)
VSS0
P
N
Input
enable
19
µPD78P4038Y
5. INTERNAL MEMORY SWITCHING (IMS) REGISTER
This register enables the software to avoid using part of the internal memory. The IMS register can be set to
establish the same memory mapping as used in ROM products that have different internal memory (ROM and RAM)
configurations.
The IMS register is set using 8-bit memory operation instructions.
A RESET input sets the IMS register to FFH.
Figure 5-1.
IMS
Internal Memory Switching (IMS) Register
7
6
5
4
3
2
1
0
Address
After Reset
R/W
IMS7
IMS6
IMS5
IMS4
IMS3
IMS2
IMS1
IMS0
0FFFCH
FFH
W
IMS0-7
Memory Size
FFH
Same as the µPD784038Y
EEH
Same as the µPD784037Y
DCH
Same as the µPD784036Y
CCH
Same as the µPD784035Y
The IMS is not contained in a mask ROM product (µPD784035Y, µPD784036Y, µPD784037Y, or µPD784038Y).
But the action is not affected if the write command to the IMS is executed to the mask ROM product.
20
µPD78P4038Y
6.
PROM PROGRAMMING
The µPD78P4038Y has an on-chip 128-KB PROM device for use as program memory. When programming, set
the VPP and RESET pins for PROM programming mode. See (2) in Chapter 2 with regard to handling of other, unused
pins.
6.1
Operation Mode
PROM programming mode is selected when +5 V or +12.5 V is added to the VPP pin or low-level input is added
to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin, and PGM pin as shown
in Table 6-1 below.
In addition, the PROM contents can be read by setting read mode.
Table 6-1. PROM Programming Operation Mode
Pin
RESET
VPP
VDD
CE
OE
PGM
D0-D7
L
+12.5 V
+6.5 V
H
L
H
Data input
Page write
H
H
L
High impedance
Byte write
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
×
H
H
High impedance
×
L
L
L
L
H
Data output
Output disable
L
H
×
High impedance
Standby
H
×
×
High impedance
Operation Mode
Page data latch
Read
+5 V
+5 V
Remark × = L or H
21
µPD78P4038Y
(1) Read mode
Set CE to L and OE to L to set read mode.
(2) Output disable mode
Set OE to H to set high impedance for data output and output disable mode.
Consequently, if several µPD78P4038Y devices are connected to a data bus, the OE pins can be controlled to
select data output from any of the devices.
(3) Standby mode
Set CE to H to set standby mode.
In this mode, data output is set to high impedance regardless of the OE setting.
(4) Page data latch mode
At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode.
In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit.
(5) Page write mode
After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program
pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting
both CE and OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X ≤ 10).
(6) Byte write mode
Adding a 0.1 ms program pulse (active, low) to the PGM pin with both CE and OE set to H causes byte write
to be executed. Later, setting OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X ≤ 10).
(7) Program verify mode
Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each
write operation.
(8) Program inhibit mode
Program inhibit mode is used to write to a single device when several µPD78P4038Y devices are connected in
parallel to OE , VPP, and D0 to D7 pins.
Use the page write mode or byte write mode described above for each write operation. Write operations cannot
be done for devices in which the PGM pin has been set to H.
22
µPD78P4038Y
6.2
PROM Write Sequence
Figure 6-1.
Page Program Mode Flowchart
Start
Address = G
VDD = +6.5 V, VPP = +12.5 V
X=0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Address = Address + 1
Latch
No
X=X+1
X = 10 ?
Yes
0.1 ms program pulse
Verify 4 bytes
Fail
Pass
No
Address = N ?
Yes
VDD = 4.5-5.5 V, VPP = VDD
Pass
Verify all bytes
Fail
All pass
Write end
Defective
Remark G = Start address
N = Program end address
23
µPD78P4038Y
Figure 6-2.
Page data latch
Page Program Mode Timing
Page program
Program verify
A2-A16
A0, A1
D0-D7
Data input
VPP
VPP
VDD
VDD+1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
24
Data output
µPD78P4038Y
Figure 6-3. Byte Program Mode Flowchart
Start
Address = G
VDD = +6.5 V, VPP = +12.5 V
X= 0
No
X= X + 1
X = 10 ?
Yes
0.1 ms program pulse
Address = Address + 1
Verify
Fail
Pass
No
Address = N ?
Yes
VDD = 4.5-5.5 V, VPP = VDD
Pass
Verify all bytes
Fail
All pass
Write end
Defective
Remark G = Start address
N = Program end address
25
µPD78P4038Y
Figure 6-4. Byte Program Mode Timing
Program
Program verify
A0-A16
D0-D7
Data input
Data output
VPP
VPP
VDD
VDD+1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
Cautions 1. Add VDD before VPP, and turn off the VDD after VPP.
2. Do not allow VPP to exceed +13.5 V including overshoot.
3. Reliability problems may result if the device is inserted or pulled out while +12.5 V is applied
at VPP.
26
µPD78P4038Y
6.3
PROM Read Sequence
Follow this sequence to read the PROM contents to an external data bus (D0 to D7).
(1) Set the RESET pin to low level and add +5 V to the VPP pin. See (2) in Chapter 2 with regard to handling of
other, unused pins.
(2) Add +5 V to the VDD and VPP pins.
(3) Input the data address to be read to pins A0 to A16.
(4) Set read mode.
(5) Output the data to pins D0 to D7.
Figure 6-5 shows the timing of steps (2) to (5) above.
Figure 6-5.
A0-A16
PROM Read Timing
Address input
CE (input)
OE (input)
D0-D7
Hi-Z
Data output
Hi-Z
27
µPD78P4038Y
7. ERASURE CHARACTERISTICS (µPD78P4038YKK-T ONLY)
Data written in the µPD78P4038YKK-T program memory can be erased (FFH); therefore users can write other
data in the memory.
To erase the written data, expose the erasure window to light with a wavelength shorter than approx. 400 nm. Normally,
ultraviolet light with a wavelength of 254 nm is employed. The amount of light required to completely erase the data
is as follows:
• Intensity of ultraviolet light × erasing time: 57.6 W•s/cm2 min.
• Erasing time: About 80 minutes (When using a 12,000 µW/cm2 ultraviolet lamp. It may, however, take more time
due to lamp deterioration, dirt on the erasure window, or the like.)
The ultraviolet lamp should be placed within 2.5 cm from the erasure window during erasure. In addition, if a filter
is attached to the ultraviolet lamp, remove the filter before erasure.
8. PROTECTIVE FILM COVERING THE ERASURE WINDOW (µPD78P4038YKK-T ONLY)
To prevent EPROM from being erased inadvertently by light other than that from the lamp used for erasing EPROM,
or to prevent the internal circuits other than EPROM from malfunctioning by light, stick a protective film on the erasure
window except when EPROM is to be erased.
9. QUALITY
The µPD78P4038YKK-T is not intended for use in mass-produced products; they do not have reliability high enough
for such purposes. Their use should be restricted to functional evaluation in experiment or trial manufacture.
10. SCREENING ONE-TIME PROM PRODUCTS
NEC cannot execute a complete test of one-time PROM products (µPD78P4038YGC-3B9, µPD78P4038YGC8BT, and µPD78P4038YGK-BE9) due to their structure before shipment. It is recommended that you screen (verify)
PROM products after writing necessary data into them and storing them at 125°C for 24 hours.
28
µPD78P4038Y
11. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Supply voltage
Input voltage
Symbol
Rating
Unit
VDD
–0.5 to +7.0
V
AVDD
AVSS to VDD + 0.5
V
AVSS
–0.5 to +0.5
V
VI1
–0.5 to VDD + 0.5
V
–0.5 to +13.5
V
–0.5 to VDD + 0.5
V
At one pin
15
mA
Total of all output pins
100
mA
At one pin
–10
mA
Total of all output pins
–100
mA
VI2
Output voltage
VO
Output low current
IOL
Output high current
IOH
Conditions
TEST/VPP pin and
P21/INTP0/A9 pin in PROM
programming mode
A/D converter reference input
voltage
AVREF1
–0.5 to VDD + 0.3
V
D/A converter reference input
voltage
AVREF2
–0.5 to VDD + 0.3
V
AVREF3
–0.5 to VDD + 0.3
V
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the
product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.
29
µPD78P4038Y
OPERATING CONDITIONS
• Operating ambient temperature (TA)
: –40 to +85°C
• Rise time and fall time (tr, tf) (at pins which are not specified) : 0 to 200 µs
• Power supply voltage and clock cycle time
: See Figure 11-1.
Figure 11-1. Power Supply Voltage and Clock Cycle Time
10,000
Clock cycle time tCYK [ns]
4,000
1,000
Guaranteed
operating
range
125
100
62.5
10
0
1
2
3
4
5
Power supply voltage [V]
6
7
CAPACITANCE (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Input capacitance
CI
Output capacitance
CO
I/O capacitance
CIO
30
Conditions
f = 1 MHz
0 V on pins other than measured pins
MIN.
TYP.
MAX.
Unit
10
pF
10
pF
10
pF
µPD78P4038Y
OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = +4.5 to 5.5 V, VSS = 0 V)
Resonator
Recommended Circuit
Ceramic resonator
or crystal
VSS1 X1
C1
MAX.
Unit
Oscillator frequency (fXX)
4
32
MHz
X1 input frequency (fX)
4
32
MHz
X1 input rise and fall times
(tXR, tXF)
0
10
ns
X1 input high-level and lowlevel widths (tWXH, tWXL)
10
125
ns
C2
X2
HCMOS
inverter
MIN.
X2
External clock
X1
Parameter
Caution When using the system clock generator, run wires in the portion surrounded by broken lines
according to the following rules to avoid effects such as stray capacitance:
• Minimize the wiring.
• Never cause the wires to cross other signal lines.
• Never cause the wires to run near a line carrying a large varying current.
• Cause the grounding point of the capacitor of the oscillator circuit to have the same potential
as VSS1. Never connect the capacitor to a ground pattern carrying a large current.
• Never extract a signal from the oscillator.
31
µPD78P4038Y
OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = +2.7 to 5.5 V, VSS = 0 V)
Resonator
Recommended Circuit
Ceramic resonator
or crystal
VSS1 X1
C1
MAX.
Unit
Oscillator frequency (fXX)
4
16
MHz
X1 input frequency (fX)
4
16
MHz
X1 input rise and fall times
(tXR, tXF)
0
10
ns
X1 input high-level and lowlevel widths (tWXH, tWXL)
10
125
ns
C2
X2
HCMOS
inverter
MIN.
X2
External clock
X1
Parameter
Caution When using the system clock generator, run wires in the portion surrounded by broken lines
according to the following rules to avoid effects such as stray capacitance:
•
Minimize the wiring.
•
Never cause the wires to cross other signal lines.
•
Never cause the wires to run near a line carrying a large varying current.
•
Cause the grounding point of the capacitor of the oscillator circuit to have the same potential
as VSS1. Never connect the capacitor to a ground pattern carrying a large current.
•
32
Never extract a signal from the oscillator.
µPD78P4038Y
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VIL1
For pins other than those described in
Notes 1, 2, 3, 4, and 6
–0.3
0.3VDD
V
VIL2
For pins described in Notes 1, 2, 3, 4,
and 6
–0.3
0.2VDD
V
VIL3
VDD = +5.0 V ± 10%
For pins described in Notes 2, 3, and 4
–0.3
+0.8
V
VIH1
For pins other than those described in
Notes 1 and 6
0.7VDD
VDD + 0.3
V
VIH2
For pins described in Notes 1 and 6
0.8VDD
VDD + 0.3
V
VIH3
VDD = +5.0 V ± 10%
For pins described in Notes 2, 3, and 4
2.2
VDD + 0.3
V
VOL1
IOL = 2 mA
For pins other than those described in
Note 6
0.4
V
VOL2
IOL = 3 mA
For pins described in Note 6
0.4
V
IOL = 6 mA
For pins described in Note 6
0.6
V
VOL3
VDD = +5.0 V ± 10%
IOL = 8 mA
For pins described in Notes 2 and 5
1.0
V
VOH1
IOH = –2 mA
VDD – 1.0
V
VOH2
VDD = +5.0 V ± 10%
IOH = –5 mA
For pins described in Note 4
VDD – 1.4
V
X1 input low current
IIL
EXTC = 0
0 V ≤ VI ≤ VIL2
–30
µA
X1 input high current
IIH
EXTC = 0
VIH2 ≤ VI ≤ VDD
+30
µA
Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,
P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, TEST
2. P40/AD0 to P47/AD7, P50/A8 to P57/A15
3. P60/A16 to P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK
4. P00 to P07
5. P10 to P17
6. P32/SCK0/SCL, P33/SO0/SDA
33
µPD78P4038Y
DC CHARACTERISTICS (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Symbol
Conditions
Input leakage current
IL|
Output leakage current
VDD supply current
Parameter
MAX.
Unit
0 V ≤ VI ≤ VDD
For pins other than X1 when EXTC = 0
±10
µA
ILO
0 V ≤ VO ≤ VDD
±10
µA
IDD1
Operation mode
IDD2
IDD3
Pull-up resistor
34
RL
HALT mode
IDLE mode
(EXTC = 0)
VI = 0 V
MIN.
TYP.
fXX = 32 MHz
VDD = +5.0 V ± 10%
25
45
mA
fXX = 16 MHz
VDD = +2.7 to 3.3 V
12
25
mA
fXX = 32 MHz
VDD = +5.0 V ± 10%
13
26
mA
fXX = 16 MHz
VDD = +2.7 to 3.3 V
8
12
mA
fXX = 32 MHz
VDD = +5.0 V ± 10%
12
mA
fXX = 16 MHz
VDD = +2.7 to 3.3 V
8
mA
80
kΩ
15
µPD78P4038Y
AC CHARACTERISTICS (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter
Address setup time
ASTB high-level width
Address hold time (to ASTB↓)
Symbol
tSAST
tWSTH
tHSTLA
Address hold time (to RD↑)
tHRA
Delay from address to RD↓
tDAR
Address float time (to RD↓)
tFRA
Delay from address to data input
tDAID
Delay from ASTB↓ to data input
Delay from RD↓ to data input
tDSTID
tDRID
Conditions
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
MIN.
MAX.
Unit
(0.5 + a) T – 15
ns
(0.5 + a) T – 31
ns
(0.5 + a) T – 17
ns
(0.5 + a) T – 40
ns
0.5T – 24
ns
0.5T – 34
ns
0.5T – 14
ns
(1 + a) T – 9
ns
(1 + a) T – 15
ns
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
0
ns
(2.5 + a + n) T – 37
ns
(2.5 + a + n) T – 52
ns
(2 + n) T – 40
ns
(2 + n) T – 60
ns
(1.5 + n) T – 50
ns
(1.5 + n) T – 70
ns
Delay from ASTB↓ to RD↓
tDSTR
0.5T – 9
ns
Data hold time (to RD↑)
tHRID
0
ns
Delay from RD↑ to address active
tDRA
0.5T – 8
ns
0.5T – 12
ns
1.5T – 8
ns
1.5T – 12
ns
0.5T – 17
ns
(1.5 + n) T – 30
ns
(1.5 + n) T – 40
ns
0.5T – 14
ns
(1 + a) T – 5
ns
(1 + a) T – 15
ns
Delay from RD↑ to ASTB↑
tDRST
RD low-level width
tWRL
Address hold time (to WR↑)
tHWA
Delay from address to WR↓
tDAW
Delay from ASTB↓ to data output
tDSTOD
Delay from WR↓ to data output
tDWOD
Delay from ASTB↓ to WR↓
tDSTW
After program
is read
VDD = +5.0 V ± 10%
After data is
read
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
0.5T – 9
0.5T + 19
ns
0.5T + 35
ns
0.5T – 11
ns
ns
Remarks T: tCYK (system clock cycle time)
a:
1 (during address wait), otherwise, 0
n:
Number of wait states (n ≥ 0)
35
µPD78P4038Y
(1) Read/write operation (2/2)
Parameter
Data setup time (to WR↑)
Data hold time (to
WR↑)Note
Symbol
tSODW
tHWOD
Delay from WR↑ to ASTB↑
tDWST
WR low-level width
tWWL
Conditions
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
MIN.
MAX.
Unit
(1.5 + n) T – 30
ns
(1.5 + n) T – 40
ns
0.5T – 5
ns
0.5T – 25
ns
0.5T – 12
ns
(1.5 + n) T – 30
ns
(1.5 + n) T – 40
ns
Note The hold time includes the time during which VOH1 and VOL1 are held under the load conditions of
CL = 50 pF and RL = 4.7 kΩ.
Remarks T: tCYK (system clock cycle time)
n:
Number of wait states (n ≥ 0)
(2) Bus hold timing
Parameter
Delay from HLDRQ↑ to float
Symbol
Conditions
MIN.
tFHQC
Delay from HLDRQ↑ to HLDAK↑ tDHQHHAH VDD = +5.0 V ± 10%
Delay from float to HLDAK↑
Delay from HLDRQ↓ to HLDAK↓
Delay from HLDAK↓ to active
tDCFHA
tDHQLHAL
tDHAC
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
Remarks T: tCYK (system clock cycle time)
36
a:
1 (during address wait), otherwise, 0
n:
Number of wait states (n ≥ 0)
MAX.
Unit
(6 + a + n) T + 50
ns
(7 + a + n) T + 30
ns
(7 + a + n) T + 40
ns
1T + 30
ns
2T + 40
ns
2T + 60
ns
1T – 20
ns
1T – 30
ns
µPD78P4038Y
(3) External wait timing
Parameter
Symbol
Delay from address to WAIT↓ input
tDAWT
Delay from ASTB↓ to WAIT↓ input
Hold time from ASTB↓ to WAIT
Delay from ASTB↓ to WAIT↑
Delay from RD↓ to WAIT↓ input
Hold time from RD↓ to WAIT↓
Delay from RD↓ to WAIT↑
Delay from WAIT↑ to data input
tDSTWT
tHSTWTH
tDSTWTH
tDRWTL
tHRWT
tDRWTH
tDWTID
Conditions
MIN.
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
Unit
(2 + a) T – 40
ns
(2 + a) T – 60
ns
1.5T – 40
ns
1.5T – 60
ns
(0.5 + n) T + 5
ns
(0.5 + n) T +10
ns
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
MAX.
(1.5 + n) T – 40
ns
(1.5 + n) T – 60
ns
T – 50
ns
T – 70
ns
nT + 5
ns
nT + 10
ns
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
(1 + n) T – 40
ns
(1 + n) T – 60
ns
0.5T – 5
ns
0.5T – 10
ns
Delay from WAIT↑ to WR↑
tDWTW
0.5T
ns
Delay from WAIT↑ to RD↑
tDWTR
0.5T
ns
Delay from WR↓ to WAIT↓ input
tDWWTL
Hold time from WR↓ to WAIT
Delay from WR↓ to WAIT↑
tHWWT
tDWWTH
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
T – 50
ns
T – 75
ns
nT + 5
ns
nT + 10
ns
VDD = +5.0 V ± 10%
(1 + n) T – 40
ns
(1 + n) T – 70
ns
MAX.
Unit
Remarks T: tCYK (system clock cycle time)
a:
1 (during address wait), otherwise, 0
n:
Number of wait states (n ≥ 0)
(4) Refresh timing
Parameter
Symbol
Random read/write cycle time
tRC
REFRQ low-level pulse width
tWRFQL
Delay from ASTB↓ to REFRQ
tDSTRFQ
Delay from RD↑ to REFRQ
tDRRFQ
Delay from WR↑ to REFRQ
tDWRFQ
Delay from REFRQ↑ to ASTB
tDRFQST
REFRQ high-level pulse width
tWRFQH
Conditions
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
MIN.
3T
ns
1.5T – 25
ns
1.5T – 30
ns
0.5T – 9
ns
1.5T – 9
ns
1.5T – 9
ns
0.5T – 15
ns
1.5T – 25
ns
1.5T – 30
ns
Remark T: tCYK (system clock cycle time)
37
µPD78P4038Y
SERIAL OPERATION (TA = –40 to +85°C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V)
(1) CSI
Parameter
Symbol
Serial clock cycle time (SCK0)
tCYSK0
Conditions
Input
MIN.
External clock
When SCK0 and SO0 are CMOS I/O
Output
Serial clock low-level width
(SCK0)
tWSKL0
Input
External clock
When SCK0 and SO0 are CMOS I/O
Output
Serial clock high-level width
(SCK0)
tWSKH0
Input
External clock
When SCK0 and SO0 are CMOS I/O
Output
MAX.
Unit
10/fXX + 380
ns
T
µs
5/fXX + 150
ns
0.5T – 40
µs
5/fXX + 150
ns
0.5T – 40
µs
SI0 setup time (to SCK0↑)
tSSSK0
40
ns
SI0 hold time (to SCK0↑)
tHSSK0
5/fXX + 40
ns
SO0 output delay time
(to SCK0↓)
tDSBSK1
CMOS push-pull output
(3-wire serial I/O mode)
0
5/f XX + 150
ns
tDSBSK2
Open-drain output
(2-wire serial I/O mode), RL = 1 kΩ
0
5/f XX + 400
ns
Remarks 1. The values in this table are those when CL is 100 pF.
2. T
:
3. fXX :
Serial clock cycle set by software. The minimum value is 16/fXX.
Oscillator frequency
(2) I2C
Parameter
Symbol
I2C Bus in Standard Mode
fXX = 4 to 32 MHz
I2C Bus in Standard Mode
fXX = 8 to 32 MHz
MIN.
MAX.
MIN.
MAX.
100
0
400
Unit
SCL clock frequency
fSCL
0
Time to hold low SCL clock
tLOW
4.7
1.3
µs
Time to hold high SCL clock
µs
tHIGH
4.0
0.6
Data hold time
tHD; DAT
300
300
Data setup time
tSU; DAT
250
900
100
kHz
ns
ns
Rise time of SDA or SCL
signal
tR
1,000
20 + 0.1Cb
300
ns
Fall time of SDA or SCL signal
tF
300
20 + 0.1Cb
300
ns
Load capacitance of each bus
line
Cb
400
400
pF
38
µPD78P4038Y
(3) IOE1, IOE2
Parameter
Serial clock cycle time
(SCK1, SCK2)
Serial clock low-level width
(SCK1, SCK2)
Serial clock high-level width
(SCK1, SCK2)
Symbol
tCYSK1
tWSKL1
tWSKH1
Conditions
Input
VDD = +5.0 V ± 10%
MIN.
MAX.
Unit
250
ns
500
ns
Output
Internal, divided by 16
T
ns
Input
VDD = +5.0 V ± 10%
85
ns
210
ns
0.5T – 40
ns
85
ns
210
ns
0.5T – 40
ns
Output
Internal, divided by 16
Input
VDD = +5.0 V ± 10%
Output
Internal, divided by 16
Setup time for SI1 and SI2
(to SCK1, SCK2↑)
tSSSK1
40
ns
Hold time for SI1 and SI2
(to SCK1, SCK2↑)
tHSSK1
40
ns
Output delay time for SO1 and
SO2 (to SCK1, SCK2↓)
tDSOSK
0
Output hold time for SO1 and
SO2 (to SCK1, SCK2↑)
tHSOSK
When data is transferred
50
ns
ns
0.5tCYSK1 – 40
Remarks 1. The values in this table are those when CL is 100 pF.
2. T: Serial clock cycle set by software. The minimum value is 16/fXX.
(4) UART, UART2
Parameter
ASCK clock input cycle time
ASCK clock low-level width
ASCK clock high-level width
Symbol
tCYASK
tWASKL
tWASKH
Conditions
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
MIN.
MAX.
Unit
125
ns
250
ns
52.5
ns
85
ns
52.5
ns
85
ns
39
µPD78P4038Y
CLOCK OUTPUT OPERATION
Parameter
Symbol
CLKOUT cycle time
tCYCL
CLKOUT low-level width
tCLL
CLKOUT high-level width
tCLR
CLKOUT rise time
tCLF
CLKOUT fall time
Remarks n:
tCLH
Conditions
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
MIN.
MAX.
Unit
nT
ns
0.5tCYCL – 10
ns
0.5tCYCL – 20
ns
0.5tCYCL – 10
ns
0.5tCYCL – 20
ns
VDD = +5.0 V ± 10%
VDD = +5.0 V ± 10%
10
ns
20
ns
10
ns
20
ns
MAX.
Unit
Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16)
T: tCYK (system clock cycle time)
OTHER OPERATIONS
Parameter
Symbol
Conditions
MIN.
NMI low-level width
tWNIL
10
µs
NMI high-level width
tWNIH
10
µs
INTP0 low-level width
tWIT0L
4tCYSMP
ns
INTP0 high-level width
tWIT0H
4tCYSMP
ns
Low-level width for INTP1INTP3 and CI
tWIT1L
4tCYCPU
ns
High-level width for INTP1INTP3 and CI
tWIT1H
4tCYCPU
ns
Low-level width for INTP4 and
INTP5
tWIT2L
10
µs
High-level width for INTP4 and
INTP5
tWIT2H
10
µs
RESET low-level width
tWRSL
10
µs
RESET high-level width
tWRSH
10
µs
Remarks tCYSMP: Sampling clock set by software
tCYCPU: CPU operation clock set by software in the CPU
40
µPD78P4038Y
A/D CONVERTER CHARACTERISTICS
(TA = –40 to +85°C, VDD = AVDD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
TYP.
MAX.
errorNote
Unit
bit
8
Resolution
Total
MIN.
VDD = AVDD = +5.0 V ± 10%
1.0
%
VDD = AVDD = +2.7 to 4.5 V
TA = -10 to +85°C
1.0
%
Linearity calibrationNote
0.8
%
Quantization error
±1/2
LSB
Conversion time
Sampling time
tCONV
tSAMP
FR = 1
120
tCYK
FR = 0
180
tCYK
FR = 1
24
tCYK
FR = 0
36
tCYK
Analog input voltage
VIAN
–0.3
AVREF1 + 0.3
V
Analog input impedance
RAN
1,000
AVREF1 current
AIREF1
0.5
1.5
mA
AVDD supply current
AIDD1
fXX = 32 MHz, CS = 1
2.0
5.0
mA
AIDD2
STOP mode, CS = 0
1.0
20
µA
MΩ
Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value.
Remark tCYK: System clock cycle time
41
µPD78P4038Y
D/A CONVERTER CHARACTERISTICS (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
8
Resolution
VDD = AVDD = +2.7 to 5.5 V
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Load conditions: VDD = AVDD = AVREF2
2 MΩ, 30 pF
= +2.7 to 5.5 V
AVREF3 = 0 V
VDD = AVDD = +2.7 to 5.5 V
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Load conditions: 2 MΩ, 30 pF
Settling time
Analog reference voltage
RO
DACS0, 1 = 55 H
Unit
bit
Load conditions: VDD = AVDD = AVREF2
4 MΩ, 30 pF
= +2.7 to 5.5 V
AVREF3 = 0 V
Total error
Output resistance
MAX.
0.6
%
0.8
%
0.8
%
1.0
%
10
µs
10
kΩ
AVREF2
0.75VDD
VDD
V
AVREF3
0
0.25VDD
V
4
kΩ
RAIREF
Reference power supply
input current
AIREF2
0
5
mA
AIREF3
–5
0
mA
42
DACS0, 1 = 55 H
8
Resistance of AVREF2 and
AVREF3
µPD78P4038Y
DATA RETENTION CHARACTERISTICS (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
TYP.
2.5
MAX.
Unit
5.5
V
Data retention voltage
VDDDR
STOP mode
Data retention current
IDDDR
VDDDR = +2.7 to 5.5 V
30
50
µA
VDDDR = +2.5 V
10
40
µA
VDD rise time
tRVD
200
µs
VDD fall time
tFVD
200
µs
VDD hold time
(to STOP mode setting)
tHVD
0
ms
STOP clear signal input time
tDREL
0
ms
Oscillation settling time
tWAIT
30
ms
Ceramic resonator
5
ms
Specific pinsNote
0
0.1VDDDR
V
0.9VDDDR
VDDDR
V
Input low voltage
VIL
Input high voltage
VIH
Crystal
Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1,
P26/INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins
AC TIMING TEST POINTS
VDD - 1 V
0.8VDD or 2.2 V
0.8VDD or 2.2 V
Test points
0.45 V
0.8 V
0.8 V
43
µPD78P4038Y
TIMING WAVEFORM
(1) Read operation
tWSTH
ASTB
tSAST
tDRST
tDSTID
tHSTLA
A8-A19
tDAID
tHRA
AD0-AD7
tDSTR
tFRA
tDAR
tHRID
tDRID
tDRA
RD
tWRL
(2) Write operation
tWSTH
ASTB
tSAST
tDWST
tDSTOD
tHSTLA
A8-A19
tHWA
AD0-AD7
tDSTW
tDAW
tHWOD
tDWOD
tSODW
WR
tWWL
44
µPD78P4038Y
HOLD TIMING
ADTB, A8-A19,
AD0-AD7, RD, WR
tFHQC
tDCFHA
tDHAC
HLDRQ
tDHQLHAL
tDHQHHAH
HLDAK
EXTERNAL WAIT SIGNAL INPUT TIMING
(1) Read operation
ASTB
tDSTWT
tDSTWTH
tHSTWTH
A8-A19
AD0-AD7
tDAWT
tDWTID
RD
tDWTR
tDRWTL
WAIT
tHRWT
tDRWTH
(2) Write operation
ASTB
tDSTWT
tDSTWTH
tHSTWTH
A8-A19
AD0-AD7
tDAWT
WR
tDWTW
tDWWTL
WAIT
tHWWT
tDWWTH
45
µPD78P4038Y
REFRESH TIMING WAVEFORM
(1) Random read/write cycle
tRC
ASTB
WR
tRC
tRC
tRC
tRC
RD
(2) When refresh memory is accessed for a read and write at the same time
ASTB
RD, WR
tDSTRFQ
tDRFQST
tWRFQH
REFRQ
tWRFQL
(3) Refresh after a read
ASTB
tDRFQST
RD
tDRRFQ
REFRQ
tWRFQL
(4) Refresh after a write
ASTB
tDRFQST
WR
tDWRFQ
REFRQ
tWRFQL
46
µPD78P4038Y
SERIAL OPERATION
(1) CSI
tWSKL0
tWSKH0
SCK
tSSSK0 tHSSK0
tCYSK0
Input data
SI
tDSBSK1
Output data
SO
(2) I2C
tR
tF
tHIGH
tLOW
SCL
SDA
tHD;DAT
tSU;DAT
(3) IOE1, IOE2
tWSKL1
tWSKH1
SCK
tSSSK1
tCYSK1
tHSSK1
Input data
SI
tDSOSK
tHSOSK
Output data
SO
(4) UART, UART2
tWASKH
tWASKL
ASCK,
ASCK2
tCYASK
47
µPD78P4038Y
CLOCK OUTPUT TIMING
tCLH
tCLL
CLKOUT
tCLR
tCLF
tCYCL
INTERRUPT INPUT TIMING
tWNIH
tWNIL
tWIT0H
tWIT0L
tWIT1H
tWIT1L
tWIT2H
tWIT2L
tWRSH
tWRSL
NMI
INTP0
CI,
INTP1-INTP3
INTP4, INTP5
RESET INPUT TIMING
RESET
48
µPD78P4038Y
EXTERNAL CLOCK TIMING
tWXH
tWXL
X1
tXR
tXF
tCYX
DATA RETENTION CHARACTERISTICS
STOP mode setting
VDD
VDDDR
tHVD
tFVD
tRVD
tDREL
tWAIT
RESET
NMI
(Clearing by falling edge)
NMI
(Clearing by rising edge)
49
µPD78P4038Y
DC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5°C, VSS = 0 V)
Symbol
SymbolNote 1
High-level input
voltage
VIH
VIH
Low-level input
voltage
VIL
VIL
Input leakage current
ILIP
ILI
High-level output
voltage
VOH
VOH
IOH = –400 µA
Low-level output
voltage
VOL
VOL
IOL = 2.1 mA
0.45
V
Output leakage
current
ILO
–
0 ≤ VO ≤ VDDP, OE = VIH
±10
µA
VDDP
VCC
Parameter
VDDP supply voltage
VPP supply voltage
VPP
VPP
Conditions
MAX.
Unit
2.2
VDDP + 0.3
V
-0.3
0.8
V
±10
µA
MIN.
0 ≤ VI ≤ VDDPNote 2
VPP supply current
IDD
IPP
IDD
IPP
Program memory write mode
6.25
6.5
6.75
V
Program memory read mode
4.5
5.0
5.5
V
Program memory write mode
12.2
12.5
12.8
V
VPP = VDDP
V
Program memory write mode
10
40
mA
Program memory read mode
10
40
mA
Program memory write mode
5
50
mA
Program memory read mode
1.0
100
µA
Notes 1. Symbols for the corresponding µPD27C1001A
2. The VDDP represents the VDD pin as viewed in the programming mode.
50
V
2.4
Program memory read mode
VDDP supply current
TYP.
µPD78P4038Y
AC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5°C, VSS = 0 V)
PROM Write Mode (Page Program Mode)
Parameter
SymbolNote 1
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time
tAS
2
µs
CE set time
tCES
2
µs
Input data setup time
tDS
2
µs
Address hold time
tAH
2
µs
tAHL
2
µs
tAHV
0
µs
Input data hold time
tDH
2
µs
Output data hold time
tDF
0
VPP setup time
tVPS
2
µs
VDDP setup time
tVDSNote 2
2
µs
Initial program pulse width
tPW
0.095
OE set time
tOES
2
Valid data delay time from OE
tOE
OE pulse width in the data latch
tLW
1
µs
PGM setup time
tPGMS
2
µs
CE hold time
tCEH
2
µs
OE hold time
tOEH
2
µs
130
0.1
0.105
ns
ms
µs
1
2
ns
Notes 1. These symbols (except tVDS) correspond to those of the corresponding µPD27C1001A.
2. For µPD27C1001A, read tVDS as tVCS.
51
µPD78P4038Y
PROM Write Mode (Byte Program Mode)
SymbolNote 1
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time
tAS
2
µs
CE set time
tCES
2
µs
Input data setup time
tDS
2
µs
Address hold time
tAH
2
µs
Input data hold time
tDH
2
µs
Output data hold time
tDF
0
VPP setup time
tVPS
2
µs
VDDP setup time
tVDSNote 2
2
µs
Initial program pulse width
tPW
0.095
OE set time
tOES
2
Valid data delay time from OE
tOE
130
0.1
0.105
ns
ms
µs
1
2
ns
Notes 1. These symbols (except tVDS) correspond to those of the corresponding µPD27C1001A.
2. For µPD27C1001A, read tVDS as tVCS.
PROM Read Mode
SymbolNote 1
Parameter
Conditions
MIN.
Data output time from address
tACC
CE = OE = VIL
Delay from CE ↓ to data output
tCE
OE = VIL
Delay from OE ↓ to data output
tOE
CE = VIL
tDF
CE = VIL or OE = VIL
0
tOH
CE = OE = VIL
0
Data hold time to OE↑ or
CE↑ Note 2
Data hold time to address
TYP.
MAX.
Unit
200
ns
1
2
µs
1
2
µs
60
ns
Notes 1. These symbols correspond to those of the corresponding µPD27C1001A.
2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
52
ns
µPD78P4038Y
PROM Write Mode Timing (Page Program Mode)
Page data latch
Page program
Program verify
A2-A16
tAS
tAHL
tAHV
tDS
tDH
tDF
A0, A1
D0-D7
Hi-Z
Hi-Z
tVPS
Data input
Hi-Z
tPGMS
tOE
Data
output
tAH
VPP
VPP
VDDP
tVDS
VDDP + 1.5
VDDP
VDDP
tCES
tOEH
VIH
CE
VIL
tCEH
tPW
VIH
PGM
VIL
VIH
tLW
tOES
OE
VIL
53
µPD78P4038Y
PROM Write Mode Timing (Byte Program Mode)
Program
Program verify
A0-A16
tAS
D0-D7
tDF
Hi-Z
tDS
Hi-Z
Data input
tDS
Hi-Z
Data output
tDH
tAH
VPP
VPP
VDDP
tVPS
VDDP + 1.5
VDDP
VDDP
tVDS
VIH
CE
VIL
tCES
tPW
VIH
PGM
VIL
tOES
tOE
VIH
OE
VIL
Cautions 1. VDDP must be applied before VPP, and must be cut after VPP.
2. VPP including overshoot must not exceed +13.5 V.
3. Plugging in or out the board with the VPP pin supplied with 12.5 V may adversely affect its
reliability.
PROM Read Mode Timing
Valid address
A0-A16
CE
tCE
OE
tACC
D0-D7
Note 1
Hi-Z
tOE
tDF
Note 1
Note 2
tOH
Data output
Hi-Z
Notes 1. For reading within tACC, the delay of the OE input from falling edge of CE must be within tACC-tOE.
2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
54
µPD78P4038Y
12. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
C D
S
R
Q
21
20
80
1
F
J
G
I
H
M
K
P
M
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
17.2±0.4
0.677±0.016
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.2±0.4
0.677±0.016
F
0.825
0.032
G
0.825
0.032
H
0.30±0.10
0.012 +0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.6±0.2
L
0.8±0.2
M
0.15 +0.10
–0.05
0.063±0.008
0.031 +0.009
–0.008
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7±0.1
0.106 +0.005
–0.004
Q
0.1±0.1
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
S80GC-65-3B9-5
55
µPD78P4038Y
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
C
S
D
R
Q
80
1
21
20
F
G
H
I
M
J
P
K
M
N
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
L
ITEM
MILLIMETERS
INCHES
A
17.20±0.20
0.677±0.008
B
14.00±0.20
0.551 +0.009
–0.008
C
14.00±0.20
0.551 +0.009
–0.008
D
17.20±0.20
0.677±0.008
F
0.825
0.032
G
0.825
0.032
H
0.32±0.06
0.013 +0.002
–0.003
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.60±0.20
0.063±0.008
L
0.80±0.20
0.031 +0.009
–0.008
M
0.17 +0.03
–0.07
0.007 +0.001
–0.003
N
0.10
0.004
P
1.40±0.10
0.055±0.004
Q
0.125±0.075
0.005±0.003
R
3° +7°
–3°
3° +7°
–3°
S
1.70 MAX.
0.067 MAX.
P80GC-65-8BT
56
µPD78P4038Y
80 PIN PLASTIC TQFP (FINE PITCH) (12×12)
A
B
60
41
61
40
detail of lead end
C
D
S
Q
R
21
80
1
20
F
G
H
I
M
J
K
P
M
N
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
L
ITEM
MILLIMETERS
INCHES
A
14.00±0.20
0.551±0.008
B
12.00±0.20
0.472 +0.009
–0.008
C
12.00±0.20
0.472 +0.009
–0.008
D
F
14.00±0.20
1.25
0.551±0.008
0.049
G
1.25
0.049
H
0.22 +0.05
–0.04
0.009±0.002
I
0.10
0.004
J
0.50 (T.P.)
0.020 (T.P.)
K
1.00±0.20
0.039 +0.009
–0.008
L
0.50±0.20
0.020 +0.008
–0.009
M
0.145 +0.055
–0.045
0.006±0.002
N
0.10
0.004
P
1.05
0.041
Q
0.10±0.05
0.004±0.002
R
5°±5°
5°±5°
S
1.27 MAX.
0.050 MAX.
P80GK-50-BE9-5
57
µPD78P4038Y
80 PIN CERAMIC WQFN
A
Q
K
B
D
80
S
W
C
U1
T
H
U
1
I M
R
G
F
J
Z
X80KW-65A-1
NOTE
Each lead centerline is located within 0.06
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
58
ITEM
MILLIMETERS
INCHES
A
14.0 ± 0.2
0.551 ± 0.008
B
13.6
0.535
C
13.6
0.535
D
14.0 ± 0.2
0.551 ± 0.008
F
1.84
0.072
G
3.6 MAX.
0.142 MAX.
H
0.45 ± 0.10
0.018+0.004
–0.005
I
0.06
0.003
J
0.65 (T.P.)
0.024 (T.P.)
K
1.0 ± 0.15
0.039+0.007
–0.006
Q
C 0.3
C 0.012
R
0.825
0.032
S
0.825
0.032
T
R 2.0
R 0.079
U
9.0
0.354
U1
2.1
0.083
W
0.75 ± 0.15
0.030+0.006
–0.007
Z
0.10
0.004
µPD78P4038Y
13. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the µPD78P4038Y.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.
Table 13-1. Soldering Conditions for Surface-Mount Devices (1/2)
(1) µPD78P4038YGC-3B9: 80-pin plastic QFP (14 × 14 × 2.7 mm)
Soldering Process
Soldering Conditions
Symbol
Infrared ray reflow
Peak package's surface temperature: 235°C
Reflow time: 30 seconds or less (210°C or more)
Maximum allowable number of reflow processes: 3
IR35-00-3
VPS
Peak package's surface temperature: 215°C
Reflow time: 40 seconds or less (200°C or more)
Maximum allowable number of reflow processes: 3
VP15-00-3
Wave soldering
Solder temperature: 260°C or less
Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature : 120°C max. (measured on the package surface)
WS60-00-1
Partial heating method
Terminal temperature: 300°C or less
Heat time: 3 seconds or less (for one side of a device)
–
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
(2) µPD78P4038YGC-8BT: 80-pin plastic QFP (14 × 14 × 1.4 mm)
Soldering Process
Soldering Conditions
Symbol
Infrared ray reflow
Peak package's surface temperature: 235°C
Reflow time: 30 seconds or less (210°C or more)
Maximum allowable number of reflow processes: 2
IR35-00-2
VPS
Peak package's surface temperature: 215°C
Reflow time: 40 seconds or less (200°C or more)
Maximum allowable number of reflow processes: 2
VP15-00-2
Wave soldering
Solder temperature: 260°C or less
Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature : 120°C max. (measured on the package surface)
WS60-00-1
Partial heating method
Terminal temperature: 300°C or less
Heat time: 3 seconds or less (for one side of a device)
–
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
59
µPD78P4038Y
Table 13-1. Soldering Conditions for Surface-Mount Devices (2/2)
(3) µPD78P4038YGK-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Soldering Process
Soldering Conditions
Symbol
Infrared ray reflow
Peak package’s surface temperature: 235°C
Reflow time: 30 seconds or less (210°C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125°C
afterward)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be
baked before unpacking.
IR35-107-2
VPS
Peak package’s surface temperature: 215°C
Reflow time: 40 seconds or less (200°C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125°C
afterward)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be
baked before unpacking.
VP15-107-2
Partial heating method
Terminal temperature: 300°C or less
–
Heat time: 3 seconds or less (for one side of a device)
Note Maximum number of days during which the product can be stored at a temperature of 25°C and a relative
humidity of 65% or less after dry-pack package is opened.
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
60
µPD78P4038Y
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78P4038Y.
See also (5).
(1) Language processing software
RA78K4
Assembler package for all 78K/IV Series models
CC78K4
C compiler package for all 78K/IV Series models
DF784038
Device file for µPD784038Y Subseries models
CC78K4-L
C compiler library source file for all 78K/IV Series models
(2) PROM write tools
PG-1500
PROM programmer
PA-78P4026GC
PA-78P4038GK
Programmer adaptor, connects to PG-1500
PA-78P4026KK
PG-1500 controller
Control program for PG-1500
(3) Debugging tools
• When using the in-circuit emulator IE-78K4-NS
IE-78K4-NS
In-circuit emulator for all 78K/IV Series models
IE-70000-MC-PS-B
Power supply unit for IE-78K4-NS
IE-70000-98-IF-C
Interface adapter when the PC-9800 series computer (other than a notebook)
is used as the host machine
IE-70000-CD-IF
PC card and interface cable when a PC-9800 series notebook is used as the
host machine
IE-70000-PC-IF-C
Interface adapter when the IBM PC/ATTM or compatible is used as the host
machine
IE-784038-NS-EM1Note
Emulation board for evaluating µPD784038Y Subseries models
NP-80GC
Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types)
NP-80GKNote
Emulation probe for 80-pin plastic TQFP (GK-BE9 type)
EV-9200GC-80
Socket for mounting on target system board made for 80-pin plastic QFP
(GC-3B9 and GC-8BT types)
TGK-080SDW
Adapter for mounting on target system board made for 80-pin plastic TQFP
(fine pitch) (GK-BE9 type)
EV-9900
Tool used to remove the µPD78P4038YKK-T from the EV-9200GC-80
ID78K4-NS
Integrated debugger for IE-78K4-NS
SM78K4-NS
System simulator for all 78K/IV Series models
DF784038
Device file for µPD784038Y Subseries models
Note Under development
61
µPD78P4038Y
• When using the in-circuit emulator IE-784000-R
IE-784000-R
In-circuit emulator for all 78K/IV Series models
IE-70000-98-IF-B
IE-70000-98-IF-C
Interface adapter when the PC-9800 series computer (other than a notebook)
is used as the host machine
IE-70000-98N-IF
Interface adapter and cable when a PC-9800 series notebook is used as the
host machine
IE-70000-PC-IF-B
IE-70000-PC-IF-C
Interface adapter when the IBM PC/AT or compatible is used as the host
machine
IE-78000-R-SV3
Interface adapter and cable when the EWS is used as the host machine
IE-784038-NS-EM1Note
IE-784038-R-EM1
Emulation board for evaluating µPD784038Y Subseries models
IE-78400-R-EM
Emulation board for all 78K/IV Series models
IE-78K4-R-EX2Note
Conversion board for 80 pins to use the IE-784038-NS-EM1 on the
IE-784000-R. The board is not needed when the conventional product
IE-784038-R-EM1 is used.
EP-78230GC-R
Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types)
EP-78054GK-R
Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) for all
µPD784038Y Subseries
EV-9200GC-80
Socket for mounting on target system board made for 80-pin plastic QFP
(GC-3B9 and GC-8BT types)
TGK-080SDW
Adapter for mounting on target system board made for 80-pin plastic TQFP
(fine pitch) (GK-BE9 type)
EV-9900
Tool used to remove the µPD78P4038YKK-T from the EV-9200GC-80
ID78K4
Integrated debugger for IE-784000-R
SM78K4
System simulator for all 78K/IV Series models
DF784038
Device file for µPD784038Y Subseries models
Note Under development
(4) Real-time OS
RX78K/IV
Real-time OS for 78K/IV Series models
MX78K4
OS for 78K/IV Series models
62
µPD78P4038Y
(5) Notes when using development tools
• The ID78K-NS, ID78K4, and SM78K4 can be used in combination with the DF784038.
• The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784038.
• The NP-80GC is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales
representative for purchasing.
• The TGK-080SDW is a product from TOKYO ELETECH CORPORATION.
Refer to: Daimaru Kogyo, Ltd.
Tokyo Electronic Components Division (03-3820-7112)
Osaka Electronic Components Division (06-244-6672)
• The host machines and operating systems corresponding to each software are shown below.
Host Machine
[OS]
Software
PC
EWS
PC-9800 Series [WindowsTM]
HP9000 Series 700TM [HP-UXTM]
IBM PC/AT and Compatibles [Windows] SPARCstationTM [SunOSTM]
NEWSTM (RISC) [NEWS-OSTM]
RA78K4
Note
CC78K4
Note
PG-1500 controller
Note
ID78K4-NS
–
–
ID78K4
SM78K4
–
RX78K/IV
Note
MX78K4
Note
Note Software under MS-DOS
63
µPD78P4038Y
APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER (TGK-080SDW)
(1) Conversion socket (EV-9200GC-80) package drawings and recommended pattern to mount the socket
Connect the µPD78P4038YKK-T (80-pin ceramic WQFN (14 × 14 mm)) and EP-78230GC-R to the circuit board
in combination with the EV-9200GC-80.
Figure B-1. Package Drawings of EV-9200GC-80 (Reference) (unit: mm)
Based on EV-9200GC-80
(1) Package drawing (in mm)
A
E
M
B
N
O
L
K
S
J
C
D
R
F
EV-9200GC-80
Q
1
No.1 pin index
P
G
H
I
EV-9200GC-80-G0E
ITEM
64
MILLIMETERS
INCHES
A
18.0
0.709
B
14.4
0.567
C
14.4
0.567
D
18.0
0.709
E
4-C 2.0
4-C 0.079
F
0.8
0.031
G
6.0
0.236
H
16.0
0.63
I
18.7
0.736
J
6.0
0.236
K
16.0
0.63
L
18.7
0.736
M
8.2
0.323
O
8.0
0.315
N
2.5
0.098
P
2.0
0.079
Q
0.35
0.014
R
φ 2.3
φ 0.091
S
1.5
0.059
µPD78P4038Y
Figure B-2. Recommended Pattern to Mount EV-9200GC-80 on a Substrate (Reference) (unit: mm)
Based on EV-9200GC-80
(2) Pad drawing (in mm)
G
J
H
D
E
F
K
I
L
C
B
A
EV-9200GC-80-P1E
ITEM
MILLIMETERS
A
19.7
B
15.0
INCHES
0.776
0.591
C
0.65±0.02 × 19=12.35±0.05
D
+0.003
0.65±0.02 × 19=12.35±0.05 0.026 +0.001
–0.002 0.748=0.486 –0.002
0.026+0.001
–0.002
× 0.748=0.486 +0.003
–0.002
E
15.0
0.591
F
19.7
0.776
G
6.0 ± 0.05
0.236 +0.003
–0.002
H
6.0 ± 0.05
0.236 +0.003
–0.002
I
0.35 ± 0.02
0.014 +0.001
–0.001
J
φ 2.36 ± 0.03
φ 0.093+0.001
–0.002
K
φ 2.3
φ 0.091
L
φ 1.57 ± 0.03
φ 0.062+0.001
–0.002
Caution
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).
65
µPD78P4038Y
(2) Conversion adapter (TGK-080SDW) package drawings
Connect the EP-78054GK-R to the circuit board in combination with the TGK-080SDW.
Figure B-3. Package Drawings of TGK-080SDW (Reference) (unit: mm)
TGK-080SDW (TQPACK080SD + TQSOCKET080SDW)
Package dimension (unit: mm)
A
B
C
T
U
V
D
R
Q
Q
Q
M2 screw
G F E
c
e
b
H
P
a
S
O
O
O
N
K
I JJJ
d
Z
W
X
Y
L L LM
g v
f
k
u
r
t
j
s
i
q
h
p
l
Protrusion : 4 places
n
o
m
ITEM
A
B
C
D
note: Product by TOKYO ELETECH CORPORATION.
66
MILLIMETERS
18.0
11.77
0.5x19=9.5
ITEM
MILLIMETERS
0.709
0.463
INCHES
a
0.5x19=9.5±0.10
0.25
0.020x0.748=0.374±0.004
0.010
0.020x0.748=0.374
0.020
c
d
0.020x0.748=0.374
0.463
e
f
g
φ 5.3
φ 5.3
φ 1.3
φ 3.55
φ 0.3
φ 0.209
φ 0.209
φ 0.051
φ 0.140
φ 0.012
h
i
1.85±0.2
3.5
0.073±0.008
0.138
j
2.0
0.079
3.0
0.25
0.118
0.010
b
E
F
0.5
0.5x19=9.5
11.77
G
18.0
H
I
0.5
1.58
J
K
1.2
7.64
0.047
0.301
L
1.2
0.047
k
l
0.709
0.020
0.062
INCHES
M
1.58
0.062
m
14.0
0.551
N
O
1.58
1.2
0.062
0.047
n
o
1.4±0.2
1.4±0.2
0.055±0.008
0.055±0.008
P
7.64
0.301
p
h=1.8 φ 1.3
h=0.071 φ 0.051
Q
1.2
0.047
R
1.58
0.062
q
r
0~5°
5.9
0.000~0.197°
0.232
S
φ 3.55
φ 0.140
s
0.8
0.031
T
C 2.0
t
2.4
0.094
U
12.31
C 0.079
0.485
u
2.7
0.106
V
10.17
0.400
v
3.9
0.154
W
X
6.8
8.24
0.268
0.324
Y
Z
14.8
1.4±0.2
0.583
0.055±0.008
TGK-080SDW-G1E
µPD78P4038Y
APPENDIX C RELATED DOCUMENTS
Documents Related to Devices
Document Name
Document No.
English
Japanese
µPD784031Y Data Sheet
U11504E
U11504J
µPD784035Y, 784036Y, 784037Y, 784038Y Data Sheet
U10741E
U10741J
µPD78P4038Y Data Sheet
This manual
U10742J
µPD784038, 784038Y Sub-Series User's Manual, Hardware
U11316E
U11316J
–
U11090J
U10905E
U10905J
78K/IV Series Instruction Summary Sheet
–
U10594J
78K/IV Series Instruction Set
–
U10595J
78K/IV Series Application Note, Software Basic
–
U10095J
µPD784038Y Sub-Series Special Function Registers
78K/IV Series User's Manual, Instruction
Documents Related to Development Tools (User's Manual)
Document Name
Document No.
English
RA78K4 Assembler Package
Japanese
Operation
U11334E
U11334J
Language
U11162E
U11162J
U11743E
U11743J
Operation
U11572E
U11572J
Language
U11571E
U11571J
CC78K Series Library Source File
U12322E
U12322J
PG-1500 PROM Programmer
U11940E
U11940J
PG-1500 Controller PC-9800 Series (MS-DOSTM) Base
EEU-1291
EEU-704
PG-1500 Controller IBM PC Series (PC DOSTM) Base
U10540E
EEU-5008
IE-78K4-NS
To be released
U13356J
RA78K Series Structured Assembler Preprocessor
CC78K4 Series
soon
IE-784000-R
EEU-1534
U12903J
IE-784038-NS-EM1
Planned
Planned
IE-784038-R-EM1
U11383E
U11383J
EP-78230
EEU-1515
EEU-985
EP-78054GK-R
EEU-1468
EEU-932
SM78K4 System Simulator Windows Base
Reference
U10093E
U10093J
SM78K Series System Simulator
External Parts User Open
Interface Specifications
U10092E
U10092J
ID78K4-NS Integrated Debugger
Reference
U12796E
U12796J
ID78K4 Integrated Debugger Windows Base
Reference
U10440E
U10440J
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base
Reference
U11960E
U11960J
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
67
µPD78P4038Y
Documents Related to Software to Be Incorporated into the Product (User’s Manual)
Document Name
Document No.
English
78K/IV Series Real-Time OS
OS for 78K/IV Series MX78K4
Japanese
Basic
U10603E
U10603J
Installation
U10604E
U10604J
Debugger
–
U10364J
Basic
–
U11779J
Other Documents
Document Name
Document No.
English
Japanese
IC PACKAGE MANUAL
C10943X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Device
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
C11892J
Semiconductor Device Quality Control/Reliability Handbook
–
C12769J
Guide for Products Related to Microcomputer: Other Companies
–
U11416J
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
68
µPD78P4038Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to
be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
69
µPD78P4038Y
Caution This product contains an I2C bus interface circuit.
When using the I2C bus interface, notify its use to NEC when ordering custom code. NEC can
guarantee the following only when the customer informs NEC of the use of the interface:
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
IEBus and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are registered trademarks or trademarks of Microsoft Corporation in the United States
and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
70
µPD78P4038Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.1.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829
J98. 2
71
µPD78P4038Y
Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated
in this document.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed
The customer must judge the need for license
: µPD78P4038YKK-T
: µPD78P4038YGC-3B9, µPD78P4038YGC-×××-3B9,
µPD78P4038YGC-8BT
µPD78P4038YGK-BE9, µPD78P4038YGK-×××-BE9
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5