NEC UPD78P328DW

DATA SHEET
MOS Integrated Circuit
µPD78P328
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The µ PD78P328 is a product provided by replacing the µ PD75328's internal mask ROM with one-time
PROM or EPROM.
The one-time PROM version is programmable only once and is useful for small-lot production of many
different products and early development and time-to-market of application sets.
The EPROM version is reprogrammable, and suited for the evaluation of systems.
Functions are described in detail in the following user's manual. Be sure to read it before designing.
µPD78328 User's Manual: IEU-1268
FEATURES
•
µPD78328 compatible
• For mass-production, the µPD78P328 can be replaced with the µPD78328 incorporating mask ROM
•
Internal PROM: 16,384 x 8 bits
• Programmable once only (one-time PROM version without window)
• Erasable with ultraviolet rays and electrically programmable (EPROM version with window)
•
•
PROM programming characteristics: µPD27C256A compatible
The µPD78P328 is a QTOPTM microcontroller.
Remark QTOP microcontroller is a general term for microcontrollers which incorporates one-time PROM, and
are totally supported by NEC's programming service (from programming to marking, screening, and
verification).
ORDERING INFORMATION
Part Number
µPD78P328CW
Package
Internal ROM
64-pin plastic shrink DIP (750 mils)
One-time PROM
µPD78P328GF-3BE
64-pin plastic QFP (14 x 20 mm)
One-time PROM
µPD78P328DW
64-pin ceramic shrink DIP (750 mils) (with window)
EPROM
Functions common to the one-time PROM and EPROM versions are referred to as PROM functions throughout this document.
The information in this document is subject to change without notice.
Document No. U10209EJ4V0DS00 (4th edition)
(Previous No. IC-2486)
Date Published October 1995 P
Printed in Japan
The mark
* shows revised points.
 NEC Corporation 1990
µPD78P328
PIN CONFIGURATIONS
(1) Normal operating mode
• 64-pin plastic shrink DIP (750 mils)
µPD78P328CW
• 64-pin ceramic shrink DIP (750 mils) (with window)
µPD78P328DW
P20/NM1
1
64
VDD
P21/INTP0
2
63
AVDD
P22/INTP1
3
62
AVREF
P30/TxD
4
61
P77/ANI7
P31/RxD
5
60
P76/ANI6
P32/SO/SB0
6
59
P75/ANI5
P33/SI/SB1
7
58
P74/ANI4
P34/SCK
8
57
P73/ANI3
P80/TO0
9
56
P72/ANI2
P81/TO1
10
55
P71/ANI1
P82/TO2
P83/TO3
11
12
54
53
P70/ANI0
AVSS
P84/TO4
13
52
VDD
P85/TO5
14
51
P57/A15
P86/TO6/INTP2
15
50
P56/A14
P87/TO7/PWM
VSS
16
17
49
48
P55/A13
P54/A12
X1
18
47
P53/A11
X2
19
46
P52/A10
RESET
20
45
P51/A9
P00/RTP0
21
44
P50/A8
22
43
P47/AD7
P02/RTP2
23
42
P46/AD6
P03/RTP3
P04/RTP4
P05/RTP5
P06/RTP6
24
25
26
27
41
40
39
P45/AD5
P44/AD4
P43/AD3
38
P42/AD2
P07/RTP7
28
37
P41/AD1
EA
29
36
P40/AD0
P93/TMD
P92/TAS
30
31
35
34
ASTB
P90/RD
VSS
32
33
P91/WR
P01/RTP1
Remark These pins are compatible with the µPD78328CW pins.
2
µPD78P328
• 64-pin plastic QFP (14 x 20 mm)
AVREF
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P22/INTP/TI
P21/INTP0
P20/NMI
VDD
AVDD
6362 61 60 59 58 57 56 55 54 53 52
51
50
49
48
47
46
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
AVSS
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
39
38
37
36
16
35
17
34
18
19
33
20 21 22 23 24 25 26 27 28 29 30 31 32
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P40/AD0
P41/AD1
P42/AD2
44
43
42
41
40
P90/RD
ASTB
VDD
P57/A15
P07/RTP7
EA
P93/TMD
P92/TAS
VSS
P91/WR
45
P05/RTP5
P04/RTP4
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P06/RTP6
P33/SI/SB1
P34/SCK
P80/TO0
P81/TO1
P82/TO2
P83TO3
P84/TO4
P85/TO5
P86/TO6/INTP2
P87/TO7/PWM
VSS
X1
X2
RESET
P00/RTP0
P01/RTP1
P02/RTP2
P03/RTP3
P31/RxD
P30/RxD
P32/SO/SB0
µPD78P328GF-3BE
Remark These pins are compatible with the µPD78328GF pins.
3
µPD78P328
P00-P07
: Port 0
SI
: Serial Input
P20-P22
: Port 2
SO
: Serial Output
P30-P34
: Port 3
SB0-SB1
: Serial Bus0-1
P40-P47
: Port 4
RD
: Read Strobe
P50-P57
: Port 5
WR
: Write Strobe
P70-P77
: Port 7
ASTB
: Address Strobe
P80-P87
: Port 8
EA
: External Access
P90-P93
: Port 9
RESET
: Reset
A8-A15
: Address8-15
SCK
: Serial Clock
AD0-AD7
: Address0-7/Data0-7
TAS
: Turbo Access Strobe
ANI0-ANI7
: Analog Input0-7
TMD
: Turbo Mode
TO0-TO7
: Timer Output0-7
X1, X2
: Crystal1, 2
NMI
: Nonmaskable Interrupt
AVDD
: Analog VDD
PWM
: Pulse Wide Modulation Output
AVREF
: Analog Reference Voltage
INTP0-INTP2
: Interrupt From Peripherals0-2
AVSS
: Analog VSS
RTP0-RTP7
: Real-Time Port0-7
VDD
: Power Supply
TxD
: Transmit Data
VSS
: Ground
RxD
: Receive Data
4
µPD78P328
(2) PROM programming mode (RESET = H, AVDD = L)
• 64-pin plastic shrink DIP (750 mils)
µPD78P328CW
• 64-pin ceramic shrink DIP (750 mils) (with window)
µPD78P328DW
1
64
VDD
2
63
AVDD
3
62
4
61
5
60
OE
6
59
CE
7
58
(L)
8
57
A8
9
56
A10
10
55
A11
A12
11
12
54
53
A13
13
52
A14
14
51
15
50
VSS
16
17
49
48
(G)
18
47
A9
(G)
(L)
(L)
(G)
VDD
(L)
(Open)
19
46
RESET
20
45
A0
21
44
A1
22
43
D7
A2
23
42
D6
A3
A4
A5
A6
24
25
26
27
41
40
39
D5
D4
D3
38
D2
A7
28
37
D1
VPP
29
36
D0
30
31
35
34
(Open)
32
33
(L)
VSS
(L)
Caution The recommended connection of the unused pins in the PROM programming mode are indicated
in parentheses.
L
:
Connect each pin to VSS via a resistor.
G
:
Connect the pin to VSS.
Open :
Leave the pin unconnected.
5
µPD78P328
• 64-pin plastic QFP (14 x 20 mm)
(G)
A9
(G)
VDD
AVDD
(G)
VDD
(L)
D7
D6
D5
D4
D3
D0
D1
D2
(Open)
(L)
VSS
A5
A4
(L)
VSS
(G)
(Open)
RESET
A0
A1
A2
A3
A7
VPP
(L)
64 63 62 61 60 59 58 57 56 55 54 53 52
1
51
2
50
49
3
4
48
47
5
46
6
7
45
8
44
9
43
10
42
11
41
40
12
13
39
14
38
15
37
36
16
35
17
34
18
19
33
20 21 22 23 24 25 26 27 28 29 30 31 32
A6
CE
(L)
A8
A10
A11
A12
A13
A14
(L)
OE
µPD78P328GF-3BE
Caution The recommended connection of the unused pins in the PROM programming mode are indicated
in parentheses.
L
:
Connect each pin to VSS via a resistor.
G
:
Connect the pin to VSS.
Open :
Leave the pin unconnected.
A0-A14
: Address0-14
AVDD
: Analog VDD
D0-D7
: Data0-7
VDD
: Power Supply
CE
: Chip Enable
VSS
: Ground
OE
: Output Enable
VPP
: Programming Power Supply
RESET
: Reset
6
µPD78P328
BLOCK DIAGRAM
EXU
PROM/RAM
BCU
Main RAM
X1
X2
RESET
(P20) NMI
INTP0-INTP2
(P21, P22, P86)
(P80) TO0
(P81) TO1
(P82) TO2
(P83) TO3
(P84) TO4
(P85) TO5
(P86) TO6
(P87) TO7/PWM
(P22) TI/INTP1
Programmable
Interrupt
Controller
Timer/Counter Unit
(Real-Time
Pulse Unit)
General
Registers
128 x 8
&
Data
Memory
128 x 8
(P33) SI/SB1
PROM
16K x 8
&
Peripheral
RAM
256 X 8
System
Control
&
Bus
Control
&
Prefetch
Control
Micro Sequence
Control
ASTB
RD (P90)
WR (P91)
TAS (P92)
TMD (P93)
A8-A15 (P50-P57)
AD0-AD7 (P40-P47)
A0-A14
D0-D7
CE
OE
Micro ROM
Note
EA/VPP Note
(P34) SCK
(P32) SO/SB0
ALU
P00-P07
(Real-Time Port)
AVREF
Serial Interface
(SBI)
(UART)
A/D Converter
(10-bit)
(P30) TxD
WDT
AVSS
AVDD
INTP0
ANI0-ANI7
(P70-P77)
Ports
/
P90-P93
VSS
/
2
2
P40-P47
P50-P57
P70-P77
P80-P87
(P31) RxD
VDD
P20-P22
P30-P34
Note During PROM programming mode
7
µPD78P328
CONTENTS
1.
PIN FUNCTIONS ... 9
1.1 Normal Operating Mode ... 9
1.2 PROM Programming Mode (RESET = H, AVDD = L) ... 11
1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ... 12
2.
DIFFERENCES BETWEEN µPD78P328 and µPD78328 ... 14
3.
PROM PROGRAMMING ... 15
3.1 Operation Mode ... 15
3.2 PROM Write Procedure ... 16
3.3 PROM Read Procedure ... 18
4.
ERASURE CHARACTERISTICS (EPROM VERSION ONLY) ... 19
5.
WINDOW SEAL (EPROM VERSION ONLY) ... 19
6.
ONE-TIME PROM VERSION SCREENING ... 19
7.
ELECTRICAL SPECIFICATIONS ... 20
8.
PACKAGE DRAWINGS ... 35
9.
RECOMMENDED SOLDERING CONDITIONS ... 37
APPENDIX A.
*
DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT... 38
APPENDIX B. TOOLS ... 40
B.1 Development Tools ... 40
B.2 Evaluation Tools ... 43
B.3 Embedded Software ... 43
8
µPD78P328
1.
PIN FUNCTIONS
1.1 Normal Operating Mode
(1) Port Pins
Pin Name Input/Output
Function
P00-P07
PORT0
Alternate
Function
Input/Output
RTP0-RTP7
4-/8-bit input/output port
Input or output mode can be specified bit-wise.
The port can also operate as a real-time output port.
P20
Input
P21
PORT 2
NMI
3-bit input-only port
INTP0
P22
P30
INTP1/TI
PORT 3
TxD
P31
Input/Output
5-bit input/output port
RxD
P32
Input or output mode can be specified bit-wise.
SO/SB0
P33
SI/SB1
P34
P40-P47
SCK
Input/Output
PORT 4
AD0-AD7
8-bit input/output port
Input or output mode can be specified in 8-bit units.
P50-P57
Input/Output
PORT 5
A8-A15
8-bit input/output port
Input or output mode can be specified bit-wise.
P70-P77
Input
PORT 7
P80
Input/Output
PORT 8
ANI0-ANI7
8-bit input-only port
TO0
P81
8-bit input/output port
TO1
P82
Input or output mode can be specified bit-wise.
TO2
P83
TO3
P84
TO4
P85
TO5
P86
TO6/INTP2
P87
P90
TO7/PWM
Input/Output
PORT 9
RD
P91
4-bit input/output port
WR
P92
Input or output mode can be specified bit-wise.
TAS
P93
TMD
9
µPD78P328
(2) Non-Port Pins (1/2)
Pin Name Input/Output
Function
Alternate
Function
RTP0-RTP7 Output
Real-time output port which outputs a pulse in synchronization with the trigger signal from P00-P07
real-time pulse unit (RPU).
NMI
Input
Edge-detected nonmaskable interrupt request input.
P20
The rising or falling edge can be selected for the valid edge by setting the mode register.
INTP0
Input
INTP1
Edge-detected external interrupt request input.
P21
The valid edge can be specified in the mode register.
P22/T1
INTP2
P86/TO6
TI
Input
External count clock input pin to timer 1 (TM1).
S22/INTP1
RxD
Input
Serial data input pin to asynchronous serial interface (UART).
P30
TxD
Output
Serial data output pin from asynchronous serial interface (UART).
P31
SO
Output
Serial data output pin from clocked serial interface in 3-wire mode.
P32/SB0
SI
Input
Serial data input pin to clocked serial interface in 3-wire mode.
P33/SB1
SB0
Input/Output
Serial data input/output pins to/from clocked serial interface in SBI mode.
SB1
SCK
Input/Output
Serial clock input/output pin to/from clocked serial interface.
P34
AD0-AD7
Input/Output
Multiplexed address/data bus used when external memory is added.
P40-P47
A8-A15
Output
Address bus used when external memory is added.
P50-P57
TO0
Output
Pulse output from real-time pulse unit.
P80
TO1
P81
TO2
P82
TO3
P83
TO4
P84
TO5
P85
TO6
P86/INTP2
TO7
*
P32/SO
P33/SI
P87/PWM
PWM
Output
RD
Output
PWM signal output from real-time pulse unit.
P87/TO7
Strobe signal output for external memory read operation.
P90
WR
Strobe signal output for external memory write operation.
P91
TAS
Control signal output pins to access turbo access manager (µPD71P301). Note
P92
TMD
ASTB
P93
Output
Timing signal output pin to externally latch an address information output to port 4 for
—
external memory access.
EA
Input
For µPD78P328, normally connect the EA pin to VDD. When the EA pin is connected to
VSS, the µPD78P328 enters the ROMless mode and external memory is accessed.
The EA pin level cannot be changed during operation.
Note Turbo access manager (µPD71P301) is available for maintenance purposes only.
10
—
µPD78P328
(2)
Non-Port Pins (2/2)
Pin Name Input/Output
Function
Alternate
Function
ANI0-ANI7
Input
Analog input to A/D converter.
P70-P77
AVREF
Input
A/D converter reference voltage input.
—
AVDD
—
A/D converter analog power supply.
—
AVSS
—
A/D converter GND.
—
RESET
Input
System reset input.
—
X1
Input
Crystal connection pin for system clock generation. To supply external clock,
—
X2
—
input to the X1 and input reverse signal to the X2 pin (X2 pin can be unconnected.)
—
VDD
—
Positive power supply pin.
—
VSS
—
GND pin.
—
1.2 PROM Programming Mode (RESET = H, AVDD = L)
Pin Name Input/Output
Function
AVDD
Input
PROM programming mode setting.
A0-A14
—
Address bus.
D0-D7
—
Data bus.
CE
Input
PROM enable to PROM.
RESET
OE
Input
Read strobe to PROM.
VPP
—
Write power supply.
VDD
Positive power supply.
VSS
GND.
11
µPD78P328
1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
Table 1-1 and Figure 1-1 show the pin input/output circuit schematically.
Table 1-1. Pin Input/Output Circuits and Recommended Connection of Unused Pins
Pin
Input/Output
Recommended connection of unused pins
circuit type
P00P07/RTP0-RTP7
5
P21/NMI
2
Input state: Independently connect to VDD or VSS via a resistor.
Output state: Leave Open.
Connect to VSS.
P21/INTP0
P27/INTP6/TI
P30/TxD
5
P31/RxD
P32/SO/SB0
Input state: Independently connect to VDD or VSS via a resistor.
Output state: Leave Open.
8
P33/SI/SB1
P34/SCK
P40/AD0-P47/AD0-AD7
5
P50/P57/A8-A15
P70-P77/ANI0-ANI7
9
Connect to VSS.
P80-P85/TO0-TO5
5
Input state: Independently connect to VDD or VSS via a resistor.
P86/TO6/INTP2
6
Output state: Leave Open.
P87/TO7/PWM
5
P90/RD
5
P91/WR
P92/TAS
P93/TMD
ASTB
12
4
Leave Open.
EA
1
—
RESET
2
—
AVREF, AVSS
—
Connect to VSS.
VDD
—
Connect to VDD.
µPD78P328
Figure 1-1. Pin Input/Output Circuits
TYPE 1
TYPE 6
VDD
VDD
data
IN
P-ch
P-ch IN/OUT
output
disable
data
data input enable
N-ch
N-ch
control signal
control input
enable
TYPE 8
TYPE 2
VDD
IN
data
P-ch
output
disable
N-ch
IN/OUT
Schmitt-triggerred input with hysteresis characteristics
TYPE 4
TYPE 9
VDD
IN
data
P-ch
output
disable
OUT
P-ch
N-ch
Comparator
+
–
VREF
(Threshold voltage)
N-ch
Push-pull output that can be placed in high impedance
(both P-ch and N-ch off).
input
enable
TYPE 5
VDD
data
P-ch
output
disable
N-ch
IN/OUT
input
disable
13
µPD78P328
2.
DIFFERENCES BETWEEN µPD78P328 and µPD78328
The µPD78P328 is a product provided by replacing the µPD78328's on-chip mask ROM with one-time PROM
or EPROM. Thus, the µPD78P328 and µPD78328 are the same in function except for the ROM specifications such
as write or verify. Table 2-1 lists the differences between these two products.
This Data Sheet describes the PROM specification function. Refer to the µPD78328 documents for details of
other functions.
Table 2-1. Differences between µPD78P328 and µPD78328
Item
µPD78P328
Internal program memory
One-time PROM
EPROM
Mask ROM
(electrical program)
(programmable only once)
(reprogrammable)
(nonprogrammable)
• 64-pin ceramic shrink DIP
• 64-pin plastic shrink DIP
PROM programming pin
Contained
Package
• 64-pin plastic shrink DIP
µPD78328
Not contained
• 64-pin plastic QFP
*
*
*
Electrical specifications
Others
(with window)
• 64-pin plastic QFP
Current dissipations are different.
Noise immunity and noise radiation differ because circuit complexity and mask layout are
different.
Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To
replace the PROM version with the mask ROM version when shifting from experimental production
to mass production, evaluate your system by using the CS version (not ES version) of the mask
ROM version.
14
µPD78P328
3.
PROM PROGRAMMING
The PROM incorporated in the µPD78P328 is a 16,384 x 8-bit electrically writable PROM. For programming,
set the PROM programming mode by using the RESET and AVDD pins.
The programming characteristics are compatible with the µPD27C256A programming characteristics.
Table 3-1. Pin Function in Programming Mode
Function
Normal Operating Mode
Programming Mode
Address input
P00-P07, P80, P20, P81-P85
A0-A14
Data input
P40-P47
D0-D7
Chip enable/program pulse
P33
CE
Output enable
P32
OE
Program voltage
EA
VPP
Mode control
RESET, AVDD
3.1 Operation Mode
To set the program write/verify mode, set RESET = H and AVDD = L. For the mode, the operation mode can be
selected by setting the CE and OE pins, as listed in Table 3-2.
To read the PROM contents, set the read mode.
Connect the unused pins exactly as indicated on Pin Configuration.
Table 3-2. PROM Programming Operation Mode
Mode
RESET
AVDD
Program write
H
L
CE
OE
VPP
VDD
+12.5 V
+6 V
D0-D7
L
H
Program verify
H
L
Data output
Program inhibit
H
H
High impedance
Read
L
L
+5 V
+5 V
Data input
Data output
Output disable
L
H
High impedance
Standby
H
L/H
High impedance
Caution When VPP is set to +12.5 V and VDD is set to +6V, setting both CE and OE to L is inhibited.
15
µPD78P328
3.2 PROM Write Procedure
The write procedure into PROM is as follows: (See also Figure 3-2).
(1) Fix RESET = H and AVDD = L. Connect other unused pins exactly as indicated in section "Pin Configuration."
(2) Supply +6 V to the VDD and +12.5 V to the VPP pin.
(3) Supply an initial address.
(4) Supply write data.
(5) Supply 1 ms program pulse (active low) to the CE pin.
(6) Execute the verify mode. Check whether or not the write data is written normally.
• When it is written normally: Proceed to step (8).
• When it is not written normally: Repeat steps (4) to (6).
If the data is not written normally after 25 repetitions of the steps, proceed to step (7).
(7) Assume the device to be defective. Stop write operation.
(8) Supply write data and X (number of steps (4) to (6) repetitions) x 3 ms program pulses (additional write).
(9) Increment the address.
(10) Repeat steps (4) to (9) to the last address.
Figure 3-1 shows the PROM Write/Verify Timing Steps (2) to (8) above.
Figure 3-1. PROM Write/Verify Timing
X-time repetition
Write
Address input
A0-A14
Hi-Z
D0-D7
Additional
data write
Verify
Data input
Data
output
Hi-Z
Hi-Z
Data input
+12.5 V
VPP
VDD
+6 V
VDD
VDD
CE (input)
OE (input)
16
3 X ms
µPD78P328
Figure 3-2. Write Procedure Flowchart
(1)
WRITE START
(2)
Supply power
(3)
Supply initial address
(4)
Supply write data
(5)
Supply program pulse
Write NG
(after 24
repetition or less)
(6)
Verify mode
Write NG
(at the 25th repetition)
Write OK
(8)
Make additional write
(3X ms pulses)
(9)
Increment address
X: Number of write
repetitions
(10)
< end address
End address
> end address
WRITE END
(7)
Defective device
17
µPD78P328
3.3 PROM Read Procedure
The read procedure of the PROM contents into the external data bus (D0-D7) is as follows.
(1) Fix RESET = H and AVDD = L. Connect other unused pins exactly as indicated on Pin Configuration.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input the address of the data to be read to the A0-A14 pins.
(4) Execute the read mode.
(5) The data is output to the D0-D7 pins.
Figure 3-3 shows the PROM read timing steps (2) to (5) above.
Figure 3-3. PROM Read Timing
A0-A14
Address input
CE (input)
OE (input)
D0-D7
18
Hi-Z
Data output
Hi-Z
µPD78P328
4.
ERASURE CHARACTERISTICS (EPROM VERSION ONLY)
The data written into the µPD78P328DW program memory can be erased (FFH) and new data can be rewritten
into the memory.
To erase data, apply light with a wave length shorter than 400 nm to the window. Normally, apply ultraviolet rays
having the 254-nm wave length. The radiation amount required to completely erase data is as follows:
• Ultraviolet strength x erasure time: 15 W•s/cm2 or more
• Erasure time:
15 to 20 minutes when a 12,000 µW/cm2 ultraviolet lamp is used. However, the time may be
prolonged due to ultraviolet lamp performance deterioration, dirty window, etc.
For erasure, place an ultraviolet lamp at a position within 2.5 cm from the window. If a filter is attached to the
ultraviolet lamp, remove the filter before applying ultraviolet rays.
5.
WINDOW SEAL (EPROM VERSION ONLY)
If the µPD78P328DW window is exposed to sunlight or fluorescent lamp light for hours, EPROM data may be
erased and the internal circuit may operate erroneously. To prevent such accidents from occurring, put a protective
seal on the window.
A protective seal whose quality is guaranteed by NEC is attached to every EPROM version with window at
shipment.
6.
ONE-TIME PROM VERSION SCREENING
The one-time PROM versions (µPD78P328CW, 78P328GF-3BE) cannot be completely tested by NEC for
shipment because of their structure. For screening, it is recommended to verify PROM after storing the necessary
data under the following conditions:
NEC provides chargeable services ranging from one-time PROM writing to marking, screening, and verification
for QTOP microcontroller products. For details, contact an NEC sales representative.
Storage temperature
Storage time
125˚C
24 hours
19
µPD78P328
7.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
Ratings
Unit
Power supply voltage
VDD
Test Conditions
–0.5 to +7.0
V
VDD
–0.5 to VDD +0.5
V
VPP
–0.5 to +13.5
V
AVSS
Input voltage
–0.5 to +0.5
V
VI1
Note 1
–0.5 to VDD +0.5
V
VI2
P20/NIM (A9) PIN
–0.5 to +13.5
V
–0.5 to VDD +0.5
V
All output pins
4.0
mA
Total for all pins
90
mA
All output pins
–1.0
mA
Total for all pins
–20
mA
Note 2
AVDD > VDD
-0.5 to VDD +0.5
V
VDD ≥ AVDD
-0.5 to AVDD +0.5
V
AVDD > VDD
-0.5 to VDD +0.3
V
VDD ≥ AVDD
-0.5 to AVDD +0.3
V
Output voltage
VO
Output current, low
IOL
Output current, high
IOH
Analog input voltage
VIAN
A/D converter reference
AVREF
input voltage
Operating ambient temperature
TA
–10 to +70
°C
Storage temperature
Tstg
–65 to +150
°C
Notes 1. Pins except for P20/NMI (A9), P70/ANI0-P77/ANI7
2. P70/ANI0-P77/ANI7
*
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter,
even momentarily. In other words, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used under
conditions which ensure that the absolute maximum ratings are not exceeded.
Recommended Operation Conditions
Oscillation frequency
TA
VDD
8 MHz ≤ fXX ≤ 16 MHz
–10 to +70 ˚C
+5.0 V ±5%
Capacitance (TA = 25 °C, VSS = VDD = 0 V)
20
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CI
f = 1 MHz
10
pF
Output capacitance
CO
Unmeasured pins returned to 0 V
20
pF
I/O capacitance
CIO
20
pF
µPD78P328
Oscillator Characteristics (TA = –10 to +70 °C, VDD = +5 V±5%, VSS = 0 V)
Resonator
Recommended Circuit
Parameter
MIN.
MAX.
Unit
Oscillation frequency (fXX)
8
16
MHz
X1 input frequency (fX)
8
16
MHz
X2
Open
X1 input rise, fall time (fXR, tXF)
0
20
ns
HCMOS
Inverter
X1 input high, low level width
25
80
ns
Ceramic or crystal
resonator
X2
VSS
X1
C2
C1
External clock
X1
X2
HCMOS
Inverter
or
X1
(tWXH, tWXL)
Caution When using the system clock oscillator, wire the portion enclosed in dotted line in the figure as
follows to avoid adverse influences on the wiring capacitance:
• Keep the wiring length as short as possible.
• Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of
lines through which a high fluctuating current flows.
• Always keep the ground point of the capacitor of the oscillator circuit at the same potential as
VSS. Do not connect the power source pattern through which a high current flows.
• Do not extract signals from the oscillation circuit.
Recommended Oscillator Constants
Ceramic resonator
Manufacturer Name
MURATA
Part Number
Frequency
Recommended
[MHz]
Constants
C1 [pF]
C2 [pF]
30
30
CSA8.00MT
8.0
CSA12.0MT
12.0
CSA16.00MX040
16.0
15
15
CST8.00MTW
8.0
Internal
Internal
CST12.00MTW
12.0
CST16.00MXW0C3
16.0
21
µPD78P328
DC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
Input voltage, low
VIL
Input voltage, high
VIH1
Note 1
2.2
VIH2
Note 2
0.8VDD
Output voltage, low
VOL
IOL = 2.0 mA
Output voltage, high
VOH
IOH = –400 µA
Input leakage current
ILI
0 V ≤ V I ≤ VDD
±10
µA
Output leakage current
ILO
0 V ≤ V O ≤ VDD
±10
µA
VDD power supply current
IDD1
Operation mode
45
75
mA
IDD2
HALT mode
25
45
mA
Data retention voltage
VDDDR
STOP mode
Data retention current
IDDDR
STOP mode
0
MAX.
Unit
0.8
V
V
0.45
VDD–1.0
V
V
2.5
V
VDDDR = 2.5 V
3
15
µA
VDDDR = 5.0 V ±5%
10
50
µA
Notes 1. Pins except for RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1/TI, P86/INTP2/TO0, P32/SO/SB0,
P33/SI/SB1, or P34/SCK.
2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1/TI, P86/INTP2/TO0, P32/SO/SB0, P33/SI/SB1, or
P34/SCK pins.
22
µPD78P328
AC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)
Discontinuous read/write operation (when general-purpose memory is connected)
Parameter
Symbol
System clock cycle time
Test Conditions
MIN.
MAX.
Unit
tCYK
125
250
ns
Address setup time (to ASTB ↓)
tSAST
22
ns
Address hold time (from ASTB ↓)
tHSTA
32
ns
Address → RD ↓ delay time
tDAR
85
ns
RD ↓ → address float time
tFRA
8
ns
Address → data input time
tDAID
222
ns
RD ↓ → data input time
tDRID
112
ns
ASTB ↓ → RD ↓ delay time
tDSTR
42
ns
Data hold time (from RD ↑)
tHRID
0
ns
RD ↑ → address active time
tDRA
37
ns
RD low-level width
tWRL
147
ns
ASTB high-level width
tWSTH
37
ns
Address → WR ↓ delay time
tDAW
85
ns
ASTB ↓ → data output time
tDSTOD
102
ns
WR ↓ → data output time
tDWOD
40
ns
ASTB ↓ → WR ↓ delay time
tDSTW
42
ns
Data setup time (to WR ↑)
tSODW
137
ns
Data hold time (from WR ↑)
tHWOD
32
ns
WR ↑ → ASTB ↓ delay time
tDWST
42
ns
WR low-level width
tWWL
147
ns
23
µPD78P328
tCYK-Dependent Bus Timings
Parameter
Calculation expression
MIN./MAX.
Unit
tSAST
0.5T – 40
MIN.
ns
tHSTA
0.5T – 30
MIN.
ns
tDAR
T – 40
MIN.
ns
tDAID
(2.5 + n) T – 90
MAX.
ns
tDRID
(1.5 + n) T – 75
MAX.
ns
tDSTR
0.5T – 20
MIN.
ns
tDRA
0.5T – 25
MIN.
ns
tWRL
(1.5 + n) T – 40
MIN.
ns
tWSTH
0.5T – 25
MIN.
ns
tDAW
T – 40
MIN.
ns
tDSTOD
0.5T + 40
MAX.
ns
tDSTW
0.5T – 20
MIN.
ns
tSODW
1.5T – 50
MIN.
ns
tHWOD
0.5T – 30
MIN.
ns
tDWST
0.5T – 20
MIN.
ns
tWWL
(1.5 + n) T – 40
MIN.
ns
Remarks 1. T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two).
2. n is the number of wait cycles defined by user software.
3. Only parameters listed in the table are dependent on tCYK.
24
µPD78P328
Serial Operation (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
Serial clock cycle time
tCYSK
Input
External clock
1
µs
Output
Internal divide by 8
8T
tCYK
Internal divide by 32
32T
tCYK
Input
External clock
420
ns
Output
Internal divide by 8
4T–80
ns
Internal divide by 32
16T–100
ns
Input
External clock
420
ns
Output
Internal divide by 8
4T–80
ns
Internal divide by 32
16T–100
ns
Serial clock high-level width
Serial clock high-level width
tWSKL
tWSKH
MAX.
Unit
SI setup time (to SCK ↑)
tSRXSK
80
ns
SI hold time (from SCK ↑)
tHSKRX
80
ns
SO/SB0, SI/SB1
tDSBSK1
output delay time (from SCK ↓)
CMOS push-pull output
0
210
ns
0
600
ns
(3-wire serial I/O mode)
tDSBSK2
Open drain output
(SBI mode), RL = 1 kΩ
SB0, SB1 high hold time (from SCK ↑) tHSBSK
SBI mode
4T
tCYK
SB0, SB1 low setup time (from SCK ↓) tSSBSK
4T
tCYK
SB0, SB1 low-level width
tWSBL
4T–20
ns
SB0, SB1 high-level width
tWBSH
4T–20
ns
Remark T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two.)
25
µPD78P328
Other operations (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = 0 V)
Parameter
Symbol
NMI high-, low-level widths
tWNIH,
Test Conditions
MIN.
MAX.
Unit
5
µs
8T
tCYK
8T
tCYK
8T
tCYK
5
µs
8T
tCYK
tWNIL
INTP0 high-, low-level widths
tWIOH,
tWIOL
INTP1 high-, low-level widths
tWI1H,
tWI1L
INTP2 high-, low-level widths
tWI2H,
tWI2L
RESET high-, low-level widths
tWRSH,
tWRSL
TI high-, low-level widths
Remark
tWTIH,
TM1
tWTIL
In the event counter mode
T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two.)
External clock timing (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = 0 V)
Parameter
Symbol
X1 input high-, low-level widths
tWXH ,
Test Conditions
MIN.
MAX.
Unit
25
80
ns
0
20
ns
62
125
ns
tWXL
X1 input rise, fall times
tXR,
tXF
TI input cycle time
26
tCYK
µPD78P328
A/D Converter (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD)
Parameter
Symbol
Test Conditions
MIN.
Resolution
Total error
TYP.
MAX.
10
Note1
bit
4.5 V ≤ AVREF ≤ AVDD
±0.4
%FSR
3.4 V ≤ AVREF ≤ AVDD
±0.7
%FSR
±1/2
LSB
Quantification error
Conversion time
Sampling time
Zero scale error
Fullscale error
Nonlinear error
tCONV
144
tCYK
tSAMP
24
tCYK
Note1
Note1
Note1
Analog input voltage
Note2
Unit
4.5 V ≤ AVREF ≤ AVDD
+1.5
±2.5
LSB
3.4 V ≤ AVREF ≤ AVDD
+1.5
±4.5
LSB
4.5 V ≤ AVREF ≤ AVDD
+1.5
±2.5
LSB
3.4 V ≤ AVREF ≤ AVDD
+1.5
±4.5
LSB
4.5 V ≤ AVREF ≤ AVDD
+1.5
±2.5
LSB
3.4 V ≤ AVREF ≤ AVDD
+1.5
±4.5
LSB
V IAN
–0.3
AVDD
V
Basic voltage
AVREF
3.4
AVDD
V
AVREF current
AI REF
1.0
3.0
mA
AVDD supply current
AIDD
2.0
6.0
mA
A/D converter data
AI DDDR
AVDDDR = 2.5 V
2.0
10
µA
AVDDDR = 5 V±5%
10
50
µA
MIN.
MAX.
Unit
5.5
V
STOP mode
retention current
*
Notes 1. Quantization error is excluded.
2. When –0.3 V ≤ VIAN ≤ 0 V, conversion result is 000H.
When 0 V < VIAN < AVREF, conversion is executed by 10-bit resolution.
When AVREF ≤ V IAN ≤ AVDD, conversion result is 3 FFH.
Standby flag retention characteristics (TA = –10˚C to 70˚C)
Parameter
Symbol
Test Conditions
Standby flag retention power supply voltage
VDDDR
2.5
V DD rising, falling time
tRVD,
200
ns
tFVD
AC Timing Test Points
VDD – 1 V
0.8 VDD or 2.2 V
0.8 V
Test
Points
0.8 VDD or 2.2 V
0.8 V
0.45 V
27
µPD78P328
Timing Wave Forms
Discontinuous Read Operation
tCYK
(CLK)
P50-P57
(output)
High-order address
tDAID
tSAST
P40-P47
(input/output)
High-order address
Low-order address
(output)
Hi-Z
Hi-Z
Data (input)
tWSTH
Low-order address
(output)
Hi-Z
tHRID
P50-P57
(output)
tHSTA
tFRA
RD (output)
tDSTR
tDRA
tDRID
tDAR
tWRA
Discontinuous Write Operation
(CLK)
P50-P57
(output)
High-order address
High-order address
tSAST
P40-P47
(input/output)
Low-order address
(output)
Data (output)
tHWOD
tWSTH
ASTB
(output)
tHSTA
tDSTA
tDSTOD
WR (output)
tDSTW
tDWOD
tSODW
tDAW
tWWL
28
Low-order address
(output)
µPD78P328
Serial Operation
Three-Wire Serial I/O Mode:
tWSKL
tWSKH
SCK
tSRXSK tHSKRX
tCYSK
SI
Input data
tDSBSKI
Output data
SO
SBI Mode
Bus Release Signal Transfer
SCK
tHSBSK
tWSBL
tWSBH
tSSBSK
SB0
Command Signal Transfer
tWSKL
tWSKH
SCK
tHSBSK
SB0
tSSBSK
tCYSK
tDSBSK2
tSSSK
tHSSK
I/O data
29
µPD78P328
Interrupt Input Timing
tWNIL
tWNIH
NMI
0.8 VDD
0.8 V
tWIOH
tWIOL
tWI1H
tWI1L
tWI2H
tWI2L
INTP0
INTP1
INTP2
Reset Input Timing
tWRSL
tWRSH
RESET
0.8 VDD
0.8 V
30
µPD78P328
External Clock Timing
tWXH
X1
tXR
tXF
tWXL
tCYX
Standby Flag Retention Timing
VDD
VDDDR
tFVD
tRVD
TI Pin Input Timing
tWTIH
tWTIL
TI
31
µPD78P328
DC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V)
Parameter
Symbol Symbol Test conditions
MIN.
TYP.
MAX.
Unit
VDDP
V
Note1
Input voltage, high
VIH
VIH
2.2
+0.3
Input voltage, low
VIL
VIL
Input leakage current
ILIP
ILI
0 ≤ V I ≤ VDDP
–0.3
Output voltage, high
VOH
VOH
IOH = –400 µA
Output voltage, low
VOL
VOL
IOL = 2.0 mA
0.45
V
Input current
IA9
—
A9 (P20/NMI) pin
±10
µA
Output leakage current
ILO
—
0 ≤ VO ≤ VDDP, OE = VIN
10
µA
PROG pin high voltage input
IIP
—
±10
µA
VDDP
VDD
Note 2
0.8
V
±10
µA
2.4
V
current
VDDP power supply voltage
VPP power supply voltage
VDDP power supply current
VPP
IDD
VPP
IDD
Program memory write mode
5.75
6.0
6.25
V
Program memory read mode
4.5
5.0
5.5
V
Program memory write mode
12.2
12.5
12.8
Program memory read mode
VPP = VDDP
V
V
Program memory write mode
10
30
mA
Program memory read mode
10
30
mA
10
30
mA
1
100
µA
CE = VIL, OE = VIN
VPP power supply current
IPP
IPP
Program memory write mode
CE = VIL, OE = VIN
Program memory read mode
Notes 1. Corresponding µPD27C256A symbols.
2. VDDP is VDD pin during the programming mode.
32
µPD78P328
AC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V)
Parameter
Symbol Symbol Test conditions
MIN.
TYP.
MAX.
Unit
Note
tSAC
tAS
2
µs
Data → OE ↓ delay time
tDDOO
tOES
2
µs
Input data setup time (to CE ↓)
tSIDC
tDS
2
µs
Address hold time (from CE ↑)
tHCA
tAH
2
µs
Input data hold time (from CE ↑)
tHCID
tDH
2
µs
Output data hold time (from OE ↑)
tHOOD
tDF
0
V PP setup time (to CE ↓)
tSVPC
tVPS
2
V DDP setup time (to CE ↓)
tSVDC
tVDS
2
Initial program pulse width
tWL1
tPW
0.95
Additional program pulse width
tWL2
tOPW
Address → data output time
tDAOD
tACC
OE ↓ → data output time
tDOOD
tOE
Data hold time (from OE ↑)
tHCOD
tDF
Data hold time (from address)
tHAOD
tOH
Address setup time (to CE ↓)
Note
2.85
OE = VIL
0
OE = VIL
0
130
ns
µs
µs
1.0
1.05
ms
78.75
ms
2
µs
1
µs
130
ns
ns
Corresponding µPD27C256A symbols.
33
µPD78P328
PROM Write Mode Timing
A12-A0
Effective address
tSAC
D7-D0
tHOOD
Data input
tSIDC
Data output
tHCA
Data onput
tHCID
tSIDC
tHCID
VPP
VPP
VDDP
VDDP
tSVPC
VDDP +1
VDDP
tSVDC
VIH
CE
VIL
tWL1
tDDOO
tWL2
tDOOD
VIH
OE
VIL
Cautions 1. Apply VDDP before VPP and remove it after VPP.
2. VPP must not exceed +13 V, including the overshoot.
PROM Read Mode Timing
A12-A0
Effective address
OE
tDAOD
D7-D0
34
Hi-Z
tDOOD
tHCOD
tHAOD
Data output
Hi-Z
µPD78P328
8.
PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
H
G
J
I
L
F
D
N
M
NOTE
B
C
M
R
ITEM
MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
58.68 MAX.
2.311 MAX.
B
1.78 MAX.
0.070 MAX.
2) Item "K" to center of leads when formed parallel.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0
0.669
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
P64C-70-750A,C-1
35
µPD78P328
36
µPD78P328
64 PIN PLASTIC QFP (14×20)
A
B
detail of lead end
33
32
51
52
C
D
S
R
Q
64
1
20
19
F
G
H
I
M
J
K
M
P
N
L
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6±0.4
0.929±0.016
B
20.0±0.2
0.795 +0.008
–0.009
C
14.0±0.2
0.551+0.009
–0.008
D
17.6±0.4
0.693±0.016
F
1.0
0.039
G
1.0
0.039
H
0.40±0.10
0.016 +0.004
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P)
K
1.8±0.2
0.071 +0.008
–0.009
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
P
Q
R
S
0.10
0.004
2.7
0.106
0.1±0.1
0.004±0.004
5°±5°
5°±5°
3.0 MAX.
0.119 MAX.
P64GF-100-3B8,3BE,3BR-2
37
µPD78P328
9.
RECOMMENDED SOLDERING CONDITIONS
*
It is recommended that this device be soldered under the following conditions.
For details on the recommended soldering conditions, refer to information document "Semiconductor Devices
Mounting Technology Manual" (IEI-1207).
For soldering methods and conditions other than those recommended, please contact your NEC sales
representative.
Table 9-1. Soldering Conditions for Surface Mount Devices
µPD78P328GF-3BE: 64-pin plastic QFP (14 x 20 mm)
Soldering Method
Soldering Conditions
Recommended Soldering
Code
Infrared reflow
Package peak temperature: 235˚C,
Time: 30 seconds max. (210˚C min.),
Number of times: 2 max, Maximum number of days: 7 daysNote
(thereafter, 20 hours of prebaking is required at 125˚C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first
reflow before starting the second reflow.
(2) Do not perform flux cleaning with water after the first reflow.
IR35-207-2
VPS
Package peak temperature: 215˚C,
Time: 40 seconds max. (200˚C min.),
Number of times: 2 max, Maximum number of days: 7 daysNote
(thereafter, 20 hours of prebaking is required at 125˚C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first
reflow before starting the second reflow.
(2) Do not perform flux cleaning with water after the first reflow.
VP15-207-2
Wave soldering
Soldering bath temperature: 260˚C max., Time: 10 seconds max.,
Number of times: 1,
Preheating temperature: 120°C max. (package surface temperature),
Maximum number of days: 7 daysNote (thereafter, 20 hours of
prebaking is required at 125˚C).
WS60-207-1
Partial heating
Pin temperature: 300˚C max.,
Time: 3 seconds max. (per pin row)
—
Note Number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max.
Caution
Do not use different soldering methods together (except the partial heating method).
Table 9-2. Soldering Conditions for Through-hole Devices
µPD78P328CW: 64-pin Plastic Shrink DIP (750 mils)
µPD78P328DW: 64-pin Ceramic Shrink DIP (750 mils) (with window)
Soldering Method
Soldering Conditions
Wave soldering (pin only)
Soldering bath temperature: 260˚C max., Time: 10 seconds max.
Partial heating
Pin temperature: 300˚C max., Time: 3 seconds max. (per pin)
Caution Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact
with the package.
38
µPD78P328
APPENDIX A. DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT
The emulation probe (EP-78327GF-R) for the µPD78P328GF-3BE is connected with the target system in
combination with the conversion socket (EV-9200G-64).
The drawings of the socket and recommended footprint are shown below.
Figure A-1. Drawing of Conversion Socket (EV-9200G-64)
(for reference only)
A
N
G
O
P
L
M
U
K
C
E
T
S
B
R
F
D
*
EV-9200G-64
1
Q
No.1 pin index
H
I
J
EV-9200G-64-G0
ITEM
MILLIMETERS
INCHES
A
25.0
0.984
B
20.30
0.799
C
4.0
0.157
D
14.45
0.569
E
19.0
0.748
F
4-C 2.8
4-C 0.11
G
0.8
0.031
H
11.0
0.433
I
22.0
0.866
J
24.7
0.972
K
5.0
0.197
L
16.2
0.638
M
18.9
0.744
O
8.0
0.315
N
7.8
0.307
P
2.5
0.098
Q
2.0
0.079
R
1.35
0.053
S
0.35 ± 0.1
0.014+0.004
–0.005
T
φ 2.3
φ 0.091
U
φ 1.5
φ 0.059
39
µPD78P328
Figure A-2. Recommended Footprint for EV-9200G-64
(for reference only)
G
J
H
I
D
E
F
L
K
M
C
B
A
EV-9200G-64-P0
ITEM
MILLIMETERS
A
25.7
B
21.0
0.827
C
1.0±0.02 × 18=18.0±0.05
D
+0.003
1.0±0.02 × 12=12.0±0.05 0.039+0.002
–0.001 × 0.472=0.472 –0.002
0.039+0.002
–0.001 ×
0.709=0.709+0.002
–0.003
E
15.2
0.598
F
19.9
0.783
G
11.00 ± 0.08
0.433+0.004
–0.003
H
5.50 ± 0.03
0.217+0.001
–0.002
I
5.00 ± 0.08
0.197+0.003
–0.004
J
2.50 ± 0.03
0.098+0.002
–0.001
K
0.6 ± 0.02
0.024+0.001
–0.002
L
φ 2.36 ± 0.03
φ 0.093+0.001
–0.002
M
φ 1.57 ± 0.03
φ 0.062+0.001
–0.002
Caution
40
INCHES
1.012
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (IEI-1207).
µPD78P328
*
APPENDIX B. TOOLS
B.1 Development Tools
The following development tools are readily available to support development of systems using the µPD78P328:
Language Processor
78K/III Series
Relocatable assembler common to the 78K/III series. Since it contains the macro function, the
relocatable assembler
development efficiency can be improved. A structured assembler which enables you to explicity
(RA78K/III)
describe program control structure is also attached and program productivity and maintenance
can be improved.
Host machine
Ordering code
OS
PC-9800 series
IBM PC/AT
TM
TM
MS-DOS
PC DOS
TM
Supply medium
(product name)
3.5-inch 2HD
µS5A13RA78K3
5-inch 2HD
µS5A10RA78K3
3.5-inch 2HC
µS7B13RA78K3
5-inch 2HC
µS7B10RA78K3
HP9000 series 700TM
HP-UXTM
DAT
µS3P16RA78K3
SPARCstationTM
SunOSTM
Cartridge tape
µS3K15RA78K3
(QIC-24)
µS3R15RA78K3
and compatible machine
NEWS
TM
NEWS-OS
TM
78K/III Series
C compiler common to the 78K/III series. This is a program to convert a program written in C
C compiler
language into an object code executable with a microcontroller. When using the compiler,
(CC78K/III)
78K/III series relocatable assembler(RA78K/III) is necessary.
Host machine
PC-9800 series
IBM PC/AT
TM
Ordering code
OS
Supply medium
(product name)
MS-DOS
3.5-inch 2HD
µS5A13CC78K3
5-inch 2HD
µS5A10CC78K3
3.5-inch 2HC
µS7B13CC78K3
PC DOS
5-inch 2HC
µS7B10CC78K3
HP9000 series 700
HP-UX
DAT
µS3P16CC78K3
SPARCstation
SunOS
Cartridge tape
µS3K15CC78K3
NEWS
NEWS-OS
(QIC-24)
µS3R15CC78K3
and compatible machine
Remark The operation of the relocatable assembler and C compiler is guaranteed only on the host machine under
the operating systems listed above.
41
µPD78P328
PROM Write Tools
Hard-
PG-1500
PG-1500 is a PROM programmer which enables you to program single chip micro-
ware
controllers containing PROM by stand-alone or host machine operation by connecting an
attached board and optional programmer adapter to PG-1500. It also enables you to
program typical PROM devices of 256K bits to 4M bits.
UNISITE
PROM programmer manufactured by Data I. O. Japan.
2900
PA-78P328CW
PROM programmer adapters to write programs onto the µPD78P328 on a general
PA-78P328GF
purpose PROM programmer such as PG-1500.
PA-78P328CW ... µPD78P328CW and 78P328DW
PA-78P328GF ... µPD78P328GF
Soft-
PG-1500 controller
ware
Connects PG-1500 and a host machine by a serial or parallel interface and controlls
PG-1500 on the host machine.
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
µS5A13PG1500
5-inch 2HD
µS5A10PG1500
IBM PC/AT
PC DOS
3.5-inch 2HD
µS7B13PG1500
5-inch 2HC
µS7B10PG1500
and compatible machine
Remark The operation of the PG-1500 controller is guaranteed only on the host machine under the operating
systems listed above.
Debugging Tools
Hard-
IE-78327-R
IE-78327-R is an in-circuit emulator that can be used for application system development
ware
and debugging.
EP-78327CW-R
Emulation probe for 64-pin plastic shrink DIP to connect IE-78327-R to the target system.
EP-78327GF-R
Emulation probe for 94-pin plastic QFP to connect IE-78327-R to the target system.
EV-9200G-64 One conversion socket EV-9200G-64 used for connection to the target system
is attached.
Soft-
IE-78327-R
Program to control IE-78327-R on a host machine. Automatic execution of commands,
ware
control program
etc., is enabled for more efficient debugging.
(IE controller)
Host machine
Ordering code
OS
Supply medium
(product name)
PC-9800 series
MS-DOS
3.5-inch 2HD
µS5A13IE78327
5-inch 2HD
µS5A10IE78327
IBM PC/AT
PC DOS
3.5-inch 2HD
µS7B13IE78327
5-inch 2HC
µS7B10IE78327
and compatible machine
Remark The operation of the IE controller is guaranteed only on the host machine under the operating systems
listed above.
42
µPD78P328
Development Tool Configuration
Host machine
PC-9800 series or
IBM PC/AT
RS-232C
Emulation probe
Software
IE-78327-R
In-circuit
emulator
PG-1500 IE controller
Relocatable
controller
assembler (with
structure assembler)
On-chip PROM version
RS-232C
PROM
programmer
EP-78327GF-R
EP-78327GF-R
+
+
Socket to connect emulation probe and target systemNote
PG-1500
EV-9200G-64
SDIP socket
µPD78P328GF µPD78P328CW µPD78P328DW
+
+
Programmer adapter
+
Target system
PA-78P328GF
PA-78P328CW
Note The socket is attached to the emulation probe.
Remarks 1. The host machine and PG-1500 can be connected directly by RS-232-C.
2. Supply media of software are represented as 3.5-inch floppy disks in the figure above.
43
µPD78P328
B.2 Evaluation Tools
The following evaluation tools are provided to evaluate the µPD78P328 function:
Ordering Code
Host Machine
Function
PC-9800 series
The µPD78P328 function can be easily evaluated by connecting the evaluation tool to
(product name)
EB-78327-98
a host machine. The EB-78327-98/PC command system basically is compliant with the
EB-78327-PC
IBM PC/AT
IE-78327-R command system. Thus, easy transition to application system development
and compatible
process by IE-78327-R can be made. The evaluation tools enable turbo access manager
machine
(µPD71P301)Note to be mounted on the printed circuit board.
Note Turbo access manager (µPD71P301) is available for maintenance purpose only.
Cautions 1.
2.
EB-78327-98/PC is not the µPD78P328 application system development tool.
EB-78327-98/PC does not contain the emulation function at internal PROM execution of the
µPD78P328.
B.3 Embedded Software
The following embedded software products are readily available to support more efficient program development
and maintenance:
Real-time OS
Real-time OS
The purpose of RX78K/III is to realize a multi-task environment in a control area which requires
(RX78K/III)
real-time processing. RX78K/III allocates idle times of CPU to other processing to improve
overall performance of the system.
RX78K/III provides a system call based on the µITRON specification.
RX78K/III assembler package provides the RX78K/III nucleus and a tool (configurator) to
prepare multiple information tables.
Host machine
PC-9800 series
IBM PC/AT
and compatible machine
Ordering code
OS
Supply medium
(product name)
MS-DOS
3.5-inch 2HD
µS5A13RX78320
5-inch 2HD
µS5A10RX78320
3.5-inch 2HC
µS7B13RX78320
5-inch 2HC
µS7B10RX78320
PC DOS
Caution When purchasing the RX78K/III, fill in the purchase application form in advance, and sign the
User's Agreement.
Remark When using the RX78K/III Real-time OS, the RA78K/III assembler package (option) is necessary.
44
µPD78P328
Fuzzy Inference Development Support System
Fuzzy knowledge Data
Program supporting input of fuzzy knowledge data (fuzzy rule and membership function),
Preparation Tool
input/editing (edit), and evaluation (simulation).
(FE9000, FE9200)
Host machine
PC-9800 series
IBM PC/AT
Ordering code
OS
Supply medium
(product name)
MS-DOS
3.5-inch 2HD
µS5A13FE9000
5-inch 2HD
µS5A10FE9000
PC DOS WindowsTM 3.5-inch 2HC
and compatible machine
5-inch 2HC
µS7B13FE9200
µS7B10FE9200
Translator
Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation
(FT78K3)Note
tool to the assembler source program for the RA78K/III.
Host machine
PC-9800 series
IBM PC/AT
Ordering code
OS
Supply medium
(product name)
MS-DOS
3.5-inch 2HD
µS5A13FT78K3
5-inch 2HD
µS5A10FT78K3
3.5-inch 2HC
µS7B13FT78K3
5-inch 2HC
µS7B10FT78K3
PC DOS
and compatible machine
Fuzzy Inference Module
Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge
(FI78K/III)Note
data converted by translator.
Host machine
PC-9800 series
IBM PC/AT
Ordering code
OS
Supply medium
(product name)
MS-DOS
3.5-inch 2HD
µS5A13FI78K3
5-inch 2HD
µS5A10FI78K3
3.5-inch 2HC
µS7B13FI78K3
5-inch 2HC
µS7B10FI78K3
PC DOS
and compatible machine
Fuzzy Inference Debugger
Support software evaluating and adjusting fuzzy knowledge data at hardware level by using
(FD78K/III)
in-circuit emulator.
Host machine
PC-9800 series
IBM PC/AT
and compatible machine
Ordering code
OS
Supply medium
(product name)
MS-DOS
3.5-inch 2HD
µS5A13FD78K3
5-inch 2HD
µS5A10FD78K3
3.5-inch 2HC
µS7B13FD78K3
5-inch 2HC
µS7B10FD78K3
PC DOS
Note Under development
45
CHAPTER 2
[MEMO]
46
PIN FUNCTIONS
µPD78P328
NOTES FOR CMOS DEVICES
(1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate
oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it once,
when it has occurred. Environmental control must be adequate. When it is dry,
humidifier should be used. It is recommended to avoid using insulators that easily
build static electricity. Semiconductor devices must be stored and transported in an
anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
(2) HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection
is provided to the input pins, it is possible that an internal input level may be generated
due to noise, etc., hence causing malfunction. CMOS devices behave differently than
Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by
using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD
or GND with a resistor, if it is considered to have a possibility of being an output pin.
All handling related to the unused pins must be judged device by device and related
specifications governing the devices.
(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device.
Production
process of MOS does not define the initial operation status of the device. Immediately
after the power source is turned ON, the devices with reset function have not yet been
initialized.
Hence, power-on does not guarantee out-pin levels, I/O settings or
contents of registers. Device is not initialized until the reset signal is received. Reset
operation must be executed immediately after power-on for devices having reset
function.
QTOP is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
47
µPD78P328
The export of these products from Japan is regulated by the Japanese government. The export of some
or all of these products may be prohibited without governmental license. To export or re-export some or
all of these products from a country other than Japan may also be prohibited without a license from that
country. Please call an NEC sales representative.
License not needed: µPD78P328DW
The customer must judge the need for license: µPD78P328CW, 78P328GF-3BE
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property
arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in
its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computer, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for
life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems or medical equipment for life support, etc.
The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they
should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11