DATA SHEET MOS INTEGRATED CIRCUIT µ PD8861 5400 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD8861 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD8861 has 3 rows of 5400 pixels, and each row has a single-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell : 5400 pixels × 3 • Photocell pitch • Photocell size : 5.25 µ m 2 : 5.25 × 5.25 µ m • Line spacing : 42 µ m (8 lines) Red line - Green line, Green line - Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 24 dot/mm A4 (210 × 297 mm) size (shorter side) 7 600 dpi US letter (8.5” × 11”) size (shorter side) : • Drive clock level : CMOS output under 5 V operation • Data rate : 6 MHz Max. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits :: Voltage amplifiers ORDERING INFORMATION Part Number Package µ PD8861CY CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15167EJ2V0DS00 (2nd edition) Date Published June 2001 NS CP (K) Printed in Japan The mark shows major revised points. © 2000 µ PD8861 BLOCK DIAGRAM φ1 20 2 11 15 14 VOUT3 (Red) 2 13 φTG1 (Blue) 12 φ TG2 (Green) 10 φ TG3 (Red) S5400 D65 D66 D67 Photocell (Green) S5399 ······ D64 S1 S2 CCD analog shift register 21 Transfer gate S5400 D65 D66 D67 Photocell (Red) S5399 ······ D64 S1 S2 CCD analog shift register 22 D14 VOUT2 (Green) Photocell (Blue) Transfer gate D14 VOUT1 (Blue) ······ S5400 D65 D66 D67 φ2 S5399 GND D64 S1 S2 GND D14 VOD Transfer gate CCD analog shift register 1 4 3 5 8 9 φ CLB φ RB φ 1L φ2 φ1 Data Sheet S15167EJ2V0DS µ PD8861 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) • µ PD8861CY 22 VOUT2 Output signal 2 (Green) Ground GND 2 21 VOUT1 Output signal 1 (Blue) Reset gate clock φ RB 3 20 VOD Output drain voltage Reset feed-through level clamp clock φ CLB 4 19 NC No connection Last stage shift register clock 1 φ1L 5 18 NC No connection No connection NC 6 17 NC No connection No connection NC 7 16 NC No connection Shift register clock 2 φ2 8 15 φ2 Shift register clock 2 Shift register clock 1 φ1 9 14 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φ TG3 10 13 φ TG1 Transfer gate clock 1 (for Blue) Ground GND 11 12 φ TG2 Transfer gate clock 2 (for Green) Blue 5400 Green 5400 Red 5400 1 1 1 VOUT3 1 Output signal 3 (Red) PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) PHOTOCELL STRUCTURE DIAGRAM 5.25 µ m 5.25 µ m 2.75 µ m Blue photocell array 2.5 µ m 8 lines (42 µm) 5.25 µ m Green photocell array Channel stopper 8 lines (42 µm) 5.25 µ m Red photocell array Aluminum shield Data Sheet S15167EJ2V0DS 3 µ PD8861 ABSOLUTE MAXIMUM RATINGS (TA = +25°°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1, Vφ 2, Vφ 1L −0.3 to +8 V Reset gate clock voltage Vφ RB −0.3 to +8 V Reset feed-through level clamp clock Vφ CLB −0.3 to +8 V Transfer gate clock voltage Vφ TG1 to Vφ TG3 −0.3 to +8 V Operating ambient temperature TA 0 to +60 °C Storage temperature Tstg −40 to +70 °C voltage Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°°C) Parameter Symbol Min. Typ. Max. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ 1H, Vφ 2H, Vφ 1LH 4.5 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 2L, Vφ 1LL −0.3 0 +0.5 V Reset gate clock high level Vφ RBH 4.5 5.0 5.5 V Reset gate clock low level Vφ RBL −0.3 0 +0.5 V Reset feed-through level clamp clock Vφ CLBH 4.5 5.0 5.5 V Vφ CLBL −0.3 0 +0.5 V Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.5 Vφ 1H Transfer gate clock low level Vφ TG1L to Vφ TG3L −0.3 0 +0.3 V Data rate fφ RB − 1.0 6.0 MHz high level Reset feed-through level clamp clock low level Note Note Vφ 1H V Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H), Image lag can increase. 4 Data Sheet S15167EJ2V0DS µ PD8861 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ RB) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Min. Typ. Max. Unit Vsat 2.0 2.5 − V Red SER − 0.420 − lx•s Green SEG − 0.429 − lx•s Blue SEB − 0.739 − lx•s VOUT = 1.0 V − 6 20 % Saturation voltage Saturation exposure Photo response non-uniformity PRNU Test Conditions Average dark signal ADS Light shielding − 0.2 2.0 mV Dark signal non-uniformity DSNU Light shielding − 1.5 5.0 mV Power consumption PW − 360 540 mW Output impedance ZO − 0.35 1 kΩ Red RR 4.15 5.94 7.72 V/lx•s Green RG 4.07 5.82 7.57 V/lx•s Blue RB 2.36 3.38 4.39 V/lx•s − 1.5 7.0 % Response Image lag Offset level IL Note 1 Output fall delay time VOS Note 2 Total transfer efficiency Response peak Reset feed-through noise 4.0 5.5 7.0 V td VOUT = 1.0 V − 25 − ns TTE VOUT = 1.0 V, data rate = 6 MHz 92 98 − % − 630 − nm Red Green − 540 − nm Blue − 460 − nm Dynamic range Random noise (CDS) VOUT = 1.0 V Note 1 DR1 Vsat/DSNU − 1666 − times DR2 Vsat/σ CDS − 2777 − times RFTN Light shielding 0 750 1500 mV σ CDS Light shielding, bit clamp mode − 0.9 − mV Notes 1. Refer to TIMING CHART 2, 3. 2. When the fall time of φ 1L (t1’) is the Typ. value (refer to TIMING CHART 2, 3). Data Sheet S15167EJ2V0DS 5 µ PD8861 INPUT PIN CAPACITANCE (TA = +25°°C, VOD = 12 V) Parameter Symbol Pin name Shift register clock pin capacitance 1 Cφ 1 φ1 Shift register clock pin capacitance 2 Cφ 2 φ2 Pin No. Min. Typ. Max. Unit 9 − 300 − pF 14 − 300 − pF 8 − 300 − pF 15 − 300 − pF Last stage shift register clock pin capacitance Cφ L φ 1L 5 − 10 − pF Reset gate clock pin capacitance Cφ RB φ RB 3 − 10 − pF Reset feed-through level clamp clock pin capacitance Cφ CLB φ CLB 4 − 10 − pF Transfer gate clock pin capacitance Cφ TG φ TG1 13 − 100 − pF φ TG2 12 − 100 − pF φ TG3 10 − 100 − pF Remark Pin 9 and 14 (φ 1), 8 and 15 (φ 2) are each connected inside of the device. 6 Data Sheet S15167EJ2V0DS TIMING CHART 1 (for each color) φ TG1 to φ TG3 φ1 φ2 φ 1L φ RB Note Note 5463 5464 5465 5466 5467 5468 5469 61 62 63 64 65 66 φ CLB (Line clamp mode) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data Sheet S15167EJ2V0DS φ CLB (Bit clamp mode) VOUT1 to VOUT3 Optical black (49 pixels) Invalid photocell (2 pixels) And stop the φ RB pulse while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. Invalid photocell (3 pixels) 7 µ PD8861 Note Set the φ RB and φ CLB (Bit clamp mode) to high level during this period. Valid photocell (5400 pixels) µ PD8861 TIMING CHART 2 (Bit clamp mode, for each color) t1 t2 90% φ1 10% 90% φ2 10% t1' 90% φ 1L 10% t5 φ RB t2' t6 t3 t4 90% 10% t9 t7 t8 t10 t11 90% φ CLB 10% td RFTN VOUT VOS 10% Symbol Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3 20 200 − ns t4 40 300 − ns t5, t6 0 −5 t7 Note 5 − ns 50 − ns t8 35 200 − ns t9, t10 0 5 − ns t11 10 50 − ns Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 8 90% Data Sheet S15167EJ2V0DS µ PD8861 TIMING CHART 3 (Line clamp mode, for each color) t1 t2 90% φ1 10% 90% φ2 10% t1' 90% φ 1L 10% t5 t6 t3 t4 90% φ RB φ CLB t2' 10% "H" td RFTN VOUT VOS 10% Symbol Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3 20 200 − ns t4 40 300 − ns t5, t6 0 5 − ns Data Sheet S15167EJ2V0DS 9 µ PD8861 TIMING CHART 4 t13 t14 t12 90% 10% t15 φ TG1 to φ TG3 t16 90% φ1 φ2 90% φ 1L t17 Note 1 t18 90% φ RB t7 t11 90% φ CLB (Bit clamp mode) t20 t22 t21 Note 2 t23 90% 10% φ CLB (Line clamp mode) t9 Symbol Min. t10 Typ. Max. Unit 50 − ns t9, t10 0 5 − ns t11 10 50 − ns t12 t7 −5 Note 3 t19 3000 10000 50000 ns t13, t14 0 50 − ns t15, t16 900 1000 − ns t17, t18 200 400 − ns t19 t12 t12 50000 ns t20, t21 0 50 − ns t22, t23 0 350 − ns Notes 1. Set the φ RB and φ CLB (Bit clamp mode) to high level during this period. 2. Stop the φ RB pulse during this period. 3. Min. of t7 shows that the φ RB and φ CLB overlap each other. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. 10 Data Sheet S15167EJ2V0DS µ PD8861 φ 1, φ 2 cross points φ1 1.0 V to 4.0 V 1.0 V to 4.0 V φ2 φ 1L, φ 2 cross points φ2 φ 1L 2.0 V or more 0.5 V or more Remark Adjust cross points (φ 1, φ 2) and (φ 1L, φ 2) with input resistance of each pin. Data Sheet S15167EJ2V0DS 11 µ PD8861 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆ x : maximum of xj − x 5400 Σx j x= j=1 5400 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 5400 Σd j ADS (mV) = j=1 5400 dj : Dark signal of valid pixel number j 12 Data Sheet S15167EJ2V0DS µ PD8861 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 5400 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT Data Sheet S15167EJ2V0DS 13 µ PD8861 9. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the video output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by the following formula. VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following formula equation. 100 σ CDS (mV) = Σ (VCDS – V) i i=1 100 2 , V= 1 100 Σ VCDS 100 i = 1 Reset feed-through Video output 14 Data Sheet S15167EJ2V0DS i µ PD8861 STANDARD CHARACTERISTIC CURVES (Nominal) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 8 2 1 Relative Output Voltage 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA (°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 R G B 80 Response Ratio (%) Relative Output Voltage 4 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) Data Sheet S15167EJ2V0DS 15 µ PD8861 APPLICATION CIRCUIT EXAMPLE +5 V + 10 µ F/16 V 0.1 µ F µ PD8861 B3 1 47 Ω φ RB 47 Ω 150 Ω 3 4 5 6 7 φ2 22 VOUT2 B2 +12 V 2 φ CLB VOUT3 4.7 Ω 8 4.7 Ω 9 10 Ω 10 11 GND VOUT1 φ RB VOD 21 B1 20 + φ CLB NC φ 1L NC NC NC NC NC φ2 φ2 φ1 φ1 φ TG3 0.1 µ F 10 µ F/16 V 18 17 + 16 0.1 µ F 10 µ F/16 V φ TG1 φ TG2 GND +5 V 19 15 4.7 Ω 14 4.7 Ω 13 10 Ω 12 10 Ω φ1 φ TG Remark The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (2 MHz ≤ data rate < 6 MHz). B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 100 Ω 47 µ F/25 V 2SC945 2 kΩ 16 Data Sheet S15167EJ2V0DS µ PD8861 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400)) (Unit : mm) 1bit 2.0 9.25±0.3 0.5±0.3 37.5 44.0±0.3 10.16 (1.79) 2.55±0.2 1 1.02±0.15 (5.42) 2.54 4.21±0.5 0.46±0.1 0 ∼ 10° 0.05 0.25± 4.39±0.4 25.4 Name Plastic cap Dimensions 42.9 × 8.35 × 0.7 1 The bottom of the package Refractive index 2 1.5 The surface of the chip 2 The thickness of the cap over the chip 22C-1CCD-PKG6-1 Data Sheet S15167EJ2V0DS 17 µ PD8861 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “Semiconductor Device Mounting Technology Manual” (C10535E). Type of Through-hole Device µ PD8861CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) Process Partial heating method Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 18 Data Sheet S15167EJ2V0DS µ PD8861 NOTES ON CLEANING THE PLASTIC CAP 1 CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. 2 RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Symbol Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP Data Sheet S15167EJ2V0DS 19 µ PD8861 [MEMO] 20 Data Sheet S15167EJ2V0DS µ PD8861 [MEMO] Data Sheet S15167EJ2V0DS 21 µ PD8861 [MEMO] 22 Data Sheet S15167EJ2V0DS µ PD8861 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15167EJ2V0DS 23 µ PD8861 • The information in this document is current as of June, 2001. The information is subject to change without notice. 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