V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order (endian) conversion • I2O ATU and messaging unit including hardware controlled circular queues • Configurable for primary master, bus master or target operation. • Type 0 and type 1 configuration cycles. • 2 channel DMA controller plus multiprocessor DMA chaining and demand mode DMA • Up to 1Kbyte burst access on PCI or local. • Hot swapping capability • Large, 640-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION™ architecture • 16 8-bit bi-directional mailbox registers with doorbell interrupts • 64-byte read FIFO per aperture. • Flexible PCI and local interrupt management • Enhanced support for 8/16-bit local bus devices with programmable region sizes. • Optional power-on serial EEPROM initialization • 3.3 volt support • Industrials temperature grade -40 to +85’C • Dual bi-directional address space remapping • Low cost 160-pin EIAJ PQFP package • 33MHz and 40MHz local bus versions • Fully compliant with PCI 2.1 specification V350EPC is a high-performance and low-cost generic solution for interfacing both 32-bit and 16-bit multiplexed local bus applications to the PCI bus. V350EPC directly connects to i960Jx or i960Sx processors without any glue logic. Minimal glue logic is required for highperformance interfacing to other multiplexed processors like Motorola ColdFire™. architecture. V350EPC is the second generation of V3’s I2O ready PCI bridges - fully backward compatible with both V961PBC and V960PBC Rev B2 devices - and is supporting powerful features like Hot Swap and DMA chaining. The PCI bus can be run at the full 33MHz frequency, independent of local bus clock rate. The overall throughput of the system is dramatically improved by increasing the FIFO depths and utilizing the unique D Y N A M I C B A N D W I D T H A L L O C A T I O N ™ Two high-performance DMA channels with chaining and demand mode capabilities provide a powerful data transfer engine for bulk data transfers. Mailbox registers and flexible PCI interrupt controllers are also included to provide a simple mechanism to emulate PCI device control ports. The part is available in 160-pin low cost PQFP packages in 33MHz and 40MHz versions. V96BMC MEMORY CONTROL i960Jx CPU D R A M V350EPC LOCAL TO PCI BRIDGE Copyright © 1998, V3 Semiconductor Corp. Access to the PCI bus can be performed through two programmable address apertures. Two more apertures are provided for PCI-to-local bus accesses. There are 64-bytes of read FIFOs in each direction, 32-byte dedicated for each aperture . ROM TYPICAL APPLICATION PCI SLOT or EDGE CONNECTOR PCI PERIPHERAL V350EPC Data Sheet Rev 1.1 V3 Semiconductor reserves the right to change the specifications of this product without notice. V350EPC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners. 1 V350EPC This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V350EPC. Detailed functional information is contained in the User’s Manual. V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design. 1.0 Product Codes Table 1: Product Codes Product Code Processors Bus Type Package Frequency V350EPC-33 REV A0 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 33MHz V350EPC-40 REV A0 i960Jx/Sx 32/16-bit multiplexed 160-pin EIAJ PQFP 40MHz 2.0 Pin Description and Pinout Table 2 below lists the pin types found on the V350EPC. Table 3 describes the function of each pin on the V350EPC. Table 5 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical dimensions of the package. Table 2: Pin Types Pin Type PCI I PCI input only pin. PCI O PCI output only pin. PCI I/O PCI tri-state I/O pin. PCI I/OD I/O4 I O4 2 Description PCI input with open drain output. TTL I/O pin with 4mA output drive. TTL input only pin. TTL output pin with 4mA output drive. V350EPC Data Sheet Rev 1.1 Copyright © 1998, V3 Semiconductor Inc. V350EPC Table 3: Signal Descriptions PCI Bus Interface Signal Type Ra Description AD[31:0] PCI I/O Z Address and data, multiplexed on the same pins. C/BE[3:0] PCI I/O Z Bus Command and Byte Enables, multiplexed on the same pins. PAR PCI I/O Z Parity represents even parity across AD[31:0] and C/BE[3:0]. FRAME PCI I/O Z Cycle Frame indicates the beginning and burst length of an access. IRDY PCI I/O Z Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction. TRDY PCI I/O Z Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. STOP PCI I/O Z Stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect). Z Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, DEVSEL indicates whether any device on the bus has been selected. DEVSEL PCI I/O IDSEL PCI I REQ PCI O GNT PCI I Grant indicates to the agent that access to the bus has been granted. PCLK PCI I PCLK provides timing for all transactions on the PCI bus. PRST PCI I/O Z/L PERR PCI I/O Z Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. SERR PCI I/OD Z System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. INT[A:D] PCI I/OD Z Level-sensitive interrupt requests may be received or generated. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip’s internal configuration space. Z Copyright © 1998, V3 Semiconductor Corp. Request indicates to the arbiter that this agent requests use of the bus. Acts as an input when RDIR is high, an output when RDIR is low. As an input it is asserted low to bring all internal PBC operation to a reset state. V350EPC Data Sheet Rev 1.1 3 V350EPC Table 3: Signal Descriptions (cont’d) Local Bus Interface Signal Type R Description LAD[31:0] LAD[15:0]b I/O4 Z Local multiplexed address and data bus. LA[31:16]b I/O4 Z Local address bus. LA[5:2] O4 ALE I/O4 Z Address Latch Enable: used to latch the address during the address phase. BE[3:0] BE[1:0]b I/O4 Z Local bus byte enables. W/R I/O4 Z Write/Read. ADS ASb I/O4 Z Asserted low to indicate the beginning of a bus cycle. RDYRCV READYb I/O4 Z Local Bus data ready HOLD O4 L Local bus hold request: asserted by the chip to initiate a local bus master cycle. HOLDA I LPAR[3:0] LPAR[1:0]b I/O4 Z Local bus parity. BLAST I/O4 Z Burst last. BTERMc I/O4 Z Bus Time-out. Burst terminate. LINT O4 H Local interrupt request. LRST I/O4 L/Z LCLK I Lower local address bus (non-multiplexed version). Local bus hold acknowledge. Local bus RESET signal. Local bus clock. Serial EEPROM Interface 4 Signal Type R Description SCL/LPERR O4 X EEPROM clock. Local parity error. SDA I/O4 X EEPROM data. V350EPC Data Sheet Rev 1.1 Copyright © 1998, V3 Semiconductor Inc. V350EPC Table 3: Signal Descriptions (cont’d) Configuration Signal Type R Description RDIR I Reset direction. Tie low to drive PRST out and LRST in, high to drive LRST out and PRST in. EN5V I Selects 5V (EN5V driven low) or 3.3V (EN5V driven high) device operation modes. Power and Ground Signals Signal Type R Description VCC - POWER leads intended for external connection to a VCC board plane. GND - GROUND leads intended for external connection to a GND board plane. a. R indicates state during reset. b. Applies to i960Sx mode. c. Applies to i960Jx mode. 2.1 Test Mode Pins Several device pins are used during manufacturing test to put the V350EPC device into various test modes. These pins must be maintained at proper levels during reset to insure proper operation. This is typically handled through pull-up or pull-down resistors (typically 1K to 10K) on the signal pins if they are not guaranteed to be at the proper level during reset. Table 4 below shows the reset states for test mode pins: Table 4: RESET State for Test Mode Pins Mode Pin 134 Pin 135 Pin 153 i960Jx Pull-Down Pull-Up Pull-Down i960Sx Pull-Down Pull-Down Pull-Down Copyright © 1998, V3 Semiconductor Corp. V350EPC Data Sheet Rev 1.1 5 V350EPC Table 5: Pin Assignments 6 PIN # Signal PIN # Signal PIN # Signal PIN # Signal 1 VCC 41 VCC 81 VCC 121 VCC 2 INTD 42 AD14 82 NC 122 NC 3 PRST 43 AD13 83 LAD8 123 LA(Da)25 4 PCLK 44 AD12 84 NC 124 LA5 5 GNT 45 AD11 85 LAD9 125 LA(Da)26 6 REQ 46 AD10 86 NC 126 LA4 7 AD31 47 AD9 87 LAD10 127 LA(Da)27 8 AD30 48 AD8 88 NC 128 LA3 9 AD29 49 C/BE0 89 LAD11 129 LA(Da)28 10 AD28 50 VCC 90 NC 130 LA2 11 GND 51 GND 91 LAD12 131 LA(Da)29 12 AD27 52 AD7 92 NC 132 LA(Da)30 13 AD26 53 AD6 93 LAD13 133 LA(Da)31 14 AD25 54 AD5 94 NC 134 ALE 15 AD24 55 AD4 95 LAD14 135 ’0’ BTERMa 16 C/BE3 56 AD3 96 NC 136 READY RDYRCVa 17 IDSEL 57 AD2 97 LAD15 137 HOLD 18 AD23 58 AD1 98 NC 138 HOLDA 19 AD22 59 AD0 99 LA(Da)16 139 AS ADSa 20 VCC 60 VCC 100 VCC 140 VCC 21 GND 61 GND 101 GND 141 GND 22 AD21 62 LAD0 102 NC 142 LCLK 23 AD20 63 NC 103 LA(Da)17 143 EN5V 24 AD19 64 LAD1 104 NC 144 VCC V350EPC Data Sheet Rev 1.1 Copyright © 1998, V3 Semiconductor Inc. V350EPC Table 5: Pin Assignments (cont’d) PIN # Signal PIN # Signal PIN # Signal PIN # Signal 25 AD18 65 NC 105 LA(Da)18 145 LAb BE3a 26 AD17 66 LAD2 106 NC 146 NC BE2a 27 AD16 67 NC 107 LA(Da)19 147 BE1 28 C/BE2 68 LAD3 108 NC 148 BE0 29 FRAME 69 NC 109 LA(Da)20 149 BLAST 30 GND 70 LAD4 110 NC 150 W/R 31 IRDY 71 NC 111 LA(Da)21 151 RDIR 32 TRDY 72 LAD5 112 NC 152 LRST 33 DEVSEL 73 NC 113 LA(Da)22 153 ’0’ 34 STOP 74 LAD6 114 NC 154 LINT 35 PERR 75 NC 115 LA(Da)23 155 SDA 36 SERR 76 LAD7 116 NC 156 SCL/LPERR 37 PAR 77 NC 117 NC LPAR2a 157 INTA 38 C/BE1 78 LPAR0 118 NC LPAR3a 158 INTB 39 AD15 79 LPAR1 119 LA(Da)24 159 INTC 40 GND 80 GND 120 GND 160 GND a. Applies to i960Jx mode. b )Applies to i960Sx mode Copyright © 1998, V3 Semiconductor Corp. V350EPC Data Sheet Rev 1.1 7 V350EPC Figure 1: Pinout for 160-pin EIAJ PQFP (top view) 8 V350EPC Data Sheet Rev 1.1 Copyright © 1998, V3 Semiconductor Inc. V350EPC Figure 2: 160-pin EIAJ PQFP mechanical details Unit of Measurement = millimeters Copyright © 1998, V3 Semiconductor Corp. V350EPC Data Sheet Rev 1.1 9 V350EPC 3.0 DC Specifications The DC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.1. For more information on the PCI DC specifications, see the PCI Specification. Table 6: Absolute Maximum Ratings Symbol Parameter Value Units -0.3 to +7 V VCC Supply voltage VIN DC input voltage -0.3 to VCC+0.3 V IIN DC input current ± 10 mA Tj Junction temperature 125 °C -40 to +125 °C TSTG Storage temperature range Table 7: Guaranteed Operating Conditions Symbol Parameter Units VCC Supply voltage 5 volt 4.50 to 5.50 V VCC Supply voltage 3.3 volt 3.0 to 3.60 V 50 °C/w -40 to 85 °C Theta Ja Thermal resistance TA 3.1 Value Ambient temperature range PCI Bus DC Specifications Table 8: PCI Bus Signals DC Operating Specifications Symbol 10 Parameter Condition Min Max Units Notes VIH Input high voltage 2.0 VCC+0.5 V VIL Input low voltage -0.5 0.8 V IIH Input high leakage current VIN = 2.7V 70 µA 1 IIL Input low leakage current VIN = 0.5V -70 µA 1 VOH Output high voltage IOUT = -2mA VOL Output low voltage IOUT = 3mA, 6mA CIN Input pin capacitance V350EPC Data Sheet Rev 1.1 2.4 V 0.55 V 2 10 pF 3 Copyright © 1998, V3 Semiconductor Inc. V350EPC Table 8: PCI Bus Signals DC Operating Specifications Symbol Parameter Condition Min Max Units 5 12 pF CCLK PCLK pin capacitance CIDSEL IDSEL pin capacitance 8 pF Pin inductance 20 nH LPIN Notes 4 Notes: 1. Input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state outputs. 2. Signals without pull-up resistors have greater than 3mA low output current. Signals requiring pull resistors have greater than 6mA output current. The latter include FRAME, TRDY, IRDY, STOP, SERR, PERR. 3. Absolute maximum pin capacitance for a PCI unit is 10pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. 3.2 Local Bus DC Specifications Table 9: Local Bus Signals DC Operating Specifications for Vcc = 5 volt Symbol Description Conditions Min Max Units 0.8 V VIL Low level input voltage VCC = 4.75V VIH High level input voltage VCC = 5.25V 2.0 V IIL Low level input current VIN=GND, VCC=5.25V -10 µA IIH High level input current VIN = VCC = 5.25V 10 µA 0.4 V VOL4 Low level output voltage for 4 mA outputs and I/O pins IOL = -4 mA VOH4 High level output voltage for 4 mA outputs and I/O pins IOH = 4 mA 2.4 V IOZL Low level float input leakage VIN = GND -10 µA IOZH High level float input leakage VIN = VCC 10 µA VCC = 5.25V PCLK = LCLK = 33MHz 150 mA VCC = 5.0V PCLK = LCLK = 33MHz 120 mA 10 pF ICC (max) Maximum supply current ICC (typ) CIO Typical supply current Input and output capacitance Copyright © 1998, V3 Semiconductor Corp. V350EPC Data Sheet Rev 1.1 11 V350EPC Table 10: Local Bus Signals DC Operating Specifications for Vcc =3.3 volt Symbol Description Min Max Units 0.8 V VIL Low level input voltage VCC = 3.0V VIH High level input voltage VCC = 3.6V 2.0 V IIL Low level input current VIN=GND, VCC=3.6V -10 µA IIH High level input current VIN = VCC = 3.6V 10 µA 0.4 V VOL4 Low level output voltage for 4 mA outputs and I/O pins IOL = -4 mA VOH4 High level output voltage for 4 mA outputs and I/O pins IOH = 4 mA 2.4 V IOZL Low level float input leakage VIN = GND -10 µA IOZH High level float input leakage VIN = VCC 10 µA VCC = 3.6V PCLK = LCLK = 33MHz 150 mA VCC = 3.3V PCLK = LCLK = 33MHz 120 mA 10 pF ICC (max) Maximum supply current ICC (typ) CIO 12 Conditions Typical supply current Input and output capacitance V350EPC Data Sheet Rev 1.1 Copyright © 1998, V3 Semiconductor Inc. V350EPC 4.0 AC Specifications The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.2. For more information on the PCI AC specifications, including the V/I curves for 5V signalling, see section 4.2.1.2 of Rev 2.1 PCI Specification. 4.1 PCI Bus Timings Table 11: PCI Bus Signals AC Operating Specifications Symbol IOH(AC) Parameter Switching current high (Test point) IOL(AC) Switching current low Condition Min 0V<VOUT≤1.4V -44 1.4V<VOUT<2.4V -44+(VOUT-1.4)/0.024 VOUT=3.1V VOUT≥2.2V 95 2.2V>VOUT>0.55 VOUT/0.023 Max Units Notes mA 1 Equation A mA 1, 2, 3 -142 mA 3 mA 1 Equation B mA 1, 3 206 mA 3 (Test point) VOUT=0.71 ICL Low clamp current -5<VIN≤-1 -25+(VIN+1)/0.015 tR Unloaded output rise time 0.4V to 2.4V 1 5 V/ns 4 tF Unloaded output fall time 2.4V to 0.4V 1 5 V/ns 4 mA Notes: 1. Refer to the V/I curves in Section 4.2.1 of the PCI Specification. This specification does not apply to CLK and RST which are system outputs. “Switching Current High” specifications are not relevant to open drain outputs such as SERR and INTA-INTD. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as it does in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements are met as drivers pull beyond the first step voltage (AC drive point). Equations defining these maximums (A and B) are provided with the respective V/I curves given in the PCI Spec. The equation defined maxima is met by design. 4. The minimum slew rate (slowest signal edge) is met by the PCI drivers. The maximum slew rate (fastest signal edge) is a guideline. Motherboard designers must bear in mind that rise and fall times faster than this maximum guideline could occur, and should ensure that signal integrity modeling accounts for this. Equation A: IOH = 11.9·(VOUT - 5.25V)·(VOUT + 2.45V) for VCC > VOUT > 3.1V Equation B: IOL = 78.5·VOUT(4.4V - VOUT) for 0V < VOUT < 0.71V Copyright © 1998, V3 Semiconductor Corp. V350EPC Data Sheet Rev 1.1 13 V350EPC 4.2 Local Bus Timings Table 12: Local Bus AC Test Conditions Symbol Parameter VCC Supply voltage 5 volt VCC Supply voltage 3.3 volt VIN Input low and high voltages COUT Capacitive load on output and I/O pins Limits Units 4.50 to 5.50 V 3.0 to 3.6 V 0.4 and 2.0 V 50 pF Table 13: Capacitive Derating for Output and I/O Pins Output Drive Limit Supply voltage Derating 4mA 5 volt 0.058 ns/pF for loads > 50pF 4mA 3.3 volt 0.099 ns/pF for loads > 50pF Figure 3: Clock and Synchronous Signals 14 V350EPC Data Sheet Rev 1.1 Copyright © 1998, V3 Semiconductor Inc. V350EPC Table 14: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5% 33MHz # Symbol Description 1 TC LCLK period 2 TCH LCLK high time 3 TCL 4 Notes Min Max 40MHz Min Max Units 30 25 ns 1 12 11 ns LCLK low time 1 12 11 ns TSU Synchronous input setup 2 7 6 ns 4a TSU Synchronous input setup (BLAST) 8 7 ns 4b TSU Synchronous input setup (W/R, BTERM) 4 4 ns 4c TSU Synchronous input setup (ADS/AS) 6 5 ns 4d TSU Synchronous input setup (address, data, byte enables) 9 8 ns 4e TSU Synchronous input setup for read data when in local bus master mode 5 5 ns 5 TH Synchronous input hold 6 TCOV LCLK to output valid delay 6a TCOV 7 2 ns 3 14 3 12 ns LCLK to output valid delay (address, data, byte enable, parity) 3 15 3 14 ns TCZO LCLK to output driving delay 3 15 3 14 ns 8 TCOZ LCLK to high impedance delay 3 15 3 14 ns 9 TRST Reset period when LRST used as input Copyright © 1998, V3 Semiconductor Corp. 3 2 4 16·TC V350EPC Data Sheet Rev 1.1 16·TC ns 15 V350EPC Table 15: Local Bus Timing Parameters for Vcc = 3.3 Volts +/- 5% 33MHz # Symbol Description 1 TC LCLK period 2 TCH LCLK high time 3 TCL 4 Notes Min Max Units 30 ns 1 12 ns LCLK low time 1 12 ns TSU Synchronous input setup 2 8 ns 4a TSU Synchronous input setup (BLAST) 9 ns 4b TSU Synchronous input setup (W/R, BTERM) 7 ns 4c TSU Synchronous input setup (ADS/AS) 8 ns 4d TSU Synchronous input setup (address, data, byte enables) 7 ns 4e TSU Synchronous input setup for read data when in local bus master mode 5 ns 5 TH Synchronous input hold 6 TCOV LCLK to output valid delay 6a TCOV 7 3 ns 4 14 ns LCLK to output valid delay (address, data, byte enable, parity) 4 16 ns TCZO LCLK to output driving delay 4 16 ns 8 TCOZ LCLK to high impedance delay 4 16 ns 9 TRST Reset period when LRST used as input 3 4 16·TC ns Notes: 1. Measured at 1.5V. 2. All local bus signals except those in 4a, 4b, 4c, 4d and 4e. 3. All local bus signals except those in 6a. 4. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK. Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 5% 16 # Symbol Description 1 TC PCLK period 2 TSU Synchronous input setup to PCLK 2a TSU Synchronous input setup to PCLK (GNT) V350EPC Data Sheet Rev 1.1 Notes 1 Min Max Units 30 ns 7 ns 10 ns Copyright © 1998, V3 Semiconductor Inc. V350EPC Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 5% 3 TH Synchronous input hold from PCLK 4 TCOV PCLK to output valid delay 4a TCOV 5 0 2 ns 3 11 ns PCLK to output valid delay (REQ) 4 12 ns TCZO PCLK to output driving delay 4 11 ns 6 TCOZ PCLK to high impedance delay 5 18 ns 7 TRST Reset period when PRST used as input 16·TC Notes: 1. All PCI bus signals except those in 2a. 2. All PCI bus signals except those in 4a. 4.3 Serial EEPROM Port TImings The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are shown in Figure 4. Figure 4: Serial EEPROM Waveforms and Timings 512 PCI BUS CLOCKS START CONDITION STOP CONDITION SCL SDA 256 PCI BUS CLOCKS Copyright © 1998, V3 Semiconductor Corp. 256 PCI BUS CLOCKS V350EPC Data Sheet Rev 1.1 17 V350EPC 5.0 Revision History Table 17: Revision History Revision Number Date 1.1 5/98 Addition of 3.3 volt information. 1.0 8/97 First revision of preliminary data sheet. 18 Comments and Changes V350EPC Data Sheet Rev 1.1 Copyright © 1998, V3 Semiconductor Inc.