STMICROELECTRONICS VN5050JTR-E

VN5050J-E
Single channel high side driver
for automotive applications
Features
Max supply voltage
VCC
41V
Operating voltage range
VCC
4.5 to 36V
Max On-State resistance (per ch.)
RON
50 mΩ
Current limitation (typ)
ILIMH
19 A
Off state supply current
IS
2 µA(1)
PowerSSO-12
Application
(1) Typical value with all loads connected
■
■
■
Main
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
Description
The VN5050J-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
with one side connected to ground. Active VCC pin
voltage clamp protects the device against low
energy spikes (see ISO7637 transient
compatibility table). The device detects open load
condition both in on and off state, when STAT_DIS
is left open or driven low. Output shorted to VCC is
detected in the off state.
Diagnostic functions
– Open drain status output
– On state open load detection
– Off state open load detection
– Thermal shutdown indication
■
All types of resistive, inductive and capacitive
loads
Protections
– Undervoltage shut-down
– Overvoltage clamp
– Output stuck to VCC detection
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shut down
– Reverse battery protection (see Figure 27)
– Electrostatic discharge protection
Table 1. Device summary
When STAT_DIS is driven high, the STATUS pin
is in a high impedance condition.Output current
limitation protects the device in overload
condition. In case of long duration overload, the
device limits the dissipated power to safe level up
to thermal shut-down intervention.Thermal shutdown with automatic restart allows the device to
recover normal operation as soon as fault
condition disappears.
Order codes
Package
PowerSSO-12
September 2007
Tube
Tape & Reel
VN5050J-E
VN5050JTR-E
Rev 2
1/31
www.st.com
31
Contents
VN5050J-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
4
6
2/31
3.1.1
Solution 1: resistor in the ground line (RGND only). . . . . . . . . . . . . . . . 20
3.1.2
Solution 2: diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . 21
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3
MCU I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4
Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VN5050J-E
List of tables
List of tables
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin (VSD=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
VN5050J-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
4/31
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Openload on state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Openload off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-12 PC Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 25
Thermal fitting model of a single channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VN5050J-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
VCC
VCC
CLAMP
UNDERVOLTAGE
PwCLAMP
GND
DRIVER
OUTPUT
ILIM
INPUT
VDSLIM
LOGIC
STATUS
OPENLOAD ON
OPENLOAD OFF
STAT_DIS
OVERTEMP.
PwrLIM
Table 2.
Pin function
Name
VCC
OUTPUT
GND
INPUT
STATUS
STAT_DIS
Function
Battery connection
Power output
Ground connection. Must be reverse battery protected by an external diode/resistor
network
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
Open drain digital diagnostic pin
Active high CMOS compatible pin, to disable the STATUS pin
5/31
Block diagram and pin description
Figure 2.
VN5050J-E
Configuration diagram (top view)
TAB = Vcc
N.C.
GND
INPUT
STATUS_DIS
STATUS
N.C.
12
11
10
9
8
7
1
2
3
4
5
6
N.C.
OUTPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
PowerSSO-12
Table 3.
Suggested connections for unused and n.c. pins
Connection / Pin
Floating
To ground
(1) Not recommended
6/31
Status
N.C.
Output
Input
STAT_DIS
X
X
X
X
X
N.R.(1)
X
N.R.
Through 10KΩ
resistor
Through 10KΩ
resistor
VN5050J-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VCC
VF
ISD
IOUT
STAT_DIS
OUTPUT
VSD
VOUT
IIN
ISTAT
INPUT
STATUS
VIN
VSTAT
GND
IGND
Note:
VF = VOUT - VCC during reverse battery condition
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 4.
Absolute maximum ratings
Symbol
Value
Unit
DC supply voltage
41
V
- VCC
Reverse DC supply voltage
0.3
V
- IGND
DC reverse ground pin current
200
mA
Internally limited
A
12
A
VCC
IOUT
- IOUT
Parameter
DC output current
Reverse DC output current
IIN
DC input current
+10 / -1
mA
ISTAT
DC status current
+10 / -1
mA
+10 / -1
mA
104
mJ
ISTAT_DIS DC status disable current
EMAX
Maximum switching energy
(L=3mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.))
7/31
Electrical specifications
Table 4.
Absolute maximum ratings (continued)
Symbol
Value
Unit
VESD
Electrostatic discharge
(Human Body Model: R=1.5KΩ; C=100pF)
- INPUT
- STATUS
- STAT_DIS
- OUTPUT
- VCC
4000
4000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Tstg
2.2
Parameter
Junction operating temperature
-40 to 150
°C
Storage temperature
- 55 to 150
°C
Thermal data
Table 5.
Symbol
8/31
VN5050J-E
Thermal data
Parameter
Rthj-case
Thermal resistance junction-case (Max.)
(with one channel ON)
Rthj-amb
Thermal resistance junction-ambient (Max.)
Value
Unit
2.7
°C/W
See Figure 31
°C/W
VN5050J-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8V<VCC<36V; -40°C<Tj<150°C, unless otherwise
specified
.
Table 6.
Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
VUSDhyst
Test conditions
Min.
Typ.
Max.
Unit
4.5
13
36
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage shut-down
hysteresis
0.5
On state resistance(2)
IOUT=1A; Tj=25°C
IOUT=1A; Tj=150°C
IOUT=1A; VCC=5V; Tj=25°C
Clamp voltage
IS=20mA
IS
Supply current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V;
IOUT=0A
IL(off1)
Off state output
current(2)
VIN=VOUT=0V; VCC=13V;
Tj=25°C
VIN=VOUT=0V; VCC=13V;
Tj=125°C
RON
Vclamp
IL(off2)
VF
Off state output current(2) VIN=0V; VOUT=4V
Output - VCC diode
voltage(2)
41
0
V
50
100
65
mΩ
mΩ
mΩ
46
52
V
2(1)
1.9
5(1)
3.5
µA
mA
0.01
3
0
5
-75
0
-IOUT=2A; Tj=150°C
µA
0.7
V
Max.
Unit
(1) PowerMOS leakage included.
(2) For each channel
Table 7.
Symbol
Switching (VCC = 13V; Tj = 25°C)
Parameter
Test conditions
Min.
Typ.
td(on)
Turn-on delay time
RL= 6.5Ω (see Figure 5)
20
µs
td(off)
Turn-off delay time
RL= 6.5Ω (see Figure 5)
35
µs
dVOUT/dt(on) Turn-on voltage slope
RL= 6.5Ω
see Figure 21
V/ µs
dVOUT/dt(off) Turn-off voltage slope
RL= 6.5Ω
see Figure 23
V/ µs
WON
Switching energy losses
during twon
RL= 6.5Ω (see Figure 5)
0.2
mJ
WOFF
Switching energy losses
during twoff
RL= 6.5Ω (see Figure 5)
0.2
mJ
9/31
Electrical specifications
Table 8.
Symbol
VN5050J-E
Status pin (VSD=0V)
Parameter
Test conditions
Min
Typ
Max
Unit
VSTAT
Status low output
voltage
ISTAT= 1.6 mA, VSD=0V
0.5
V
ILSTAT
Status leakage current
Normal Operation or VSD=5V,
VSTAT= 5V
10
µA
CSTAT
Status pin input
capacitance
Normal Operation or VSD=5V,
VSTAT= 5V
100
pF
VSCL
Status clamp voltage
ISTAT= 1mA
ISTAT= -1mA
7
V
V
Table 9.
Symbol
Parameter
Test conditions
DC Short circuit current
VCC=13V
5V<VCC<36V
IlimL
Short circuit current
during thermal cycling
VCC=13V
TR<Tj<TTSD
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of
STATUS
tSDL
VDEMAG
VON
-0.7
Protections (1)
IlimH
THYST
5.5
Min.
Typ.
Max.
Unit
13.5
19
26.5
26.5
A
A
7
150
175
A
200
TRS + 1 TRS + 5
°C
135
Thermal hysteresis
(TTSD-TR)
°C
7
Status delay in overload
conditions
Tj>TTSD (see Figure 4)
Turn-off output voltage
clamp
IOUT=2A; VIN=0; L=6mH
Output voltage drop
limitation
IOUT = 0.1A;
Tj= -40°C...+150°C
(see Figure 6)
°C
20
µs
VCC-41 VCC-46 VCC-52
V
25
mV
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles
10/31
°C
VN5050J-E
Electrical specifications
Table 10.
Symbol
Openload detection
Parameter
Test conditions
IOL
Openload ON State
Detection Threshold
VIN = 5V ,8V<VCC<18V
tDOL(on)
Openload ON State
Detection Delay
IOUT = 0A, VCC=13V
(see Figure 4)
tPOL
Delay between INPUT
falling edge and STATUS
= 0A (see Figure 4)
I
rising edge in Openload OUT
condition
VOL
Openload OFF State
Voltage Detection
Threshold
VIN = 0V, 8V<VCC<16V
Output Short Circuit to
VCC Detection Delay at
Turn Off
(see Figure 4)
tDSTKON
Table 11.
Symbol
Parameter
Test conditions
Input Low Level
IIL
Low Level Input Current
VIH
Input High Level
IIH
High Level Input Current VIN = 2.1 V
VIN =0.9 V
Input Hysteresis Voltage
VICL
Input Clamp Voltage
VSDL
STAT_DIS low level
voltage
ISDL
Low level STAT_DIS
current
VSDH
STAT_DIS high level
voltage
ISDH
High level STAT_DIS
current
VSD(hyst)
STAT_DIS hysteresis
voltage
VSDCL
Typ
Max
Unit
10
See
Figure 18
50
mA
200
µs
200
500
1000
µs
2
See
Figure 19
4
V
tPOL
µs
Max.
Unit
0.9
V
180
Logic input
VIL
VI(hyst)
Min
STAT_DIS clamp voltage
Min.
Typ.
1
µA
2.1
V
10
0.25
IIN = 1mA
IIN = -1mA
VSD = 0.9 V
V
5.5
7
V
V
0.9
V
-0.7
1
µA
2.1
V
VSD = 2.1 V
10
0.25
ISD=1mA
ISD=-1mA
µA
µA
V
5.5
7
-0.7
V
V
11/31
Electrical specifications
Figure 4.
VN5050J-E
Status timings
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
VIN
VOUT < VOL
OPEN LOAD STATUS TIMING (with external pull-up)
VOUT > VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OVER TEMP STATUS TIMING
OUTPUT STUCK TO VCC
Tj > TTSD
IOUT > IOL
VIN
VOUT > VOL
VSTAT
VIN
VSTAT
tDOL(on)
Truth Table
IOUT < IOL
VIN
Table 12.
tSDL
tDSTKON
Truth table
Conditions
Input
Output
Status (VSD=0V)(1)
Normal operation
L
H
L
H
H
H
Current limitation
L
H
L
X
H
H
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output voltage > VOL
L
H
H
H
Lv
H
Output current < IOL
L
H
L
H
H(2)
L
(1) If the VSD is high, the STATUS pin is in a high impedance.
(2) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
12/31
tSDL
VN5050J-E
Electrical specifications
Figure 5.
Switching characteristics
VOUT
tWon
tWoff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
tr
tf
t
INPUT
td(on)
td(off)
t
Figure 6.
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
Iout
13/31
Electrical specifications
Table 13.
VN5050J-E
Electrical transient requirements
ISO 7637-2:
2004(E)
Test levels
Test pulse
III
IV
Number of
pulses or
test times
1
-75V
-100V
5000 pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37V
+50V
5000 pulses
0.2 s
5s
50 µs, 2 Ω
3a
-100V
-150V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75V
+100V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6V
-7V
1 pulse
100 ms,
0.01Ω
5b(2)
+65V
+87V
1 pulse
400 ms, 2 Ω
Burst cycle/pulse
repetition time
Delays and
Impedance
Test level results(1)
ISO 7637-2:
2004(E)
Test pulse
III
IV
1
2a
3a
3b
4
5b(2)
C
C
C
C
C
C
C
C
C
C
C
C
(1) The above test levels must be considered referred to VCC = 13.5V except for pulse 5b
(2) Valid in case of external load dump clamp: 40V maximum referred to ground.
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
14/31
VN5050J-E
Electrical specifications
Figure 7.
Waveforms
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
STAT_DIS
LOAD CURRENT
undefined
STATUS
OPEN LOAD with external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
VOL
VOUT>VOL
STATUS
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
IOUT<IOL
LOAD CURRENT
tPOL
STATUS
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
IOUT>IOL
LOAD VOLTAGE
VOUT>VOL
VOL
STATUS
tDSTKON
OVERLOAD OPERATION
Tj
TTSD
TR
TRS
INPUT
STAT_DIS
ILIMH
ILIML
LOAD CURRENT
STATUS
current power
limitation limitation
thermal cycling
SHORTED LOAD
NORMAL LOAD
15/31
Electrical specifications
VN5050J-E
2.4
Electrical characteristics curves
Figure 8.
Off state output current
Figure 9.
Iloff1 (uA)
High level input current
lih (uA)
1
5
4.5
0.875
Off state
Vcc=13V
Vin=Vout=0V
0.75
Vin=2.1V
4
3.5
0.625
3
0.5
2.5
2
0.375
1.5
0.25
1
0.125
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C )
50
75
100
125
150
175
100
125
150
175
150
175
Tc (°C )
Figure 10. Input clamp voltage
Figure 11. Input high level
Vih (V)
Vicl (V)
4
8
3.5
7.75
lin=1mA
7.5
3
7.25
2.5
7
2
6.75
1.5
6.5
1
6.25
0.5
6
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Figure 12. Input low level
75
Figure 13. Input hysteresis voltage
Vil (V)
Vihyst (V)
4
2
3.5
1.75
3
1.5
2.5
1.25
2
1
1.5
0.75
1
0.5
0.5
0.25
0
0
-50
-25
0
25
50
75
Tc (°C )
16/31
50
Tc (°C )
Tc (°C )
100
125
150
175
-50
-25
0
25
50
75
Tc (°C )
100
125
VN5050J-E
Electrical specifications
Figure 14. Status low output voltage
On state resistance vs Tcase
Vstat (V)
Ron (mOhm)
0.9
100
90
0.8
Istat=1.6mA
Iout=2A
Vcc=13V
80
0.7
70
0.6
60
0.5
50
0.4
40
0.3
30
0.2
20
0.1
10
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 15. Status leakage current
Figure 16. On state resistance vs VCC
Ilstat (uA)
Ron (mOhm)
0.055
100
90
0.05
Tc= 150°C
80
Vstat=5V
70
0.045
Tc= 125°C
60
0.04
0.035
50
Tc= 25°C
40
Tc= -40°C
30
20
0.03
10
0
0.025
-50
-25
0
25
50
75
100
125
150
0
175
5
10
15
20
25
30
35
40
Vcc (V)
Tc (°C )
Figure 17. Status clamp voltage
Figure 18. Openload on state detection
threshold
Vscl (V)
Iol (mA)
9
100
8.5
90
Istat=1mA
8
Vin=5V
80
7.5
70
7
60
6.5
50
6
40
5.5
30
5
20
4.5
10
4
0
-50
-25
0
25
50
75
Tc (°C )
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
17/31
Electrical specifications
VN5050J-E
Figure 19. Openload off state voltage detection Figure 20. ILIM vs Tcase
threshold
Ilimh (A)
Vol (V)
25
5
22.5
4.5
Vcc=13V
Vin=0V
4
20
3.5
17.5
3
15
2.5
12.5
2
10
1.5
7.5
5
1
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 21. Turn-on voltage slope
Figure 22. Undervoltage shutdown
dVout/dt(on) (V/ms)
Vusd (V)
1000
14
900
Vcc=13V
RI=6.5Ohm
800
12
700
10
600
8
500
400
6
300
4
200
2
100
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C )
50
75
100
125
150
175
150
175
Tc (°C )
Figure 23. Turn-off voltage slope
Figure 24. STAT_DIS clamp voltage
dVout/dt(off) (V/ms)
Vsdcl(V)
1000
14
900
Vcc=13V
RI=6.5Ohm
800
12
Isd=1mA
700
10
600
8
500
400
6
300
4
200
2
100
0
0
-50
-25
0
25
50
75
Tc (°C )
18/31
100
125
150
175
-50
-25
0
25
50
75
Tc (°C )
100
125
VN5050J-E
Electrical specifications
Figure 25. High level STAT_DIS voltage
Figure 26. Low level STAT_DIS voltage
Vsdh(V)
Vsdl(V)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-50
-25
0
25
50
75
Tc (°C )
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
19/31
Application information
3
VN5050J-E
Application information
Figure 27. Application schematic
+5V
+5V
VCC
Rprot
STAT_DIS
Dld
Rprot
INPUT
µC
OUTPUT
Rprot
STATUS
GND
VGND
RGND
DGND
3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (RGND only).
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤600mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
20/31
VN5050J-E
3.1.2
Application information
Solution 2: diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection:
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤Rprot ≤(VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤Rprot ≤65kΩ.
Recommended values: Rprot =10kΩ.
3.4
Open load detection in off state
Off state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2.
no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
21/31
Application information
VN5050J-E
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical characteristics
section.
Figure 28. Open load detection in off state
V batt.
VPU
V CC
R PU
INP UT
DRIVER
+
LOGIC
IL(off2)
OUT
+
S TATUS
R
V OL
G ROUND
22/31
RL
VN5050J-E
3.5
Application information
Maximum demagnetization energy (VCC = 13.5V)
Figure 29. Maximum turn off current versus inductance
100
A
B
C
I (A)
10
1
0,1
1
L (mH)
10
100
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
23/31
Package and PCB thermal data
VN5050J-E
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 30. PowerSSO-12 PC Board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 31. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
70
65
60
55
50
45
40
0
2
4
6
PCB Cu heatsink area (cm^2)
24/31
8
10
VN5050J-E
Package and PCB thermal data
Figure 32. PowerSSO-12 thermal impedance junction ambient single pulse
ZTH (°C/W)
Footprint
100
2 cm2
8 cm2
10
1
0,1
0,0001
0,001
0,01
0,1
1
Time (s)
10
100
1000
Equation 1: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ)
where δ = tP/T
Figure 33. Thermal fitting model of a single channel HSD in PowerSSO-12(a)
(a )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered
25/31
Package and PCB thermal data
Table 14.
Thermal parameter
Area/island (cm2)
26/31
VN5050J-E
Footprint
2
8
R1 (°C/W)
0.6
R2 (°C/W)
2.8
R3 (°C/W)
6.5
R4 (°C/W)
10
10
9
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1 (W.s/°C)
0.001
C2 (W.s/°C)
0.0025
C3 (W.s/°C)
0.022
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
VN5050J-E
Package information
5
Package information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
Package mechanical data
Figure 34. PowerSSO-12™ package dimensions
27/31
Package information
VN5050J-E
Table 15.
PowerSSO-12™ mechanical data
millimeters
Symbol
Min
Max
A
1.250
1.620
A1
0.000
0.100
A2
1.100
1.650
B
0.230
0.410
C
0.190
0.250
D
4.800
5.000
E
3.800
4.000
e
0.800
H
5.800
6.200
h
0.250
0.500
L
0.400
1.270
k
0°
8°
X
2.200
2.800
Y
2.900
3.500
ddd
28/31
Typ
0.100
VN5050J-E
5.3
Package information
Packing information
Figure 35. PowerSSO-12 tube shipment (no suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 36. PowerSSO-12 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
29/31
Revision history
6
VN5050J-E
Revision history
Table 16.
Document revision history
Date
Revision
30-Mar-2006
1
Initial release.
2
Document reformatted and restructured.
Contents and lists of tables and figures added.
Figure 2: Configuration diagram (top view) updated: pins 1-6-712 N.C. (not connected).
Table 4: Absolute maximum ratings: EMAX entries updated.
Table 13: Electrical transient requirements :Test level values III
and IV for test pulse 5b and notes updated.
Section 3.5: Maximum demagnetization energy (VCC = 13.5V)
added.
Figure 33: Thermal fitting model of a single channel HSD in
PowerSSO-12 : note added
Table 15: PowerSSO-12™ mechanical data : slug dimensions
(X,Y) corrected
13-Sep-2007
30/31
Changes
VN5050J-E
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31/31