Preliminary VT73LVP10 TTL to Differential LVPECL Translator with Enable Applications •= PECL clock source General Description The Vaishali VT73LVP10 is a general purpose TTL (CMOS) to differential LVPECL translator, with active-LOW enable. The device operates from a single 3.3V supply. When /EN is LOW or open circuit, the device accepts an LVTTL or LVCMOS input and provides differential LVPECL outputs referenced to the positive supply rail. When /EN is HIGH, the Q output is set to the LOW state and QN output is set to the HIGH state. Features •= 700ps typical propagation delay •= 5V - tolerant inputs •= Differential LVPECL outputs •= •= Flow-through pinout ESD rating >2000V (Human Body Model) or >200V (Machine Model) •= -40 C to +85 C operating temperature range •= Available as die, 8-pin SOIC or 8 pin MSOP package o o Figure 1. Functional Block Diagram & Pin Assignment 8 pin SOIC/ MSOP NC 1 8 VDD TTL/ CMOS Q 2 LVPECL QN 3 /EN 4 7 D 6 NC 5 GND 100kΩ Page 1 MDST-0014-07 www.vaishali.com Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063 2002-01-15 VT73LVP10 Preliminary Table 1. Pin Description Type Pin # /EN Name CMOS/TTL Active LOW enable input, with pull-down resistor Description I 4* Q PECL data output O 2 QN PECL complementary data output O 3 VDD Connect to 3.3V P 8 D CMOS/TTL data input I 7 GND Connect to ground P 5 Legend: I = Input O = Output P = Power supply connection * = Internal 100kΩ pull-down resistor Table 2. Absolute Maximum Ratings Symbol Parameter Conditions VDD Supply voltage Referenced to GND VIN Input voltage Referenced to GND IOUT Output current in LOW state TSTG Storage temperature Min Typ Max Units 6 V 6 V 50 mA -0.5 -65 150 o C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3. Operating Conditions Symbol VDD Parameter Conditions Power Supply Voltage Min 3.0 -40 Typ Max 3.6 85 Units V o TA Ambient Temperature VIH Input HIGH Voltage D, /EN inputs VIL Input LOW Voltage D, /EN inputs tRin Input slew rate 10% to 90% (L → H) 1 V/ns tFin Input slew rate 90% to 10% (H → L) 1 V/ns 2.0 C V 0.8 V Page 2 MDST-0014-06 www.vaishali.com Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063 2002-01-15 VT73LVP10 Preliminary Table 4. DC Characteristics o o TA = -40 C to +85 C, VDD = 3.0V to 3.6V unless otherwise stated below. Symbol IIH Parameter Conditions Input HIGH Current IIL VIN = 2.7V Input LOW Current VIK VIN = 0.5V Input Clamp Diode Voltage VOH Output HIGH Voltage Max Units D input 1 µA /EN input 50 D input 1 /EN input 20 Output LOW Voltage o -40 C VDD = 3.3V (1, 2) Power Supply Current µA -1.2 V 2275 2375 2475 mV o 25 C 2200 2300 2400 mV o 2125 2225 2325 mV o -40 C 1350 1450 1550 mV o VDD = 3.3V 25 C 1400 1500 1600 mV o 1450 1550 1650 mV 85 C IDD Typ IIN = -18mA (1, 2) 85 C VOL Min (2) 33 mA Notes:1.The VT73LVP10 is designed to meet these specifications after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board. 2. Q and QN outputs are loaded with 50 ohms to VDD-2 volts. Table 5. AC Characteristics o o TA = -40 C to +85 C, VDD = 3.0V to 3.6V Symbol Typ Max Units Propagation Delay (1) 0.7 1.2 ns tPHL Propagation Delay (1) 0.7 1.2 ns tPLH Propagation Delay /EN to Q, QN 1.5 2.5 ns tPHL Propagation Delay /EN to Q, QN 1.5 2.5 ns tr/tf Output Rise/Fall time 20%-80% 0.25 0.35 0.7 ns fMAX Maximum Input Frequency LVTTL or LVCMOS input 170 MHz 750mV peak-to-peak sine wave (AC coupled) 400 MHz tPLH fMAX Parameter Conditions Maximum Input Frequency (2) Min Notes: 1. Q and QN outputs are loaded with 50 ohms to VDD-2 volts. 2. Measured using a 750mV peak-to-peak, 50% duty cycle clock source. Ordering Information Part Number VT73LVP10S1 VT73LVP10S1X VT73LVP10M VT73LVP10MX VT73LVP10/D VT73LVP10/DW Marking VT73LVP10S1 VT73LVP10S1 VT73LVP10M VT73LVP10M Shipping/Packaging Tubes Tape & Reel Tubes Tape & Reel Dice in waffle-pak Dice in wafer form No. of Pins 8 8 8 8 Package SOIC SOIC MSOP MSOP Temperature -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Page 3 MDST-0014-06 www.vaishali.com Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063 2002-01-15