W48S87-72 Desktop/Notebook Frequency Generator Features • Maximized EMI suppression using Cypress’s Spread Spectrum technology • ±0.5% Spread Spectrum clocking • Equivalent to the W48S67-72 with Spread Spectrum for Tilamook, MMO, and Deschutes processors • Generates system clocks for CPU, IOAPIC, SDRAM, PCI, USB plus 14.318-MHz (REF0:1) • Serial data interface (SDATA, SCLOCK inputs) provides additional CPU/PCI clock frequency selections, individual output clock disabling and other functions • MODE input pin selects optional power management input control pins (reconfigures pins 26 and 27) • Two fixed outputs separately selectable as 24-MHz or 48-MHz (default = 48-MHz) • VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% • Uses external 14.318-MHz crystal • Available in 48-pin SSOP (300 mils) • 10Ω CPU output impedance Table 1. Pin Selectable Frequency[1] Block Diagram 60/66_SEL CPU, SDRAM Clocks (MHz) PCI Clocks (MHz) 0 60 30 1 66.8 33.4 Pin Configuration VDDQ3 REF0 X1 X2 REF1 XTAL OSC PLL Ref Freq VDDQ2 IOAPIC CPU0 CPU1 CPU_STOP# MODE CPU2 Stop Output Control I/O Control CPU3 VDDQ3 SDRAM0 SDRAM1 SDRAM2 60/66_SEL SDRAM3 PLL 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W48S87-72 VDDQ2 REF1 REF0 GND X1 X2 MODE VDDQ3 PCI_F PCI0 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 GND 60/66_SEL SDATA SCLOCK VDDQ3 48/24MHZ 48/24MHZ GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 CPU2.5# VDDQ2 IOAPIC PWR_DWN# GND CPU0 CPU1 VDDQ2 CPU2 CPU3 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6/CPU_STOP# SDRAM7/PCI_STOP# VDDQ3 SDRAM4 SDRAM5 ÷2 SDRAM6 SDRAM7 PCI_F PCI0 Stop Output Control PCI1 PCI2 Power Down Control PWR_DWN# PCI3 PCI4 PCI5 PLL2 48/24MHZ 48/24MHZ Note: 1. Additional frequency selections provided by serial data interface; refer to Table 5 on page 8. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 August 4, 2000 rev. *A W48S87-72 Pin Definitions Pin No. Pin Type CPU0:3 42, 41, 39, 38 O CPU Outputs 0 through 3: These four CPU outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI0:5 9, 11, 12, 13, 14, 16 O PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. PCI_F 8 O Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. 36, 35, 33, 32, 30, 29 O SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run synchronous to the CPU clock outputs. Output voltage swing is controlled by voltage applied to VDDQ3. 27 I/O SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 6. Pin Name SDRAM0:5 SDRAM6/ CPU_STOP# Pin Description Regarding use as a CPU_STOP# input: When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 are started beginning with a full clock cycle (2–3 CPU clock latency). Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM7/ PCI_STOP# 26 I/O SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 7. PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5 are started beginning with a full clock cycle. Clock latency provides one PCI_F rising edge of PCI clock following PCI_STOP# state change. Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. 45 O I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 22, 23 O 48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following device power-up. Either or both can be changed to 24 MHz through use of the serial data interface (Byte 0, bits 2 and 3). Output voltage swing is controlled by voltage applied to VDDQ3 2, 1 O Fixed 14.318-MHz Outputs 0 through 1: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. REF0 is stronger than REF1 and should be used for driving ISA slots. CPU_2.5# 47 I 60/66_SEL 18 I Set to logic 0 for V DDQ2 = 2.5V (0 to 2.5V CPU output swing). 60- or 66-MHz Input Selection: Selects power-up default CPU clock frequency as shown in Table 1 on page 1 (also determines SDRAM and PCI clock frequency selections). Can be used to change CPU clock frequency while device is in operation if serial data port bits 0–2 of Byte 7 are logic 1 (default powerup condition). X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. IOAPIC 48/24MHz REF0:1 2 W48S87-72 Pin Definitions (continued) Pin No. Pin Type PWR_DWN# 44 I Power-Down Control: When this input is LOW, the device goes into a lowpower standby condition. All outputs are actively held LOW while in powerdown. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing a full clock cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). MODE 6 I Mode Control: This input selects the function of device pin 26 (SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to description for those pins. SDATA 19 I/O SCLOCK 20 I Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data Interface section that follows. VDDQ3 7, 15, 21, 25 28, 34, 48 P Power Connection: Power supply for PCI0:5, REF0:1, and 48/24MHz output buffers. Connected to 3.3V supply. VDDQ2 46, 40 P Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Connected to 2.5V supply. 3, 10, 17, 24, 31, 37, 43 G Ground Connection: Connect all ground pins to the common system ground plane. Pin Name GND Pin Description Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface section that follows. 3 W48S87-72 The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is ±0.5% of the center frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum Generator The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As depicted in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1–0 in data byte 0 of the I2C data stream. Refer to Table 4 for more details. dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. G%GLY (0, 5HGXFWLRQ 7\SLFDO &ORFN $PSOLWXGH G% 66)7* 6SUHDG 6SHFWUXP (QDEOHG 66 )UHTXHQF\ 6SDQ 0+] 66 1RQ 6SUHDG 6SHFWUXP )UHTXHQF\ 6SDQ 0+] 66 Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN. (–0.5%) Figure 2. Typical Modulation Profile 4 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX (+.0.5%) W48S87-72 of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Serial Data Interface The W48S87-72 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W48S87-72 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is writeonly (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs Operation Data is written to the W48S87-72 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3. Table 2. Serial Data Interface Control Functions Summary Control Function Description Common Application Clock Output Disable Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI slot. 48-/24-MHz Clock Output Frequency Selection 48-/24-MHz clock outputs can be set to 48 MHz or 24 MHz. Provides flexibility in Super I/O and USB device selection. CPU Clock Frequency Selection Provides CPU/PCI frequency selections beyond the 60- and 66.6-MHz selections that are provided by the SEL60/66 input pin. Frequency is changed in a smooth and controlled fashion. For alternate CPU devices, and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing. Test Mode All clock outputs toggle in relation with X1 input, internal PLL is bypassed. Refer to Table 4. Production PCB testing. (Reserved) Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0. Table 3. Byte Writing Sequence Byte Sequence Byte Name Bit Sequence Byte Description 1 Slave Address 11010010 Commands the W48S87-72 to accept the bits in Data Bytes 0–7 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W48S87-72 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W48S87-72, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W48S87-72, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 Refer to Table 4 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 The data bits in Data Bytes 0–7 set internal W48S87-72 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map. 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 11 Data Byte 7 5 W48S87-72 Writing Data Bytes 7. Table 4 gives the bit formats for registers located in Data Bytes 0–7. Each bit in the data bytes control a particular device function except for the “reserved” bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 0, bits 1 and 0. Table 4. Data Bytes 0–7 Serial Configuration Map Affected Pin Bit(s) Pin No. Bit Control Pin Name Control Function 0 1 Default Data Byte 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) Refer to Table 5 0 5 -- -- SEL_4 Refer to Table 5 0 4 -- -- SEL_3 Refer to Table 5 0 3 23 48/24MHZ 48-/24-MHz Clock Output Frequency Selection 24 MHz 48 MHz 2 22 48/24MHZ 48-/24-MHz Clock Output Frequency Selection 24 MHz 48 MHz 1–0 -- -- 7 23 48/24MHZ Clock Output Disable Low Active 1 6 22 48/24MHZ Clock Output Disable Low Active 1 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 38 CPU3 Clock Output Disable Low Active 1 2 39 CPU2 Clock Output Disable Low Active 1 1 41 CPU1 Clock Output Disable Low Active 1 0 42 CPU0 Clock Output Disable Low Active 1 -- -- -- -- 0 6 8 PCI_F Clock Output Disable Low Active 1 5 16 PCI5 Clock Output Disable Low Active 1 4 14 PCI4 Clock Output Disable Low Active 1 3 13 PCI3 Clock Output Disable Low Active 1 2 12 PCI2 Clock Output Disable Low Active 1 1 11 PCI1 Clock Output Disable Low Active 1 0 9 PCI0 Clock Output Disable Low Active 1 7 26 SDRAM7 Clock Output Disable Low Active 1 6 27 SDRAM6 Clock Output Disable Low Active 1 5 29 SDRAM5 Clock Output Disable Low Active 1 4 30 SDRAM4 Clock Output Disable Low Active 1 3 32 SDRAM3 Clock Output Disable Low Active 1 2 33 SDRAM2 Clock Output Disable Low Active 1 1 35 SDRAM1 Clock Output Disable Low Active 1 0 36 SDRAM0 Clock Output Disable Low Active 1 Bit 1 0 0 1 1 Bit 0 0 1 0 1 0 0 00 Function (See Table 6 for function details) Normal Operation Test Mode Spread Spectrum On All Outputs Three-stated Data Byte 1 Data Byte 2 7 (Reserved) Data Byte 3 6 W48S87-72 Table 4. Data Bytes 0–7 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. Bit Control Pin Name Control Function 0 1 Default Data Byte 4 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 45 IOAPIC Low Active 1 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 1 REF1 Clock Output Disable Low Active 1 0 2 REF0 Clock Output Disable Low Active 1 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- SEL_2 Refer to Table 5 1 1 -- -- SEL_1 Refer to Table 5 1 0 -- -- SEL_0 Refer to Table 5 1 Data Byte 5 Clock Output Disable Data Byte 6 Data Byte 7 7 W48S87-72 Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Date Byte 0 Date Byte 7 Bit 5 SEL_4 Bit 4 SEL_3 60/66_SEL (Pin 18) Bit 2 SEL_2 BIT 1 SEL_1 0 0 X 0 0 0 0 X 0 0 0 0 X 0 1 0 0 X 0 0 0 X 0 0 X 0 0 0 BIT 0 SEL_0 CPU0:3 SDRAM0:7 PCI_F PCI0:5 Spread Spectrum% 0 75.0 CPU/2 ±0.5 1 75.0 32 ±0.5 0 83.31 32 ±0.5 1 1 33.41 CPU/2 ±0.5 1 0 0 50.11 CPU/2 ±0.5 1 0 1 68.52 CPU/2 ±0.5 X 1 1 0 60.0 CPU/2 ±0.5 0 0 1 1 1 60.0 CPU/2 ±0.5 0 0 1 1 1 1 66.82 CPU/2 ±0.5 0 1 0 X X X 60.0 CPU/2 ±0.5 0 1 1 X X X 66.6 CPU/2 –0.5 1 0 0 X X X 60.0 CPU/2 ±0.5 1 0 1 X X X 66.6 CPU/2 –0.5 1 1 0 X X X 60.0 CPU/2 ±0.5 1 1 1 X X X 66.6 CPU/2 –0.5 Table 6. Select Function for Data Byte 0, Bits 0:1 Input Conditions Data Byte 0 Output Conditions Bit 1 Bit 0 CPU0:3, SRAM0:7 PCI_F, PCI0:5 REF0:2, IOAPIC 48/24MHZ Normal Operation 0 0 Note 2 Note 2 14.318 MHz 48 or 24 MHz Test Mode 0 1 X1/2 X1/4 X1 Note 3 Spread Spectrum On 1 0 Note 2 Note 2 14.318 MHz 48 or 24 MHz Three-state 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Function Notes: 2. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5. 3. In Test Mode, the 48-/24-MHz clock outputs are: - X1/2 if 48-MHz is selected. - X1/4 if 24-MHz is selected. 8 W48S87-72 Although the W48S87-72 is a receive-only device (no data write-back capability), it does transmit an “acknowledge” data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. How To Use the Serial Data Interface Electrical Requirements Figure 3 illustrates electrical characteristics for the serial interface bus used with the W48S87-72. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistors on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. 9'' 9'' a NΩ a NΩ 6(5,$/ %86 '$7$ /,1( 6(5,$/ %86 &/2&. /,1( 6'&/. &/2&. ,1 &/2&. 287 6'$7$ 6&/2&. '$7$ ,1 1 '$7$ 287 &/2&. ,1 '$7$ ,1 1 '$7$ 287 &+,3 6(7 &/2&. '(9,&( 6(5,$/ %86 0$67(5 75$160,77(5 6(5,$/ %86 6/$9( 5(&(,9(5 Figure 3. Serial Interface Bus Electrical Characteristics 9 6'$7$ 1 W48S87-72 Signaling Requirements Sending Data to the W48S87-72 As shown in Figure 4, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition). A write sequence is initiated by a “start bit” as shown in Figure 5. A “stop bit” signifies that a transmission has ended. As stated previously, the W48S87-72 sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 6. 6'$7$ 6&/2&. 9DOLG 'DWD %LW &KDQJH RI 'DWD $OORZHG Figure 4. Serial Data Bus Valid Data Bit 6'$7$ 6&/2&. 6WDUW %LW 6WRS %LW Figure 5. Serial Data Bus Start and Stop Bit 10 Figure 6. Serial Data Bus Write Sequence 6LJQDOLQJ IURP 6\ VWHP &RUH /RJLF 6WDUW &RQGLWLRQ 6WRS &RQGLWLRQ 6ODYH $GGUHVV )LUVW %\ WH &RPPDQG &RGH 6HFRQG %\WH 6'$7$ 06% /6% 6&/2&. %\ WH &RXQW 7KLUG %\WH 06% $ /6% /DVW 'DWD %\ WH /DVW %\WH 06% $ 06% /6% $ 6'$7$ $FNQRZOHGJPHQW %LW IURP &ORFN 'HY LFH 6LJQDOLQJ E\ &ORFN 'HYLFH 11 W W 6&/2&. W /2: 67+' W W W 5 +,*+ W ) '68 W '+' W 63) 63 W 6368 W 67+' W 6368 W48S87-72 Figure 7. Serial Data Bus Timing Diagram 6'$7$ W48S87-72 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 2 (min.) kV TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias ESDPROT Input ESD Protection DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V) fXTL = 14.31818 MHz, VDDQ2 = 2.5±5% Parameter Description Test Condition Min. Typ. Max. Unit 120 150 200 mA 50 mA 0.8 V Supply Current IDDQ3 Supply Current (3.3V) CPUCLK =66.8 MHz Outputs Loaded[4] IDDQ2 Supply Current (2.5V) CPUCLK =66.8 MHz Outputs Loaded[4] Logic Inputs VIL Input Low Voltage VIH Input High Voltage IIL IIH 2.0 V [5] 10 µA [5] 10 µA 50 mV Input Low Current Input High Current Clock Outputs VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 V VOH Output High Voltage (CPU, IOAPIC) IOH = –1 mA 2.2 V IOL Output Low Current CPU0:3 VOL = 1.25V 155 mA SDRAM0:7 VOL = 1.5V 100 mA PCI_F, PCI0:5 VOL = 1.5V 95 mA IOAPIC VOL = 1.25V 85 mA REF0 VOL = 1.5V 75 mA REF1 VOL = 1.5V 60 mA 48/24MHZ VOL = 1.5V 60 mA CPU0:3 VOL = 1.25V 125 mA SDRAM0:7 VOL = 1.5V 95 mA PCI_F, PCI0:5 VOL = 1.5V 100 mA IOH Output High Current IOAPIC VOL = 1.25V 80 mA REF0 VOL = 1.5V 80 mA REF1 VOL = 1.5V 65 mA 48/24MHZ VOL = 1.5V 60 mA Notes: 4. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 5. W48S87-72 logic inputs have internal pull-up devices. (Not CMOS level.) 12 W48S87-72 DC Electrical Characteristics: (continued) TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V) fXTL = 14.31818 MHz, VDDQ2 = 2.5±5% Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH X1 Input Threshold Voltage[6] CLOAD Load Capacitance, Imposed on External Crystal[7] CIN,X1 X1 Input Capacitance[8] VDD = 3.3V Pin X2 unconnected 1.65 V 14 pF 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH 0.3VDD V Except X1 and X2 5 pF Serial Input Port VIL Input Low Voltage VDD = 3.3V VIH Input High Voltage VDD = 3.3V IIL Input Low Current No internal pull-up/down on SCLOCK 10 10 µA IIH Input High Current No internal pull-up/down on SCLOCK 10 10 µA IOL Sink Current into SDATA or SCLOCK, Open Drain N-Channel Device On IOL = 0.3VDD 10 15 mA CIN Input Capacitance of SDATA and SCLOCK 5 10 pF CSDATA Total Capacitance of SDATA Bus 400 pF CSCLOCK Total Capacitance of SCLOCK Bus 400 pF 0.4 0.7VDD 5 2.4 V Notes: 6. X1 input threshold voltage (typical) is VDDQ3 /2. 7. The W48S87-72 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 13 W48S87-72 AC Electrical Characteristics TA = 0°C to +70°C, VDD = VDDQ3 = 3.3V±5% (3.135–3.465V) fXTL = 14.31818 MHz, VDDQ2 = 2.5±5% AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF) CPU = 66.8 MHz Parameter Description Test Condition/Comments Min. CPU = 60 MHz Typ. Max. Min. 15 Typ. Max. Unit tP Period Measured on rising edge at 1.5V 16.7 f Frequency, Actual Determined by PLL divider ratio tH High Time Duration of clock cycle above 2.4V tL Low Time Duration of clock cycle below 0.4V tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 250 250 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 66.8 ns 59.876 5.2 MH z 6 5 ns 5.8 52 ns 52 Ω 10 10 CPU = 66.8 MHz CPU = 60 MHz SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Min. tP Period Measured on rising edge at 1.5V f Frequency, Actual Determined by PLL divider ratio tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V tSK CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. 500 500 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 14 15 Typ. Max. Unit 16.7 66.8 50 ns 59.876 50 250 100 16 MHz 100 16 ps Ω W48S87-72 PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 66.8 MHz Parameter Description Test Condition/Comments Min. CPU = 60 MHz Typ. Max. Min. 30 Typ. Max. Unit tP Period Measured on rising edge at 1.5V 33.3 f Frequency, Actual Determined by PLL divider ratio tH High Time Duration of clock cycle above 2.4V 12 tL Low Time Duration of clock cycle below 0.4V 12 tR Output Rise Edge Rate 1 4 1 4 V/ns tF Output Fall Edge Rate 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.5V 250 250 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 33.4 45 ns 29.938 MHz 13.3 ns 13.3 51 1 4 ns 51 1 3 30 Ω 30 I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter Description Test Condition/Comments Min. Frequency generated by crystal oscillator Typ. Max. f Frequency, Actual tR Output Rise Edge Rate 1 4 V/ns tF Output Fall Edge Rate 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 14.31818 Unit 45 52.5 15 MHz Ω W48S87-72 REF0 Clock Output (Lump Capacitance Test Load = 45 pF) CPU = 60/66.8 MHz Parameter Description Test Condition/Comments Min. Typ. Max. 14.31818 Unit f Frequency, Actual Frequency generated by crystal oscillator tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 fST Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. MHz 50 55 % 1.5 ms Ω 16 REF1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter Description Test Condition/Comments f Frequency, Actual tR Output Rise Edge Rate tF Output Fall Edge Rate tD Duty Cycle Measured on rising and falling edge at 1.5V fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Min. Frequency generated by crystal oscillator Typ. Max. 14.31818 Unit MHz 0.5 2 V/ns 0.5 2 V/ns 45 55 % 1.5 ms Ω 40 48/24MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 60/66.8 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see n/m below) fD Deviation from 48 MHz (48.008 – 48)/48 m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) tR Output Rise Edge Rate 0.5 2 V/ns tF Output Fall Edge Rate 0.5 2 V/ns tD Duty Cycle 55 % fST Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Measured on rising and falling edge at 1.5V Average value during switching transition. Used for determining series termination value. 16 48.008/24.004 MHz +167 ppm 57/17 45 50 40 Ω W48S87-72 Serial Input Port Parameter Description Test Condition Normal Mode Min. 0 Typ. Max. Unit 100 kHz fSCLOCK SCLOCK Frequency tSTHD Start Hold Time 4.0 µs tLOW SCLOCK Low Time 4.7 µs tHIGH SCLOCK High Time 4.0 µs tDSU Data Set-up Time tDHD Data Hold Time (Transmitter should provide a 300-ns hold time to ensure proper timing at the receiver.) tR Rise Time, SDATA and SCLOCK From 0.3VDD to 0.7VDD 1000 ns tF Fall Time, SDATA and SCLOCK From 0.7VDD to 0.3VDD 300 ns tSTSU Stop Set-up Time 4.0 µs tSPF Bus Free Time between Stop and Start Condition 4.7 µs tSP Allowable Noise Spike Pulse Width W48S87 ns 0 ns 50 Ordering Information Ordering Code 250 Freq. Mask Code Package Name 72 H X Package Type 48-pin SSOP (300 mils) 48-pin TSSOP Document #: 38-00855-*A 17 ns W48S87-72 Package Diagrams 48-Pin Small Shrink Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 18 W48S87-72 Package Diagrams (continued) 48-Pin Thin Shrink Small Outline Package (TSSOP) 12 11 10 9 8 7 6 5 4 3 2 1 H H THIS TABLE IN MILLIMETERS S Y M B O L G A A1 A2 b b1 C C1 D E F e H L N E C OC COMMON DIMENSIONS NOM. MIN. MAX. 0.10 0.05 0.90 0.85 0.17 0.17 0.20 0.090 0.090 0.127 SEE VARIATIONS 6.00 6.10 0.50 BSC 7.95 8.10 0.50 0.60 SEE VARIATIONS O T E NOTE VARIATIONS MIN. 4 D NOM. MAX. MIN. S NOM. AA AB 12.40 13.90 12.50 14.00 12.60 14.10 0.37 0.12 0.50 0.25 6 N MAX. G 48 56 8 8 F 4 4 6.20 8.25 0.75 4° 0° N 1.10 0.15 0.95 0.27 0.23 0.200 0.160 5 6 E 8° THIS TABLE IN INCHES D D S Y M B O L A A1 A2 b b1 C C1 D E C B e H L N C OC COMMON DIMENSIONS MIN. MAX. NOM. .002 .004 .0354 .0335 .0067 .0067 .0078 .0035 .0035 .0050 SEE VARIATIONS .236 .240 .0197 BSC .313 .319 .020 .024 SEE VARIATIONS 0° .0433 .006 .0374 .011 .0090 .0078 .0063 .244 .325 .030 N O T E NOTE VARIATIONS AA AB MIN. 4 D NOM. MAX. MIN. S NOM. .488 .547 .492 .551 .496 .555 .0146 .0047 .0197 .0098 6 N MAX. 48 56 C 8 8 4 4 B 5 6 8° 4° TITLE P AC KA G E O UTLINE , 6 .10 mm (.2 40 ") B O DY, TSS O P, 0.50 mm L EA D P ITC H A SIZE D WG. N O. 12 11 10 9 8 7 6 5 4 3 8/1 S HE ET 2 A R EV . 34389 A1 SC AL E 02 2 OF 2 1 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.