WE32K32-XXX HI-RELIABILITY PRODUCT 32Kx32 EEPROM MODULE, SMD 5962-94614 FEATURES ■ Access Times of 80*, 90, 120, 150ns ■ Commercial, Industrial and Military Temperature Ranges ■ MIL-STD-883 Compliant Devices Available ■ Automatic Page Write Operation ■ Packaging: ■ Page Write Cycle Time: 10ms Max ■ Data Polling for End of Write Detection • 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square, 3.56mm (0.140") height (Package 510). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2) ■ Hardware and Software Data Protection ■ TTL Compatible Inputs and Outputs • 66-pin, PGA Type, 1.075" square, Hermetic Ceramic HIP (Package 400) ■ 5 Volt Power Supply ■ Data Retention at 25°C, 10 Years ■ Low Power CMOS, 10mA Standby Typical ■ Write Endurance, 10,000 Cycles ■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation ■ Organized as 32Kx32; User Configurable 64Kx16 or 128Kx8 * 80ns speed is not fully characterized and is subject to change or cancellation without notice. FIG. 1 PIN CONFIGURATION FOR WE32K32N-XH1X TOP VIEW 1 12 23 PIN DESCRIPTION 34 45 56 I/O0-31 Data Inputs/Outputs I/O8 WE2 I/O15 I/O24 VCC I/O31 A0-14 Address Inputs I/O9 CS2 I/O14 I/O25 CS4 I/O30 WE1-4 Write Enables CS1-4 Chip Selects OE Output Enable VCC Power Supply I/O10 GND I/O13 I/O26 WE4 I/O29 A13 I/O11 I/O12 A6 I/O27 I/O28 A14 A10 OE A7 A3 A0 NC A11 NC NC A4 A1 NC A12 WE1 A8 A5 A2 NC VCC I/O7 A9 WE3 I/O23 I/O0 CS1 I/O6 I/O16 CS3 I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 11 22 33 44 55 Ground NC Not Connected BLOCK DIAGRAM W E 1 CS 1 W E 2 CS 2 W E 3 CS 3 W E 4 CS 4 OE A0-14 32K x 8 66 8 I/O0-7 June 1999 Rev. 2 GND 1 32K x 8 8 I/O8-15 32K x 8 8 I/O16-23 32K x 8 8 I/O24-31 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 WE32K32-XXX FIG. 2 PIN CONFIGURATION FOR WE32K32-XG2UX TOP VIEW NC A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE1 A6 A7 A8 A9 A10 VCC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 PIN DESCRIPTION I/O0-31 Data Inputs/Outputs 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 A0-14 Address Inputs WE1-4 Write Enables CS1-4 Chip Selects 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 OE Output Enable VCC Power Supply GND Ground NC Not Connected NC NC NC WE4 WE3 NC WE2 OE CS2 NC CS1 NC A14 A13 A12 A11 VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 BLOCK DIAGRAM W E 1 CS 1 W E 3 CS 3 W E 2 CS 2 W E 4 CS 4 OE A0-14 0.940" 32K x 8 8 I/O0-7 32K x 8 32K x 8 8 8 I/O8-15 I/O16-23 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 32K x 8 8 I/O24-31 2 The White 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form. WE32K32-XXX TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Symbol Operating Temperature Unit -55 to +125 °C T STG -65 to +150 °C VG -0.6 to +6.25 V -0.6 to +13.5 V TA Storage Temperature Signal Voltage Relative to GND Voltage on OE and A9 CS H L L X X X NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. OE X L H H X L WE X H L X H X Symbol Condition Max Unit C AD COE V IN = 0V, f = 1.0MHz 50 pF CS1-4 Capacitance CCS V IN = 0V, f = 1.0MHz 20 pF °C WE1-4 Capacitance C WE V IN = 0V, f = 1.0MHz 20 pF °C Data I/O Capacitance CI/O V IN = 0V, f = 1.0MHz 20 pF Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input High Voltage V IH 2.0 V CC + 0.3 V Input Low Voltage V IL -0.5 +0.8 V Operating Temp. (Mil.) Operating Temp. (Ind.) TA -55 +125 -40 TA +85 Data I/O High Z Data Out Data In High Z/Data Out CAPACITANCE (TA = 25° C) RECOMMENDED OPERATING CONDITIONS Parameter Mode Standby Read Write Out Disable Write Inhibit Parameter Address Input Capacitance OE Capacitance This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55°C to +125°C) Parameter Symbol Input Leakage Current ILI Conditions -80 Min Max 10 VCC = 5.5, VIN = GND to VCC -90 Min Max 10 -120 Min Max 10 -150 Units Min Max 10 µA Output Leakage Current ILO x 32 CS = VIH, OE = VIH, VOUT = GND to VCC 10 10 10 10 µA Operating Supply Current x 32 Mode ICC x 32 CS = VIL, OE = VIH, f = 5MHz 320 250 200 150 mA Standby Current ISB CS = VIH, OE = VIH, f = 5MHz 2.5 2.5 2.5 2.5 mA Output Low Voltage VOL IOL = 2.1mA, VCC = 4.5V 0.45 0.45 0.45 0.45 Output High Voltage VOH IOH = -400µA, VCC = 4.5V 2.4 2.4 2.4 2.4 V V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V FIG. 3 AC TEST CONDITIONS AC TEST CIRCUIT Parameter I OL Current Source VZ D.U.T. ≈ 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source 3 Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. V Z is typically the midpoint of VOH and V OL. I OL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 WE32K32-XXX WRITE A write cycle is initiated when OE is high and a low pulse is on WE or CS with CS or WE low. The address is latched on the falling edge of CS or WE whichever occurs last. The data is latched by the rising edge of CS or WE, whichever occurs first. A byte write operation will automatically continue to completion. WRITE CYCLE TIMING Figures 4 and 5 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS or WE goes low. The WE line transition from high to low also initiates an internal 150 µsec delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the 150 µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. AC WRITE CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55°C to +125°C) WRITE CYCLE Write Cycle Parameter -80 Symbol Min -90 Max Min 10 -120 Max Min 10 -150 Max Min 10 Max Unit 10 ms Write Cycle Time, TYP = 6ms tWC Address Set-up Time tAS 0 0 30 30 ns Write Pulse Width (WE or CS) tWP 100 100 150 150 ns Chip Select Set-up Time tCS 0 0 0 0 ns Address Hold Time tAH 50 50 100 100 ns Data Hold Time tDH 0 0 10 10 ns Chip Select Hold Time tCSH 0 0 0 0 ns Data Set-up Time tDS 50 50 100 100 ns Write Pulse Width High tWPH 50 50 50 50 ns Output Enable Set-up Time tOES 10 10 10 10 ns Output Enable Hold Time tOEH 10 10 10 10 ns White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 4 WE32K32-XXX FIG. 4 WRITE WAVEFORMS WE CONTROLLED t WC OE t OEH t OES ADDRESS t AS CS 1-4 tCSH t AH t CS WE 1-4 t WP t WPH t DS t DH DATA IN FIG. 5 WRITE WAVEFORMS CS CONTROLLED t WC OE t OEH t OES ADDRESS t AS tCSH t AH WE1 - 4 t CS CS1 - 4 t WP t WPH t DS t DH DATA IN 5 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 WE32K32-XXX READ The WE32K32-XHX stores data at the memory location determined by the address pins. When CS and OE are low and WE is high, this data is present on the outputs. When CS and OE are high, the outputs are in a high impedance state. This 2 line control prevents bus contention. AC READ CHARACTERISTICS (See Figure 6) (VCC = 5.0V, GND = 0V, TA = -55°C to +125°C) READ CYCLE Symbol Parameter -80 Min -90 Max Min 80 -120 Max 90 Min -150 Max Unit Max Read Cycle Time t RC Address Access Time t ACC 80 90 120 150 ns CS Access Time t ACS 80 90 120 150 ns Output Hold from Add. Change, OE or CS t OH Output Enable to Output Valid t OE 40 50 85 85 ns Chip Select or OE to Output in High Z t DF 40 50 70 70 ns 0 120 Min 0 150 0 ns 0 ns FIG. 6 READ WAVEFORMS t RC ADDRESS VALID ADDRESS CS t ACS t OE OE NOTES: 1. OE may be delayed up to tACS - tOE after the falling edge of CS without impact on tOE or by tACC - tOE after an address change without impact on tACC . 2. t CHZ , tOHZ are specified from OE or CS whichever occurs first (C L = 5pF). 3. All I/O transitions are measured ±200 mV from steady state with loading as specified in "Load Test Circuits." White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 t DF t ACC HIGH Z OUTPUT 6 t OH OUTPUT VALID WE32K32-XXX DATA POLLING The WE32K32-XXX offers a data polling feature which allows a faster method of writing to the device. Figure 7 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7 (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. DATA POLLING CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55°C to +125°C) Parameter Symbol Min Data Hold Time tDH 10 OE Hold Time tOEH 10 OE To Output Valid tOE Write Recovery Time tWR Max Unit ns ns 100 0 ns ns FIG. 7 DATA POLLING WAVEFORMS WE1-4 CS1-4 t OEH OE I/O7 t OE t DH HIGH Z t WR ADDRESS 7 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 WE32K32-XXX PAGE WRITE OPERATION The usual procedure is to increment the least significant address lines from A0 through A5 at each write cycle. In this manner a page of up to 64 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. The WE32K32-XXX has a page write operation that allows one to 64 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150µs or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. After the 150µs time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. PAGE WRITE CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55°C to +125°C) PAGE MODE WRITE CHARACTERISTICS Parameter Symbol -80 Min -90 Max Min -120 Max -150 Max tWC tDS 50 50 100 100 Data Hold Time t DH 0 0 10 10 ns Write Pulse Width tWP 100 100 150 150 ns tBLC tWPH 150 10 Unit Max Data Set-up Time Write Pulse Width High 10 Min Write Cycle Time, TYP = 6ms Byte Load Cycle Time 10 Min 150 50 50 10 150 50 ns 150 50 OE CS t WP t BLC t WPH WE t DS t DH ADDRESS (1) VALID ADDRESS t WC VALID DATA DATA BYTE 0 BYTE 1 NOTE: 1. Decoded Address Lines must be valid for the duration of the write. White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 8 BYTE 2 BYTE 3 BYTE n µs ns FIG. 8 PAGE WRITE WAVEFORMS ms BYTE n + 1 WE32K32-XXX FIG. 9 SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1) LOAD DATA AA TO ADDRESS 5555 ➞ LOAD DATA 55 TO ADDRESS 2AAA ➞ WRITES ENABLED(2) ➞ LOAD DATA A0 TO ADDRESS 5555 ➞ LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE NOTES: 1. Data Format: D 7 - D 0 (Hex); Address Format: A 14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data may be loaded. 9 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 WE32K32-XXX SOFTWARE DATA PROTECTION FIG. 10 A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WE32K32-XXX has the feature disabled. Write access to the device is unrestricted. SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM(1) To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. LOAD DATA AA TO ADDRESS 5555 ➞ LOAD DATA 55 TO ADDRESS 2AAA ➞ LOAD DATA 80 TO ADDRESS 5555 ➞ Each 32KByte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. LOAD DATA AA TO ADDRESS 5555 ➞ LOAD DATA 55 TO ADDRESS 2AAA ➞ HARDWARE DATA PROTECTION These features protect against inadvertent writes to the WE32K32-XXX. These are included to improve reliability during normal operation: LOAD DATA 20 TO ADDRESS 5555 (3) ➞ EXIT DATA PROTECT STATE a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5msec typical before allowing write cycles. LOAD DATA XX TO ANY ADDRESS(4) ➞ (3) b) VCC sense While below 3.8V typical write cycles are inhibited. LOAD LAST BYTE TO LAST ADDRESS c) Write inhibiting Holding OE low and either CS or WE high inhibits write cycles. d) Noise filter Pulses of <8ns (typ) on WE or CS will not initiate a write cycle. NOTES: 1. Data Format: D 7 - D0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data may be loaded. White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 10 WE32K32-XXX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1) 27.3 (1.075) ± 0.25 (0.010) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 4.34 (0.171) MAX 3.81 (0.150) ± 0.13 (0.005) 1.42 (0.056) ± 0.13 (0.005) 0.76 (0.030) ± 0.13 (0.005) 2.54 (0.100) TYP 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) ± 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 11 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 WE32K32-XXX PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U) 25.15 (0.990) ± 0.25 (0.010) SQ 3.51 (0.140) MAX 22.36 (0.880) ± 0.25 (0.010) SQ 0.25 (0.010) ± 0.10 (0.002) 0.25 (0.010) REF Pin 1 R 0.25 (0.010) 24.0 (0.946) ± 0.25 (0.010) 0.53 (0.021) ± 0.18 (0.007) 1° / 7° 1.01 (0.040) ± 0.13 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP SEE DETAIL "A" 0.38 (0.015) ± 0.05 (0.002) 20.3 (0.800) REF The White 68 lead G2U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead inspection advantage of the CQFP form. 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 12 WE32K32-XXX ORDERING INFORMATION WE 32K32 X - XXX X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: Q = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE TYPE: H1 = Ceramic Hex In-line Package, HIP (Package 400) G2U = 22.4mm Ceramic Quad Flat Pack, CQFP Low Profile (Package 510) ACCESS TIME (ns) IMPROVEMENT MARK N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade ORGANIZATION, 32K x 32 User Configurable as 64Kx16 or 128Kx8 EEPROM WHITE ELECTRONIC DESIGNS CORP. DEVICE TYPE SPEED PACKAGE SMD NO. 32K x 32 EEPROM Module 150ns 66 pin HIP (H1) 5962-94614 01HXX 32K x 32 EEPROM Module 120ns 66 pin HIP (H1) 5962-94614 02HXX 32K x 32 EEPROM Module 90ns 66 pin HIP (H1) 5962-94614 03HXX 32K x 32 EEPROM Module 150ns 68 lead CQFP/J (G2U) 5962-94614 01HZX 32K x 32 EEPROM Module 120ns 68 lead CQFP/J (G2U) 5962-94614 02HZX 32K x 32 EEPROM Module 90ns 68 lead CQFP/J (G2U) 5962-94614 03HZX 13 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520