WF128K16, WF256K16-XCX5 5V FLASH MODULE PRELIMINARY * FEATURES ■ Access Times of 50, 60, 70, 90, 120 and 150ns ■ 5 Volt Programming; 5V ±10% Supply ■ 40 pin Ceramic DIP (Package 303) ■ Low Power CMOS ■ Organized as 128Kx16 and 256Kx16 ■ Embedded Erase and Program Algorithms ■ Sector Architecture ■ TTL Compatible Inputs and CMOS Outputs ■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation • 8 equal size sectors of 16KBytes each per chip • Any combination of sectors can be concurrently erased. ■ Page Program Operation and Internal Program Control Time Also supports full chip erase * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. ■ 100,000 Erase/Program Cycles Minimum (0°C to 70°C) ■ Data Retention, 10 Years at 125°C Note: Programming information available upon request. ■ Commercial, Industrial and Military Temperature Ranges FIG. 1 PIN CONFIGURATION AND BLOCK DIAGRAM TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIN DESCRIPTION VCC WE A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Inputs Data Input/Output CS1-2 Chip Selects OE Output Enable WE Write Enable VCC +5.0V Power GND Ground 7 BLOCK DIAGRAM FOR WF256K16-XCX5 I/O0-7 * CS2 for 256Kx16 and NC for 128Kx16 I/O8-15 WE OE BLOCK DIAGRAM FOR WF128K16-XCX5 I/O0-7 A0-16 I/O0-15 A0-16 I/O8-15 WE OE 128K x 8 128K x 8 128K x 8 128K x 8 A0-16 (1) 128K x 8 CS1 (1) CS2 128K x 8 NOTE: 1. CS1 and CS2 are used to select the lower and upper 128Kx16 of the device. CS1 and CS2 must not be enabled at the same time. CS1 October 1998 1 White Microelectronics • Phoenix, AZ • (602) 437-1520 FLASH MODULES CS2*/NC CS1 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE WF128K16, WF256K16-XCX5 ABSOLUTE MAXIMUM RATINGS (1) Parameter CAPACITANCE (TA = 25°C) Unit Operating Temperature -55 to +125 °C Test Max Unit Supply Voltage Range (VCC) -2.0 to +7.0 V OE capacitance COE VIN = 0 V, f = 1.0 MHz 50 pF Signal voltage range (any pin except A9) (2) -2.0 to +7.0 V WE capacitance CWE VIN = 0 V, f = 1.0 MHz 50 pF Storage Temperature Range -65 to +150 °C CS capacitance CCS VIN = 0 V, f = 1.0 MHz 30 pF +300 °C I/O0-7 capacitance CI/O VI/O = 0 V, f = 1.0 MHz 30 pF Address capacitance CAD VIN = 0 V, f = 1.0 MHz Lead Temperature (soldering, 10 seconds) Data Retention Mil Temp 10 years Endurance (write/erase cycles) Mil Temp 10,000 cycles min. A9 Voltage for sector protect (VID) (3) -2.0 to +14.0 Symbol Conditions pF 50 This parameter is guaranteed by design but not tested. V NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is V CC + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns. 3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input High Voltage V IH 2.0 V CC + 0.3 V Input Low Voltage V IL -0.5 +0.8 V Operating Temp. (Mil.) TA -55 +125 °C Operating Temp. (Ind.) TA -40 +85 °C A9 Voltage for Sector Protect VID 11.5 12.5 V DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol Conditions 128K x 16 Min 7 256K x 16 Max Min Unit Max µA FLASH MODULES Input Leakage Current I LI V CC = 5.5, V IN = GND to VCC 10 10 Output Leakage Current I LO V CC = 5.5, V IN = GND to VCC 10 10 µA VCC Active Current for Read (1) ICC1 CS = VIL, OE = VIH 70 80 mA V CC Active Current for Program or Erase (2) I CC2 CS = V IL , OE = V IH 100 110 mA V CC Standby Current I CC3 V CC = 5.5, CS = V IH , f = 5MHz 6 8 mA Output Low Voltage V OL I OL = 12.0 mA, V CC = 4.5 0.45 0.45 Output High Voltage V OH1 I OH = -2.5 mA, V CC = 4.5 0.85xVcc 0.85xVcc Output High Voltage V OH2 I OH = -100 µA, V CC = 4.5 V CC -0.4 V CC -0.4 V Low V CC Lock Out Voltage V LKO 3.2 3.2 V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. I CC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = V CC - 0.3V White Microelectronics • Phoenix, AZ • (602) 437-1520 2 V V WF128K16, WF256K16-XCX5 WRITE PRINCIPLES OF OPERATION Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine outputs dictate the function of the device. The following principles of operation of the WF128K16-XCX5 and WF256K16-XCX5 are applicable to each 128K x 8 memory chip inside the MCM. Programming of the device is accomplished by executing the program command sequence. The program algorithm, which is an internal algorithm, automatically times the program pulse widths and verifies proper cell margin. Sectors can be programmed and verified in less than 0.3 seconds. Erase is accomplished by executing the erase command sequence. The erase algorithm, which is internal, automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The entire memory is typically erased and verified in three seconds (including pre-programming). The command register itself does not occupy an addressable memory location. The register is a latch used to store the commands, along with address and data information needed to execute the command. The command register is written by bringing Write-Enable to a logic-low level (VIL), while Chip-Select is low and OE is at VIH. Addresses are latched on the falling edge of the Write-Enable while data is latched on the rising edge of the WE pulse. Standard microprocessor write timings are used. Refer to AC Program characteristics, Figures 4 and 7. BUS OPERATIONS READ The device has two control functions, both of which must be logically active, to obtain data at the outputs. Chip-Select (CS) is the power control and should be used for device selection. Output-Enable (OE) is the output control and should be used to gate data to the output pins. Figure 3 illustrates read timing waveforms. OUTPUT DISABLE With Output-Enable at a logic-high level (VIH), output from the device is disabled. Output pins are placed in a high impedance state. STANDBY MODE The device has two standby modes, a CMOS standby mode (CS input held at VCC + 0.5V), and a TTL standby mode (CS is held VIH). In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is completed. 7 3 Operation CS OE WE A0 A1 A9 I/O Read L L H A0 A1 A9 DOUT Standby H X X X X X HIGH Z Output Disable L H H X X X HIGH Z Write L H L A0 A1 A9 DIN Enable Sector Protect L VID L X X VID X Verify Sector Protect L L H L H VID Code White Microelectronics • Phoenix, AZ • (602) 437-1520 FLASH MODULES TABLE 1 - BUS OPERATIONS WF128K16, WF256K16-XCX5 AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol -50 Min -60 Max Min -70 Max Min -90 Max Min -120 Max Min -150 Max Min Unit Max Write Cycle Time t AVAV t WC 50 60 70 90 120 150 Chip Select Setup Time t ELWL t CS 0 0 0 0 0 0 ns Write Enable Pulse Width t WLWH t WP 25 30 35 45 50 50 ns Address Setup Time t AVWL t AS 0 0 0 0 0 0 ns Data Setup Time t DVWH t DS 25 30 30 45 50 50 ns Data Hold Time t WHDX t DH 0 0 0 0 0 0 ns Address Hold Time t WLAX t AH 40 45 45 45 50 50 ns Chip Select Hold Time t WHEH t CH 0 0 0 0 0 0 ns Write Enable Pulse Width High t WHWL t WPH 20 20 20 20 20 20 ns Duration of Byte Programming Operation (min) t WHWH1 14 14 14 14 14 14 Chip and Sector Erase Time t WHWH2 2.2 t GHWL 0 Read Recovery Time Before Write VCC Setup Time t VCS 60 2.2 0 50 Chip Programming Time 60 60 0 50 12.5 2.2 2.2 60 0 50 60 0 50 12.5 2.2 12.5 ns µs 2.2 60 0 50 12.5 ns µs 50 12.5 sec 12.5 sec Output Enable Setup Time tOES 0 0 0 0 0 0 ns Output Enable Hold Time (1) tOEH 10 10 10 10 10 10 ns 1. For Toggle and Data Polling. AC CHARACTERISTICS – READ ONLY OPERATIONS (VCC = 5.0V, V SS = 0V, TA = -55°C to +125°C) Parameter Symbol -50 Min 7 -60 Max Min 50 -70 Max 60 Min -90 Max Min 90 120 -150 Max Min Unit Max FLASH MODULES Read Cycle Time t AVAV t RC Address Access Time t AVQV t ACC 50 60 70 90 120 150 ns Chip Select Access Time t ELQV t CE 50 60 70 90 120 150 ns OE to Output Valid t GLQV t OE 25 30 35 40 50 55 ns Chip Select to Output High Z (1) t EHQZ t DF 20 20 20 25 30 35 ns OE High to Output High Z (1) t GHQZ t DF 20 20 20 25 30 35 ns Output Hold from Address, CS or OE Change, whichever is first t AXQX t OH 0 0 1. Guaranteed by design, not tested. White Microelectronics • Phoenix, AZ • (602) 437-1520 4 70 -120 Min Max 0 0 0 150 0 ns ns WF128K16, WF256K16-XCX5 AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol -50 Min -60 Max Min -70 Max -90 Min Max Min -120 Max Min -150 Max Min Unit Max Write Cycle Time t AVAV t WC 50 60 70 90 120 150 WE Setup Time t WLEL t WS 0 0 0 0 0 0 ns CS Pulse Width t ELEH t CP 25 30 35 45 50 50 ns Address Setup Time t AVEL t AS 0 0 0 0 0 0 ns Data Setup Time t DVEH t DS 25 30 30 45 50 50 ns Data Hold Time t EHDX t DH 0 0 0 0 0 0 ns Address Hold Time t ELAX t AH 40 45 45 45 50 50 ns WE Hold from WE High t EHWH t WH 0 0 0 0 0 0 ns CS Pulse Width High tEHEL tCPH 20 20 20 20 20 20 ns Duration of Programming Operation t WHWH1 14 Duration of Erase Operation t WHWH2 2.2 Read Recovery before Write t GHEL 0 14 60 2.2 14 60 0 Chip Programming Time 12.5 2.2 14 60 0 12.5 2.2 14 60 0 12.5 2.2 µs 14 60 2.2 0 12.5 ns 60 sec 12.5 sec 0 12.5 ns 7 AC TEST CONDITIONS AC TEST CIRCUIT Parameter I OL Current Source VZ D.U.T. ≈ 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source 5 Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. V Z is typically the midpoint of VOH and V OL. I OL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Microelectronics • Phoenix, AZ • (602) 437-1520 FLASH MODULES FIG. 2 WF128K16, WF256K16-XCX5 FIG. 3 tACC tCE tOE Addresses Stable tRC Output Valid tOH tDF High Z AC WAVEFORMS FOR READ OPERATIONS 6 Outputs WE OE Addresses FLASH MODULES White Microelectronics • Phoenix, AZ • (602) 437-1520 CS High Z 7 WF128K16, WF256K16-XCX5 FIG. 4 A0A0H 5.0 V Data tDS tCS WE OE 7 tDH tWPH tWP tGHWL tWC CS Addresses NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed. 3. D7 is the output of the complement of the data written (for each chip). 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 7 FLASH MODULES 5555H tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT tOE tCE tRC tDF tOH AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED White Microelectronics • Phoenix, AZ • (602) 437-1520 WF128K16, WF256K16-XCX5 FIG. 5 NOTES: 1. SA is the sector address for Sector Erase. White Microelectronics • Phoenix, AZ • (602) 437-1520 5555H AAAAH tDS tDH tWPH tCS tWP VCC tVCS 8 Data WE OE CS Addresses tGHWL 5555H FLASH MODULES tAS 7 2AAAH tAH 5555H 8080H 5555H AAAAH 2AAAH 5555H SA 1010H/3030H AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS 9 I/O0-6 and I/O8-14 I/O7 and I/O15 t CH FLASH MODULES Data WE OE CS tOEH tWHWH 1 or 2 tCE t OE I/O0-6 and I/O8-14 Invalid I/O7 and I/O15 t OE I/O0-15 Valid Data I/O7 and I/O15 Valid Data t OH t DF High Z WF128K16, WF256K16-XCX5 FIG. 6 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS 7 White Microelectronics • Phoenix, AZ • (602) 437-1520 WF128K16, WF256K16-XCX5 FIG. 7 A0H NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device (for each chip). 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. White Microelectronics • Phoenix, AZ • (602) 437-1520 tDH 10 5.0 V Data tDS tWS CS OE WE FLASH MODULES Addresses tWC 5555H 7 tCPH tGHEL tCP tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED WF128K16, WF256K16-XCX5 PACKAGE 303: 40 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED 51.3 (2.020) ± 0.5 (0.020) 15.1 (0.595) ± 0.25 (0.010) 7.2 (0.285) ± 0.8 (0.030) PIN 1 IDENTIFIER 3.2 (0.125) MIN 0.25 (0.010) ± 0.05 (0.002) 0.94 (0.037) ± 0.25 (0.010) 2.5 (0.100) TYP 1.27 (0.050) ± 0.1 (0.005) 15.25 (0.600) ± 0.25 (0.010) 0.5 (0.018) ± 0.05 (0.002) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W F XXXK16 - XXX C X 5 X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5 = 5V 7 DEVICE GRADE: M = Military Screened -55°C to 125°C I = Industrial -40°C to +85°C C = Commercial 0 to +70°C PACKAGE TYPE: C = 40 Pin Ceramic 0.600" DIP (Package 303) ACCESS TIME (ns) ORGANIZATION, 128K x 16 or 256K x 16 Flash PROM WHITE MICROELECTRONICS 11 White Microelectronics • Phoenix, AZ • (602) 437-1520 FLASH MODULES Q = Compliant