WEDC WF512K32N

White Electronic Designs
WF512K32-XXX5
512Kx32 5V FLASH MODULE, SMD 5962-94612
FEATURES
Access Times of 60, 70, 90, 120, 150ns
Packaging
Commercial, Industrial and Military Temperature
Ranges
5 Volt Programming. 5V ± 10% Supply.
Low Power CMOS, 6.5mA Standby
68 lead, 40mm, Low Capacitance Hermetic
CQFP (Package 501)1
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
•
68 lead, 40mm, Low Profile 3.5mm (0.140"),
CQFP (Package 502)1
Built-in Decoupling Caps for Low Noise Operation
•
68 lead, 22.4mm (0.880") Low Profile CQFP
(G2U) 3.5mm (0.140") high, (Package 510)1
Page Program Operation and Internal Program
Control Time
•
68 lead, 22.4mm (0.880") CQFP (G2L) 5.08mm
(0.200") high, Package (528)
Weight
•
66 pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP (Package 400(1)).
•
1,000,000 Erase/Program Cycles Minimum
Sector Architecture
•
8 equal size sectors of 64KBytes each
•
Any combination of sectors can be concurrently
erased. Also supports full chip erase
WF512K32 - XG2UX5 - 8 grams typical
WF512K32N - XH1X5 - 13 grams typical
WF512K32 - XG4TX51 - 20 grams typical
WF512K32-XG2LX5 - 8 grams typical
* This product is subject to change without notice.
Note 1: Package Not Recommended for New Design
See Flash Programming Application Note 4M5 for algorithms.
Organized as 512Kx32
FIGURE 1 – PIN CONFIGURATION FOR WF512K32N-XH1X5
Top View
1
12
23
Pin Description
34
45
I/O0-31
A0-18
WE1-4#
CS1-4#
OE#
VCC
GND
NC
56
I/O8
WE2#
I/O15
I/O24
VCC
I/O31
I/O9
CS2#
I/O14
I/O25
CS4#
I/O30
I/O10
GND
I/O13
I/O26
WE4#
I/O29
A14
I/O11
I/O12
A7
I/O27
I/O28
A16
A10
OE#
A12
A4
A1
A11
A9
A17
NC
A5
A2
A0
A15
WE1#
A13
A6
A3
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
WE1# CS1#
A18
VCC
I/O7
A8
WE3#
I/O23
I/O0
CS1#
I/O6
I/O16
CS3#
I/O22
I/O1
NC
I/O5
I/O17
GND
I/O21
I/O2
I/O3
I/O4
I/O18
I/O19
I/O20
512K x 8
8
11
March 2006
Rev. 11
22
33
44
55
WE2# CS2#
WE3# CS3#
WE4# CS4#
OE#
A0-18
I/O0-7
66
1
512K x 8
8
I/O8-15
512K x 8
8
I/O16-23
512K x 8
8
I/O24-31
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WF512K32-XXX5
FIGURE 2 – PIN CONFIGURATION FOR WF512K32-XG4TX51
Pin Description
NC
A0
A1
A2
A3
A4
A5
CS1#
GND
CS3#
WE#
A6
A7
A8
A9
A10
VCC
Top View
I/O0-31
A0-18
WE#
CS1-4#
OE#
VCC
GND
NC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
Block Diagram
CS1#
512K X 8
512K X 8
8
NC
NC
NC
NC
NC
A17
A18
A15
A16
CS2#
OE#
CS4#
A14
A13
A12
A11
CS2#
CS3#
CS4#
WE#
OE#
A0-18
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
VCC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
8
I/O8 - 15
I/O0 - 7
512K X 8
8
I/O16 - 23
512K X 8
8
I/O24 - 31
Note 1: Package not recommended for new designs
FIGURE 3 – PIN CONFIGURATION FOR WF512K32-XG2UX5 AND WF512K32-XG2LX5
Top View
Pin Description
NC
A0
A1
A2
A3
A4
A5
CS3#
GND
CS4#
WE1#
A6
A7
A8
A9
A10
VCC
I/O0-31
A0-18
WE1-4#
CS1-4#
OE#
VCC
GND
NC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
Block Diagram
WE1# CS1#
512K x 8
8
I/O0-7
March 2006
Rev. 11
WE2# CS2#
WE3# CS3#
WE4# CS4#
OE#
A0-18
512K x 8
512K x 8
512K x 8
A18
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VCC
A11
A12
A13
A14
A15
A16
CS1#
OE#
CS2#
A17
WE2#
WE3#
WE4#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
2
8
I/O8-15
8
I/O16-23
8
I/O24-31
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White Electronic Designs
Absolute Maximum Ratings (1)
WF512K32-XXX5
CAPACITANCE
TA = +25°C
Parameter
Operating Temperature
Supply Voltage Range (VCC)
Signal voltage range (any pin except A9) (2)
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
Data Retention (Mil Temp)
Endurance - write/erase cycles (Mil Temp)
A9 Voltage for sector protect (VID) (3)
Unit
Parameter
OE# capacitance
WE1-4# capacitance
HIP (PGA)
CQFP G4T
CQFP G2U/G2L
CS1-4# capacitance
Data# I/O capacitance
Address input capacitance
-55 to +125
°C
-2.0 to +7.0
V
-2.0 to +7.0
V
-65 to +150
°C
+300
°C
20 years
1,000,000 cycles min.
-2.0 to +14.0
V
NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions,inputs
may overshoot Vss to -2.0 V for periods of up to 20ns. Maximum DC voltage on
output and I/O pins is Vcc + 0.5V. During voltage transitions, outputs may overshoot
to Vcc + 2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may
overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is
+13.5V which may overshoot to 14.0 V for periods up to 20ns.
Symbol
Conditions
COE
VIN = 0V, f = 1.0 MHz
CWE
VIN = 0V, f = 1.0 MHz
Max Unit
50 pF
pF
20
50
15
VIN = 0V, f = 1.0 MHz 20 pF
VI/O = 0V, f = 1.0 MHz 20 pF
VIN = 0V, f = 1.0 MHz 50 pF
CCS
CI/O
CAD
This parameter is guaranteed by design but not tested.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
VCC
VIH
VIL
TA
TA
VID
4.5
2.0
-0.5
-55
-40
11.5
5.5
VCC + 0.5
+0.8
+125
+85
12.5
V
V
V
°C
°C
V
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
A9 Voltage for Sector Protect
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Max
Units
VCC = 5.5, VIN = GND to VCC
10
µA
ILOx32
CS# = VIH, OE# = VIH, VOUT = GND to VCC
10
µA
VCC Active Current for Read (1)
ICC1
CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5
190
mA
VCC Active Current for Program or Erase (2)
ICC2
CS# = VIH, OE# = VIH
240
mA
VCC Standby Current
ICC4
VCC = 5.5, CS = VIH, f = 5MHz
6.5
mA
VCC Static Current
ICC3
VCC = 5.5, CS = VIH
0.6
mA
Output Low Voltage
VOL
IOL = 8.0mA, VCC = 4.5
0.45
Output High Voltage
VOH1
IOH = 2.5mA, VCC = 4.5
Low VCC Lock-Out Voltage
VLKO
Input Leakage Current
Output Leakage Current
Sym
ILI
Conditions
Min
0.85 X VCC
3.2
V
V
4.2
V
DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component
(at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
March 2006
Rev. 11
3
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White Electronic Designs
WF512K32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-60
Min
-70
Max
Min
-90
Max
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
tAVAV
tWC
60
70
90
120
150
ns
Write Enable Setup Time
tWLEL
tWS
0
0
0
0
0
ns
Chip Select Pulse Width
tELEH
tCP
40
45
45
50
50
ns
ns
Address Setup Time
tAVEL
tAS
0
0
0
0
0
Data Setup Time
tDVEH
tDS
40
45
45
50
50
ns
Data Hold Time
tEHDX
tDH
0
0
0
0
0
ns
Address Hold Time
tELAX
tAH
40
45
45
50
50
ns
tEHEL
tCPH
20
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
tWHWH1
Sector Erase Time (2)
tWHWH2
Read Recovery Time
tGHEL
20
300
20
300
15
15
0
0
20
300
15
0
20
300
15
0
ns
300
µs
15
sec
0
ns
Chip Programming Time
11
11
11
11
11
sec
Chip Erase Time (3)
64
64
64
64
64
sec
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
FIGURE. 4 – AC TEST CIRCUIT
AC Test Conditions
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
I OL
Current Source
VZ
D.U.T.
1.5V
I OH
Current Source
March 2006
Rev. 11
Unit
V
ns
V
V
Notes:
V Z is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
V Z is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
(Bipolar Supply)
C eff = 50 pf
Typ
VIL = 0, VIH = 3.0
5
1.5
1.5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WF512K32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,WE# CONTROLLED
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-60
Min
-70
Max
Min
-90
Max
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
tAVAV
tWC
60
70
90
120
150
ns
Chip Select Setup Time
tELWL
tCS
0
0
0
0
0
ns
Write Enable Pulse Width
tWLWH
tWP
40
45
45
50
50
ns
ns
Address Setup Time
tAVWH
tAS
0
0
0
0
0
Data Setup Time
tDVWH
tDS
40
45
45
50
50
ns
Data Hold Time
tWHDX
tDH
0
0
0
0
0
ns
Address Hold Time
tWHAX
tAH
40
45
45
50
50
ns
Write Enable Pulse Width High
tWHWL
tWPH
20
Duration of Byte Programming Operation (1)
tWHWH1
Sector Erase Time (2)
tWHWH2
Read Recovery Time before Write
tGHWL
VCC Set-up Time
20
20
300
15
tVCS
0
50
Output Enable Setup Time
tOES
0
Output Enable Hold Time (4)
tOEH
10
10
sec
µs
11
0
10
64
15
ns
11
0
10
64
µs
50
11
0
300
0
50
11
0
Chip Erase Time (3)
15
0
50
11
ns
300
15
0
50
20
300
15
0
Chip Programming Time
20
300
ns
10
64
sec
ns
64
64
sec
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
4. For Toggle and Data Polling.
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,WE# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-60
Min
-70
Max
Min
60
-90
Max
70
Min
-120
Max
90
Min
-150
Max
120
Min
Unit
Max
Read Cycle Time
tAVAV
tRC
Address Access Time
tAVQV
tACC
60
70
90
120
150
150
ns
ns
Chip Select Access Time
tELQV
tCE
60
70
90
120
150
ns
Output Enable to Output Valid
tGLQV
tOE
30
35
35
50
55
ns
Chip Select to Output High Z (1)
tEHQZ
tDF
20
20
20
30
35
ns
Output Enable High to Output High Z (1)
tGHQZ
tDF
Output Hold from Address, CS# or OE#
Change, whichever is First
tAXQX
tOH
20
20
0
0
20
0
30
0
35
0
ns
ns
1. Guaranteed by design, but not tested
March 2006
Rev. 11
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WF512K32-XXX5
FIGURE 5 – AC WAVEFORMS FOR READ OPERATIONS
CS#
OE#
WE#
March 2006
Rev. 11
6
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White Electronic Designs
WF512K32-XXX5
FIGURE 6 – WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
Data# Polling
CS#
OE#
WE#
D7#
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device (for each chip).
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
March 2006
Rev. 11
7
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White Electronic Designs
WF512K32-XXX5
FIGURE 7 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
tAH
Addresses
5555H
2AAAH
5555H
5555H
2AAAH
SA
tAS
CS#
tGHWL
OE#
tWP
WE#
tWPH
tCS
Data
tDH
AAH
55H
80H
AAH
55H
10H/30H
tDS
VCC
tVCS
NOTE:
1. SA is the sector address for Sector Erase.
March 2006
Rev. 11
8
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White Electronic Designs
WF512K32-XXX5
FIGURE 8 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED
ALGORITHM OPERATIONS
t CH
CS#
t DF
t OE
OE#
tOEH
WE#
tCE
t OH
D7 =
Valid Data
D7#
D7
High Z
tWHWH 1 or 2
Data
D0-D7
Valid Data
D0-D6 = Invalid
D0-D6
t OE
March 2006
Rev. 11
9
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White Electronic Designs
WF512K32-XXX5
FIGURE 9 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
Data# Polling
CS#
OE#
WE#
D7#
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device (for each chip).
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
March 2006
Rev. 11
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WF512K32-XXX5
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
4.60 (0.181)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
March 2006
Rev. 11
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WF512K32-XXX5
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
o
o
The White 68 lead G2U CQFP fills the same fit
and function as the JEDEC 68 lead CQFJ or
68 PLCC. But the G2U has the TCE and lead
inspection advantage of the CQFP form.
0.940" TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
March 2006
Rev. 11
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WF512K32-XXX5
PACKAGE 528: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2L)
25.15 (0.990) ± 0.25 (0.010) MAX
5.10 (0.200) MAX
22.36 (0.880) ± 0.25 (0.010) MAX
0.25 (0.010) ± 0.10 (0.002)
0.23 (0.009) REF
24.0 (0.946)
± 0.25 (0.010)
R 0.127
(0.005)
O
1.37 (0.054) MIN
0.004
O
2 /9
0.89 (0.035)
± 1.14 (0.045)
1.27 (0.050) TYP
0.38 (0.015) ± 0.05 (0.002)
20.31 (0.800) REF
0.940" TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
March 2006
Rev. 11
13
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White Electronic Designs
WF512K32-XXX5
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)1
5.1 (0.200) MAX
39.6 (1.56) ± 0.38 (0.015) SQ
1.27 (0.050)
± 0.1 (0.005)
PIN 1 IDENTIFIER
Pin 1
12.7 (0.500)
± 0.5 (0.020)
4 PLACES
5.1 (0.200)
± 0.25 (0.010)
4 PLACES
1.27 (0.050)
TYP
0.38 (0.015)
± 0.08 (0.003)
68 PLACES
0.25 (0.010)
± 0.05 (0.002)
38 (1.50) TYP
4 PLACES
Note 1: Package Not Recommended for New Design
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
March 2006
Rev. 11
14
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White Electronic Designs
WF512K32-XXX5
ORDERING INFORMATION
W F 512K32 X - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5=5V
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M = Military Screened
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex In Line Package, HIP (Package 400*)
G2U = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 510)
G2L = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 528)
G4T1 = 40mm Low Profile CQFP (Package 502)
ACCESS TIME (ns)
IMPROVEMENT MARK
N = No Connect at pins 21 and 39 in HIP for Upgrade
ORGANIZATION, 512K x 32
User configurable as 1M x 16 or 2M x 8
FLASH
WHITE ELECTRONIC DESIGNS CORP.
Note 1: Package Not Recommended for New Design
March 2006
Rev. 11
15
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White Electronic Designs
WF512K32-XXX5
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
512K x 32 Flash Module
150ns
66 pin HIP (H1) 1.075" sq.
5962-94612 01H4X
512K x 32 Flash Module
120ns
66 pin HIP (H1) 1.075" sq.
5962-94612 02H4X
512K x 32 Flash Module
90ns
66 pin HIP (H1) 1.075" sq.
5962-94612 03H4X
512K x 32 Flash Module
70ns
66 pin HIP (H1) 1.075" sq.
5962-94612 04H4X
512K x 32 Flash Module
150ns
68 lead CQFP Low Profile (G4T)1
5962-94612 01HTX1
512K x 32 Flash Module
120ns
68 lead CQFP Low Profile (G4T)1
5962-94612 02HTX1
1
5962-94612 03HTX1
512K x 32 Flash Module
90ns
68 lead CQFP Low Profile (G4T)
512K x 32 Flash Module
70ns
68 lead CQFP Low Profile (G4T)1
5962-94612 04HTX1
512K x 32 Flash Module
150ns
68 lead CQFP/J (G2U)
5962-94612 01HZX
512K x 32 Flash Module
120ns
68 lead CQFP/J (G2U)
5962-94612 02HZX
512K x 32 Flash Module
90ns
68 lead CQFP/J (G2U)
5962-94612 03HZX
512K x 32 Flash Module
70ns
68 lead CQFP/J (G2U)
5962-94612 04HZX
512K x 32 Flash Module
150ns
68 lead CQFP (G2L)
5962-94612 01HAX
512K x 32 Flash Module
120ns
68 lead CQFP (G2L)
5962-94612 02HAX
512K x 32 Flash Module
90ns
68 lead CQFP (G2L)
5962-94612 03HAX
512K x 32 Flash Module
70ns
68 lead CQFP (G2L)
5962-94612 04HAX
March 2006
Rev. 11
16
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com