WSF128K16-XXX 128Kx16 SRAM/FLASH MODULE, SMD 5962-96900 FEATURES n Access Times of 35ns (SRAM) and 70ns (FLASH) n Access Times of 70ns (SRAM) and 120ns (FLASH) n Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation n Weight • WSF128K16-XHX - 13 grams typical • WSF128K16-H1X - 13 grams typical • WSF128K16-XG1UX - 5 grams typical n Packaging • 66-pin, PGA Type, 1.075 inch square HIP, Hermetic Ceramic HIP (Package 400) FLASH MEMORY FEATURES • 66-pin, PGA Type, 1.185 inch square HIP, Hermetic Ceramic HIP (Package 401) • 68 lead, Hermetic CQFP (G1U), 22.4mm (0.880 inch) square (Package 519). Designed to fit JEDEC 68 lead 0.990” CQFJ footprint (Fig. 2) n 10,000 Erase/Program Cycles n Sector Architecture • 8 equal size sectors of 16K bytes each • Any combination of sectors can be concurrently erased. Also supports full chip erase n 128Kx16 SRAM n 128Kx16 5V FLASH n Organized as 128Kx16 of SRAM and 128Kx16 of Flash Memory with separate Data Buses n 5 Volt Programming; 5V ± 10% Supply n Embedded Erase and Program Algorithms n Both blocks of memory are User Configurable as 256Kx8 n Hardware Write Protection n Page Program Operation and Internal Program Control Time. n Low Power CMOS n Commercial, Industrial and Military Temperature Ranges Note: For programming information refer to Flash Programming 1M5 Application Note. n TTL Compatible Inputs and Outputs PIN DESCRIPTION FIG.1 PIN CONFIGURATION FOR WSF128K16-XHX AND WSF128K16-XH1X TOP VIEW FD0-15 Flash Data Inputs/Outputs SD0-15 SRAM Data Inputs/Outputs A 0-16 Address Inputs SWE1-2 SRAM Write Enable SCS1-2 SRAM Chip Selects OE Output Enable VCC Power Supply GND Ground NC Not Connected FWE1-2 Flash Write Enable FCS1-2 Flash Chip Select BLOCK DIAGRAM May 2001 Rev. 5 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF128K16-XXX FIG. 2 PIN CONFIGURATION FOR WSF128K16-XG1UX PIN DESCRIPTION TOP VIEW The WEDC 68 lead G1U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G1U has the TCE and lead inspection advantage of the CQFP form. FD 0-15 Flash Data Inputs/Outputs SD0-15 SRAM Data Inputs/Outputs A 0-16 Address Inputs SWE1-2 SRAM Write Enable SCS1-2 SRAM Chip Selects OE Output Enable VCC Power Supply GND Ground NC Not Connected FWE1-2 Flash Write Enable FCS1-2 Flash Chip Select BLOCK DIAGRAM White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 WSF128K16-XXX SRAM TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit SCS OE SWE Mode Data I/O Power TA -55 +125 °C °C H L L L X L H X X H H L Standby Read Read Write High Z Data Out High Z Data In Standby Active Active Active Operating Temperature Storage Temperature T STG -65 +150 Signal Voltage Relative to GND VG -0.5 7.0 V Junction Temperature TJ 150 °C 7.0 V Supply Voltage VCC -0.5 CAPACITANCE (TA = +25°C) Parameter Flash Data Retention 10 years Flash Endurance (write/erase cycles) 10,000 Test NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Max Unit OE Capacitance COE V IN = 0V, f = 1.0MHz 50 pF F/S WE 1-2 Capacitance C WE V IN = 0V, f = 1.0MHz 20 pF F/S CS 1-2 Capacitance C CS V IN = 0V, f = 1.0MHz 20 pF SD0-15/FD0-15 Capacitance CI / O V IN = 0V, f = 1.0MHz 20 pF A0 - A16 Capacitance C AD V IN = 0V, f = 1.0MHz 50 pF This parameter is guaranteed by design but not tested. Symbol Min Max Supply Voltage V CC 4.5 5.5 Unit V Input High Voltage VIH 2.2 V CC + 0.3 V Input Low Voltage V IL -0.5 +0.8 V DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Max Unit Input Leakage Current ILI V CC = 5.5, V IN = GND to VCC 10 µA Output Leakage Current ILO SCS = VIH, OE = VIH, VOUT = GND to VCC 10 µA I CCx16 SCS = VIL, OE = FCS = VIH, f = 5MHz, V CC = 5.5 360 mA Standby Current I SB FCS = SCS = VIH, OE = VIH, f = 5MHz, V CC = 5.5 40 mA SRAM Output Low Voltage V OL I OL = 2.1mA, V CC = 4.5 0.4 SRAM Output High Voltage VOH I OH = -1.0mA, V CC = 4.5 Flash V CC Active Current for Read (1) ICC1 FCS = VIL, OE = SCS = VIH 100 mA Flash V CC Active Current for Program or Erase (2) ICC2 FCS = VIL, OE = SCS = VIH 130 mA Flash Output Low Voltage V OL I OL = 8.0mA, V CC = 4.5 Flash Output High Voltage V OH1 I OH = -2.5 mA, V CC = 4.5 0.85 x V CC Flash Output High Voltage V OH2 I OH = -100 µA, V CC = 4.5 V CC -0.4 V Flash Low V CC Lock Out Voltage V LKO 3.2 V SRAM Operating Supply Current x 16 Mode Symbol Conditions Min 2.4 V V 0.45 V V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF128K16-XXX SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C TO +125°C) SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol Read Cycle -35 Min -70 Max 35 Min -35 Min -70 Unit Max ns Write Cycle Time t WC 35 70 ns ns Chip Select to End of Write tCW 25 60 ns ns Address Valid to End of Write t AW 25 60 ns 70 ns Data Valid to End of Write t DW 20 30 ns 35 ns Write Pulse Width t WP 25 50 ns ns Address Setup Time t AS 0 5 ns ns Address Hold Time t AH 0 5 ns ns Output Active from End of Write t OW 1 4 5 Write Enable to Output in High Z t WHZ 1 t RC Address Access Time t AA 70 Output Hold from Address Change tOH Chip Select Access Time t ACS 35 Output Enable to Output Valid tOE 20 Chip Select to Output in Low Z t CLZ 1 3 Output Enable to Output in Low Z t OLZ 1 0 Chip Disable to Output in High Z t CHZ 1 20 25 Output Disable to Output in High Z t OHZ 1 20 25 ns 0 Symbol Write Cycle Read Cycle Time 35 Parameter Unit Max 70 3 3 0 1. This parameter is guaranteed by design but not tested. Data Hold from Write Time tDH 20 0 ns 25 0 ns ns 1. This parameter is guaranteed by design but not tested. FIG. 3 AC TEST C IRCUIT AC TEST C ONDITIONS Parameter Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75W. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 4 WSF128K16-XXX FIG. 4 SRAM T IMING W AVEFORM - READ CYCLE FIG. 5 SRAM WRITE CYCLE - SWE CONTROLLED FIG. 6 SRAM W RITE CYCLE - SCS CONTROLLED WS32K32-XHX 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF128K16-XXX FL ASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FWE CONTROLLED (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -70 Min -120 Max Min Unit Max Write Cycle Time t AVAV t WC 70 120 ns Chip Select Setup Time tELWL tCS 0 0 ns Write Enable Pulse Width t WLWH t WP 35 50 ns Address Setup Time tAVWL t AS 0 0 ns Data Setup Time t DVWH tDS 30 50 ns Data Hold Time t WHDX tDH 0 0 ns Address Hold Time tWLAX t AH 45 50 ns Chip Select Hold Time t WHEH t CH 0 0 ns Write Enable Pulse Width High t WHWL t WPH 20 20 ns Duration of Byte Programming Operation (min) t WHWH1 14 14 µs Chip and Sector Erase Time t WHWH2 2.2 t GHWL 0 0 µs t VCS 50 50 µs Output Enable Setup Time tOES 0 0 ns Output Enable Hold Time (1) tOEH 10 10 ns Read Recovery Time Before Write VCC Set-up Time 60 Chip Programming Time 2.2 60 12.5 12.5 sec sec 1. For Toggle and Data Polling. FL ASH AC CHARACTERISTICS READ ONLY OPERATIONS (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -70 Min Max 70 -120 Min Unit Max Read Cycle Time t AVAV t RC Address Access Time t AVQV t ACC 70 120 ns Chip Select Access Time t ELQV t CE 70 120 ns OE to Output Valid t GLQV tOE 35 50 ns Chip Select to Output High Z (1) t EHQZ t DF 20 30 ns OE High to Output High Z (1) t GHQZ t DF 20 30 ns Output Hold from Address, CS or OE Change, whichever is first t AXQX tOH 1. Guaranteed by design, not tested. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 6 0 120 0 ns ns WSF128K16-XXX FL ASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FCS CONTROLLED (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -70 Min -120 Max Min Unit Max Write Cycle Time t AVAV t WC 70 120 ns FWE Setup Time tWLEL t WS 0 0 ns FCS Pulse Width t ELEH t CP 35 50 ns Address Setup Time t AVEL t AS 0 0 ns Data Setup Time tDVEH tDS 30 50 ns Data Hold Time t EHDX tDH 0 0 ns Address Hold Time tELAX t AH 45 50 ns FWE Hold from FWE High t EHWH t WH 0 0 ns tEHEL tCPH FCS Pulse Width High 20 20 ns Duration of Programming Operation t WHWH1 14 14 µs Duration of Erase Operation t WHWH2 2.2 t GHEL 0 Read Recovery before Write Chip Programming Time 60 60 sec 12.5 sec 0 12.5 7 2.2 ns White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF128K16-XXX FIG. 7 AC WAVEFORMS FOR F L ASH MEMORY READ OPERATIONS White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 8 WSF128K16-XXX FIG. 8 WRITE/ERASE/PROGRAM OPERATION, FL ASH MEMORY FWE CONTROLLED NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF128K16-XXX FIG. 9 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FL ASH MEMORY Notes: 1. SA is the sector address for Sector Erase. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 10 WSF128K16-XXX FIG. 10 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FL ASH MEMORY 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF128K16-XXX FIG. 11 WRITE/ERASE/PROGRAM OPERATION FOR FL ASH MEMORY, CS CONTROLLED NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 12 WSF128K16-XXX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-L INE PACKAGE, HIP (H1) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WSF128K16-XXX PACKAGE 519: 68 LEAD, CERAMIC QUAD FL AT PACK, CQFP (G1U) The WEDC 68 lead G1U CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G1U has the TCE and lead inspection advantage of the CQFP form. ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 14 WSF128K16-XXX ORDERING INFORMATION W S F 128K16 - XXX X X X LEAD FINISH: Blank =Gold plated leads A = Solder dip leads DEVICE GRADE: M I C = Military Screened = Industrial = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE TYPE: H1 H G1U = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400) = 1.185" sq. Ceramic Hex In-line Package, HIP (Package 401) = 22.4 mm Ceramic Quad Flat Pack, CQFP (Package 519) ACCESS TIME (ns) 37 72 = 35ns SRAM and 70ns FLASH = 70ns SRAM and 120ns FLASH ORGANIZATION, 128K x 16 FLASH SRAM WHITE ELECTRONIC DESIGNS CORP. DEVICE TYPE SRAM SPEED FLASH SPEED PACKAGE SMD NO. 128K x 16 Mixed Module 70ns 120ns 66 pin HIP (H) 5962-96900 01HXX 128K x 16 Mixed Module 70ns 120ns 66 pin HIP (H1) 5962-96900 01HYX 128K x 16 Mixed Module 35ns 70ns 66 pin HIP (H) 5962-96900 02HXX 128K x 16 Mixed Module 35ns 70ns 66 pin HIP (H1) 5962-96900 02HYX 128K x 16 Mixed Module 70ns 120ns 68 lead CQFP/J (G1U) 5962-96900 01HX* 128K x 16 Mixed Module 35ns 70ns 68 lead CQFP/J (G1U) 5962-96900 02HX* *SMD Pending 15 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com