WSF128K32-XH2X White Electronic Designs 128KX32 SRAM/FLASH MODULE PRELIMINARY* FEATURES FLASH MEMORY FEATURES ■ Access Times of 25ns (SRAM) and 70, 90 and 120ns (FLASH) ■ 10,000 Erase/Program Cycles ■ Sector Architecture ■ Packaging: 8 equal size sectors of 16K bytes each 66-pin, PGA Type, 1.385 inch square HIP, Hermetic Ceramic HIP (Package 402) Any combination of sectors can be concurrently erased. Also supports full chip erase ■ 128Kx32 SRAM ■ 5 Volt Programming; 5V ± 10% Supply ■ 128Kx32 5V Flash ■ Embedded Erase and Program Algorithms ■ Organized as 128Kx32 of SRAM and 128Kx32 of Flash Memory with common Data Bus ■ Hardware Write Protection ■ Page Program Operation and Internal Program Control Time. ■ Low Power CMOS ■ Commercial, Industrial and Military Temperature Ranges * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. ■ TTL Compatible Inputs and Outputs ■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Note: Programming information available upon request. ■ Weight - 13 grams typical FIG. 1 PIN CONFIGURATION FOR WSF128K32-XH2X TOP VIEW 1 11 12 23 34 45 I/O8 FWE2 I/O15 I/O24 VCC I/O31 I/O9 SWE2 I/O14 I/O25 SWE4 I/O30 I/O10 GND I/O13 I/O26 FWE4 I/O29 A14 I/O11 I/O12 A7 I/O27 I/O28 A16 A10 OE A12 A4 A1 A11 A9 NC SWE1 A5 A2 A0 A15 FWE1 A13 A6 A3 NC VCC I/O7 A8 FWE3 I/O23 I/O0 FCS I/O6 I/O16 SWE3 I/O22 I/O1 SCS I/O5 I/O17 GND I/O21 I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 22 October 2002 Rev. 4 33 44 55 PIN DESCRIPTION 56 D0-31 A0-16 SWE 1-4 SCS OE VCC GND NC Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected FWE1-4 FCS Flash Write Enables Flash Chip Select BLOCK DIAGRAM FWE1 SWE1 FWE2 SWE2 FWE3 SWE3 FWE4 SWE4 OE A0-16 SCS FCS 128K x 8 Flash 66 1 128K x 8 Flash 128K x 8 Flash 128K x 8 Flash 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF128K32-XH2X White Electronic Designs A BSOLUTE MAXIMUM RATINGS Parameter SRAM TRUTH TABLE Symbol Min Max Unit SCS OE SWE Mode Data I/O Power TA -55 +125 °C H X X Standby High Z Standby Active Operating Temperature Storage Temperature T STG -65 +150 °C L L H Read Data Out Signal Voltage Relative to GND VG -0.5 7.0 V L H H Read High Z Active Junction Temperature TJ 150 °C L X L Write Data In Active 7.0 V Supply Voltage -0.5 V CC NOTE: 1. FCS must remain high when SCS is low. Parameter Flash Data Retention 10 years Flash Endurance (write/erase cycles) 10,000 CAPACITANCE (TA = +25°C) NOTE: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Test RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input High Voltage V IH 2.2 V CC + 0.3 V Input Low Voltage V IL -0.5 +0.8 V Symbol Condition Max Unit OE Capacitance C OE V IN = 0V, f = 1.0MHz 80 pF F/S WE 1-4 Capacitance C WE V IN = 0V, f = 1.0MHz 30 pF F/S CS Capacitance C CS V IN = 0V, f = 1.0MHz 50 pF D0-31 Capacitance CI /O V IN = 0V, f = 1.0MHz 30 pF A0 - A16 Capacitance C AD V IN = 0V, f = 1.0MHz 80 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Max Unit Input Leakage Current I LI V CC = 5.5, V IN = GND to VCC 10 µA Output Leakage Current I LO SCS = VIH, OE = VIH, VOUT = GND to VCC 10 µA I CCx32 SCS = VIL, OE = FCS = VIH, f = 5MHz, V CC = 5.5 670 mA Standby Current I SB FCS = SCS = VIH, OE = VIH, f = 5MHz, V CC = 5.5 80 mA SRAM Output Low Voltage V OL I OL = 8mA, V CC = 4.5 0.4 SRAM Output High Voltage V OH I OH = -4.0mA, V CC = 4.5 Flash V CC Active Current for Read (1) I CC1 FCS = VIL, OE = SCS = VIH 220 mA Flash V CC Active Current for Program or Erase (2) I CC2 FCS = VIL, OE = SCS = VIH 280 mA Flash Output Low Voltage V OL I OL = 8.0mA, V CC = 4.5 0.45 V Flash Output High Voltage V OH1 I OH = -2.5 mA, V CC = 4.5 0.85 x V CC Flash Output High Voltage V OH2 I OH = -100 µA, V CC = 4.5 V CC -0.4 V Flash Low V CC Lock Out Voltage V LKO 3.2 V SRAM Operating Supply Current x 32 Mode Symbol Conditions Min 2.4 NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V White Electronic Designs Corporation Phoenix AZ (602) 437-1520 2 V V V WSF128K32-XH2X White Electronic Designs SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C TO +125°C) -25 Read Cycle Min Unit Parameter Max Read Cycle Time t RC 25 Address Access Time tAA Output Hold from Address Change t OH Chip Select Access Time t ACS Output Enable to Output Valid t OE Chip Select to Output in Low Z t CLZ 1 3 Output Enable to Output in Low Z t OLZ 1 0 Chip Disable to Output in High Z t CHZ 1 12 Output Disable to Output in High Z t OHZ 1 12 Symbol Write Cycle -25 Min Unit Max ns Write Cycle Time t WC 25 ns ns Chip Select to End of Write tCW 20 ns ns Address Valid to End of Write t AW 20 ns 25 ns Data Valid to End of Write t DW 15 ns 15 ns Write Pulse Width t WP 20 ns ns Address Setup Time t AS 0 ns ns Address Hold Time t AH 0 ns ns Output Active from End of Write t OW 1 3 ns Write Enable to Output in High Z t WHZ 1 25 0 Data Hold from Write Time 1. This parameter is guaranteed by design but not tested. t DH ns 15 ns 0 ns 1. This parameter is guaranteed by design but not tested. FIG. 2 AC TEST CIRCUIT AC TEST CONDITIONS Parameter I OL Current Source Unit VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 W. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. VZ ≈ 1.5V D.U.T. (Bipolar Supply) C eff = 50 pf Typ Input Pulse Levels I OH Current Source 3 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF128K32-XH2X White Electronic Designs FIG. 3 SRAM TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA SCS tRC tCHZ tACS ADDRESS tCLZ tAA SOE tOE tOLZ tOH DATA I/O DATA I/O DATA VALID PREVIOUS DATA VALID tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 1, (SCS = OE = V IL, SWE = FCS = VIH ) READ CYCLE 2, (SWE = FCS = VIH ) FIG. 4 SRAM WRITE CYCLE - SWE CONTROLLED tWC ADDRESS tAW tAH tCW SCS tAS tWP SWE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, SWE CONTROLLED (FCS = VIH) FIG. 5 SRAM WRITE CYCLE - SCS CONTROLLED tWC WS32K32-XHX ADDRESS tAS tAW tAH tCW SCS tWP SWE tDW DATA I/O DATA VALID WRITE CYCLE 2, SCS CONTROLLED (FCS = VIH ) White Electronic Designs Corporation Phoenix AZ (602) 437-1520 4 tDH WSF128K32-XH2X White Electronic Designs FLASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FWE CONTROLLED (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -70 Min -90 Max Min -120 Max Min Unit Max Write Cycle Time t AVAV t WC 70 90 120 ns Chip Select Setup Time t ELWL t CS 0 0 0 ns Write Enable Pulse Width t WLWH t WP 35 45 50 ns Address Setup Time t AVWL t AS 0 0 0 ns Data Setup Time t DVWH t DS 30 45 50 ns Data Hold Time t WHDX t DH 0 0 0 ns Address Hold Time t WLAX t AH 45 45 50 ns Chip Select Hold Time t WHEH t CH 0 0 0 ns Write Enable Pulse Width High t WHWL t WPH 20 20 20 ns Duration of Byte Programming Operation (min) t WHWH1 14 14 14 µs Chip and Sector Erase Time t WHWH2 2.2 t GHWL 0 0 0 µs t VCS 50 50 50 µs Output Enable Setup Time tOES 0 0 0 ns Output Enable Hold Time (1) tOEH 10 10 10 ns Read Recovery Time Before Write VCC Set-up Time 60 Chip Programming Time 2.2 60 12.5 2.2 60 12.5 12.5 sec sec 1. For Toggle and Data Polling. FLASH AC CHARACTERISTICS READ ONLY OPERATIONS (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -70 Min -90 Max Read Cycle Time t AVAV t RC Address Access Time t AVQV t ACC 70 70 Min -120 Max 90 Min Unit Max 120 ns 90 120 ns Chip Select Access Time t ELQV t CE 70 90 120 ns OE to Output Valid t GLQV t OE 35 40 50 ns Chip Select to Output High Z (1) t EHQZ t DF 20 25 30 ns OE High to Output High Z (1) t GHQZ t DF 20 25 30 ns Output Hold from Address, FCS or OE Change, whichever is first t AXQX t OH 0 0 0 ns 1. Guaranteed by design, not tested. 5 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF128K32-XH2X White Electronic Designs FLASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FCS CONTROLLED (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol Min -70 Max Min -90 Max Min -120 Max Unit Write Cycle Time t AVAV t WC 70 90 120 ns FWE Setup Time t WLEL t WS 0 0 0 ns FCS Pulse Width t ELEH t CP 35 45 50 ns Address Setup Time t AVEL t AS 0 0 0 ns Data Setup Time t DVEH t DS 30 45 50 ns Data Hold Time t EHDX t DH 0 0 0 ns Address Hold Time t ELAX t AH 45 45 50 ns FWE Hold from FWE High t EHWH t WH 0 0 0 ns tEHEL tCPH FCS Pulse Width High 20 20 20 ns Duration of Programming Operation t WHWH1 14 14 14 µs Duration of Erase Operation t WHWH2 2.2 Read Recovery before Write t GHEL 0 Chip Programming Time White Electronic Designs Corporation Phoenix AZ (602) 437-1520 60 60 0 12.5 6 2.2 2.2 60 sec 12.5 sec 0 12.5 ns WSF128K32-XH2X White Electronic Designs Outputs FWE OE FCS High Z tACC tCE tOE Addresses Stable Addresses tRC Output Valid tOH tDF High Z FIG. 6 AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS NOTE: SCS = V IH 7 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF128K32-XH2X White Electronic Designs White Electronic Designs Corporation Phoenix AZ (602) 437-1520 A0H 5.0 V Data tDS tCS FWE OE 8 tDH tWPH tWP tGHWL tWC FCS NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. SCS = VIH Addresses 5555H tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT tOE tCE tRC tDF tOH FIG. 7 WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE CONTROLLED WSF128K32-XH2X White Electronic Designs AAH tDS tDH VCC tVCS 9 Data FWE OE FCS Notes: 1. SA is the sector address for Sector Erase. 2. SCS = VIH Addresses tGHWL tCS tWP tWPH 55H 2AAAH 5555H tAS tAH 5555H 80H 5555H AAH 2AAAH 55H SA 10H/30H FIG. 8 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF128K32-XH2X White Electronic Designs High Z D7 D7 tWHWH 1 or 2 D0-D6 = Invalid D0-D6 t OE FWE OE FCS D7 t CH tOEH tCE t OE tWHWH 1 or 2 D7 D7 Valid Data D0-D7 Valid Data D7 = Valid Data t OH t DF High Z FIG. 9 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY Note: SCS = VIH White Electronic Designs Corporation Phoenix AZ (602) 437-1520 10 WSF128K32-XH2X White Electronic Designs A0H tDH tCPH 5.0 V tDS Data FCS OE tWS tWC FWE Addresses 5555H tGHEL tCP tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT FIG. 10 WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS CONTROLLED NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. 6. SCS = VIH 11 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF128K32-XH2X White Electronic Designs PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2) 35.2 (1.385) ± 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 5.7 (0.223) MAX 3.81 (0.150) ± 0.1 (0.005) 1.27 (0.050) ± 0.1 (0.005) 0.76 (0.030) ± 0.1 (0.005) 2.54 (0.100) TYP 1.27 (0.050) TYP DIA 15.24 (0.600) TYP 0.46 (0.018) ± 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W S F 128K32 - XX H2 X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE TYPE: H2 = Ceramic Hex In-line Package, HIP (Package 402) ACCESS TIME (ns) 22 = 25ns SRAM and 120ns FLASH 29 = 25ns SRAM and 90ns FLASH 27 = 25ns SRAM and 70ns FLASH ORGANIZATION, 128K x 32 Flash PROM SRAM WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corporation Phoenix AZ (602) 437-1520 12