xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER NOVEMBER 2006 REV. 1.0.0 GENERAL DESCRIPTION input is pulled low. This is a test mode intended for system debug purposes. The XRK39351 is a low voltage PLL based clock driver designed for high speed clock distribution applications. The XRK39351 has two reference clock inputs, one LVPECL and the other LVCMOS. The REF_SEL input selects clock input to be used as the PLL’s reference source. The XRK39351 uses PLL technology to frequency lock its outputs to the clock reference input. The divider in the feedback path will determine the frequency of the VCO. The XRK39351 provides 9 LVCMOS outputs that are separated into 4 banks. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK39351 to generate a variety of output-to-input frequency ratios (1:1, 1:2, 1:4, 2:1 and 4:1). All outputs provide LVCMOS compatible levels while driving 50Ω terminated transmission lines. The input reference clock can be directly applied to the output dividers bypassing the PLL when PLL_EN The XRK39351 has an output/input frequency range of 25MHz to 200MHz with the PLL enabled and an input frequency range of 2MHz to 300MHz when the PLL is disabled (test mode). FEATURES • • • • • 9 LVCMOS Outputs (4 banks) • • • • 150ps max output to output skew 25 - 200 MHz output frequency range Fully Integrated PLL 2.5V or 3.3V Operation Selectable reference clock input, LVCMOS or LVPECL Pin compatible with MPC9351 Industrial temp range: -40°C to +85°C 32-Lead TQFP Packaging FIGURE 1. BLOCK DIAGRAM OF THE XRK39351 REF_SEL ÷2 0 QA TCLK 1 PECL PECL 0 Ref ÷4 PLL 1 FB FB_IN VDD PLL_EN SELA SELB SELC SELD 1 0 ÷8 0 QB 1 0 QC0 1 QC1 QD0 0 OE QD1 QD2 1 QD3 QD4 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRK39351CQ 32-Lead TQFP 0°C to +70°C XRK39351IQ 32-Lead TQFP -40°C to +85°C REF_SEL PLL_EN TCLK GND QA VCCQB QB GND FIGURE 2. PIN OUT OF THE XRK39351 32 31 30 29 28 27 26 25 AVCC 1 24 QC0 FB_IN 2 23 VCCQC SELA 3 22 QC1 SELB 4 21 GND SELC 5 20 QD0 SELD 6 19 VCCQD AGND 7 18 QD1 PECL 8 17 GND 2 OE VCC QD4 13 14 15 16 QD2 12 VCCQD 11 QD3 10 GND 9 PECL XRK39351 xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 PIN DESCRIPTIONS NUMBER NAME TYPE DESCRIPTION 1 AVCC Power 2 FB_IN Input pull-down External PLL feedback clock input 3 SELA Input pull-down Selects divider value for Bank A output 4 SELB Input pull-down Selects divider value for Bank B output 5 SELC Input pull-down Selects divider value for Bank C outputs 6 SELD Input pull-down Selects divider value for Bank D outputs 7 AGND Power PLL ground 8 PECL Input LVPECL - pos differential reference clock 9 PECL Input LVPECL - neg differential reference clock 10 OE Input 11 VCC Power Power supply for core, inputs and bank A output clock 12, 14, 16, 18, 20 QD[4:0] Output Bank D clock outputs 13, 17, 21, 25, 29 GND Power Ground 15, 19 VCCQD Power Power supply for bank D output clocks 20, 22 QC[1:0] Output Bank C clock outputs 23 VCCQC Power Power supply for bank C output clocks 26 QB Output Bank B clock output 27 VCCQB Power Power supply for bank B output clock 28 QA Output Bank A clock output 30 TCLK Input pull-down 31 PLL_EN Input pull-up 32 REF_SEL Input pull-down Power supply for PLL pull-down Output enable/disable and device reset LVCMOS reference clock input Selects PLL or PLL-bypass (test mode) operation Selects primary reference clock source 3 xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 TABLE 1: CONTROL INPUT FUNCTION TABLE PIN NAME 0 1 DEFAULT REF_SEL PECL clock inputs selected as reference TCLK input selected as reference 0 PLL_EN PLL is bypassed. Test Mode. TCLK reference source drives the divider select blocks PLL enabled. Normal operation. VCO output drives the divider select blocks 1 SELA Bank A divider = 2 Bank A divider = 4 0 SELB Bank B divider = 4 Bank B divider = 8 0 SELC Bank C divider = 4 Bank C divider = 8 0 SELD Bank D divider = 4 Bank D divider = 8 0 OE Outputs enabled Outputs tri-stated, VCO running at minimum frequency 0 DC C HARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) SYMBOL CHARACTERISTICS M IN TYP MAX UNIT VCMRa PECL Clock inputs common mode range 1.2 VCC-0.9 V VPP PECL Clock peak-to-peak input voltage 500 1000 mV VIH Input voltage high 2.0 VCC+0.3 V VIL Input voltage low 0.8 V VOH Output High Voltagea VOL Output Low Voltagea ZOUT IIN ICC_PLL 2.4 0.55 0.30 Output Impedance Maximum PLL supply current ICC Maximum Quiescent supply current VTT Output Termination Voltage 3.0 VCC÷2 a. VCMR is the cross point of the differential input signal. 4 V IOH=-24mA V V IOL=24mA IOL=12mA Ω 14-17 Input leakage current CONDITION +150 μΑ VIN =V CC or VIN =GND 5.0 mA AVCC pin 4 mA All VCCQX pins V xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 . AC C HARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) a SYMBOL fVCO fref PARAMETER MIN VCO Frequency TYP MAX UNIT 200 400 MHz Input Reference Frequency ÷2 feedback ÷4 feedback ÷8 feedback PLL Bypass 100 50 25 2 200 100 50 300 MHz fMAX Max Output Frequency ÷2 feedback ÷4 feedback ÷8 feedback 100 50 25 200 100 50 MHz tir/tif Input Rise/Fall time 1.0 ns frefDC tpd tskew Input Clock duty cycle 25 75 % Propagation Delay - (SPO, Input clock to FB) TCLK to FB_IN PECL to FB_IN -50 -25 150 325 ps ps 150 ps Output-to-Output Skew CONDITION PLL_EN PLL_EN PLL_EN PLL_EN =1 =1 =1 =0 0.8 to 2.0V PLL Locked PLL Locked tJIT(CC) Cycle-to-Cycle Jitter (RMS) ÷4 feedback 10 22 ps All outputs set to ÷4 tJIT(PER) Period Jitter (RMS) ÷4 feedback 8 15 ps All outputs set to ÷4 tJIT(I/O) I/O Phase Jitter (RMS) BW PLL bandwidth ÷2 feedback ÷4 feedback ÷8 feedback DC Output duty cycle ÷2 feedback ÷4 feedback ÷8 feedback 4 - 17 ps 9.0-20.0 3.0-9.5 1.2-2.1 MHz MHz MHz 45 47.5 48.75 50 50 50 55 52.5 51.75 % % % 1.0 ms 1000 ps tLOCK Maximum PLL Lock Time tor/tof Output Rise/Fall time tPLZ,HZ Output Disable Time 10 ns tPHZ,LZ Output Enable Time 10 ns 100 a. AC characteristics apply for parallel output termination of 50Ω to VTT. 5 100 - 200MHz 50 - 100MHz 25 - 50MHz 0.55 to 2.4V xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 DC C HARACTERISTICS (VCC= 2.5 + 5%, TA= -40°C TO +85°C) SYMBOL CHARACTERISTICS MIN TYP MAX UNIT VCMRa PECL Clock inputs common mode range 1.2 VCC-0.6 V VPP PECL Clock peak-to-peak input voltage 500 1000 mV VIH Input voltage high 1.7 VCC+0.3 V VIL Input voltage low 0.7 V VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN ICC_PLL 1.8 0.6 Maximum PLL supply current ICC Maximum Quiescent supply current VTT Output Termination Voltage 3.0 VCC÷2 a. VCMR is the cross point of the differential input signal. 6 V IOH=-15mA V IOL=15mA Ω 17-20 Input leakage current CONDITION +150 μΑ VIN =VCC or VIN=GND 5.0 mA AVCC pin 1 mA All VCCQX pins V xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 . AC C HARACTERISTICS (VCC= 2.5 + 5%, TA= -40°C TO +85°C) a SYMBOL fVCO fref PARAMETER MIN VCO Frequency TYP MAX UNIT 200 400 MHz Input Reference Frequency ÷2 feedback ÷4 feedback ÷8 feedback PLL Bypass 100 50 25 200 100 50 MHz fMAX Max Output Frequency ÷2 feedback ÷4 feedback ÷8 feedback 100 50 25 200 100 50 MHz tir/tif Input Rise/Fall time 1.0 ns 25 75 % -100 0 100 300 ps ps 150 ps frefDC tpd tskew Input Clock duty cycle Propagation Delay - (SPO, Input clock to FB) TCLK to FB_IN PECL to FB_IN Output-to-Output Skew CONDITION PLL_EN PLL_EN PLL_EN PLL_EN =1 =1 =1 =0 0.7 to 1.7V PLL Locked PLL Locked tJIT(CC) Cycle-to-Cycle Jitter (RMS) ÷4 feedback 10 22 ps All outputs set to ÷4 tJIT(PER) Period Jitter (RMS) ÷4 feedback 8 15 ps All outputs set to ÷4 tJIT(I/O) I/O Phase Jitter (RMS) BW PLL bandwidth ÷2 feedback ÷4 feedback ÷8 feedback DC Output duty cycle ÷2 feedback ÷4 feedback ÷8 feedback 6 - 25 ps 4.0-15.0 2.0-7.0 0.7-2.0 MHz MHz MHz 45 47.5 48.75 50 50 50 55 52.5 51.75 % % % 1.0 ms 1000 ps tLOCK Maximum PLL Lock Time tor/tof Output Rise/Fall time tPLZ,HZ Output Disable Time 12 ns tPHZ,LZ Output Enable Time 12 ns 100 a. AC characteristics apply for parallel output termination of 50Ω to VTT. 7 100 - 200MHz 50 - 100MHz 25 - 50MHz 0.6 to 1.8V xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 ABSOLUTE MAXIMUM RATINGSa SYMBOL CHARACTERISTICS MIN M AX UNIT VCC Supply Voltage -0.3 4.6 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V DC Input Current +20 mA DC Output Current +50 mA 150 °C VOUT IIN IOUT TS Storage Temperature -55 CONDITION a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. GENERAL SPECIFICATIONS SYMBOL CHARACTERISTICS MIN TYP MAX UNIT VTT Output termination voltage MM ESD Protection (Machine model) 200 V HBM ESD Protection (Human body model) 2000 V LU Latch-up immunity 200 mA CIN Input Capacitance θJA Thermal resistance junction to ambient JESD 51-3, single layer test board 62.0 °C/W JESD 51-6, multi layer test board 47 °C/W Thermal resistance junction to case 14 °C/W Operating junction temperature 115 °C θJC VCC÷2 CONDITION V 4.0 pF Inputs Natural convection FIGURE 3. OUTPUT-TO-OUTPUT SKEW tSK(O) VCC VCC÷2 GND VCC VCC÷2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. 8 xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 FIGURE 4. PROPOGATION DELAY (t(Ø), STATIC PHASE OFFSET) TEST REFERENCE VCC CCLKx VCC÷2 GND VCC VCC÷2 FB_IN GND t(Ø) FIGURE 5. OUTPUT DUTY C YCLE (DC) VCC VCC÷2 GND tp T0 DC=tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage FIGURE 6. I/O JITTER CCLKx FB_IN TJIT(I/O) = |T0-T1mean | The deviation in t0 for a controlled edge with respect to a t 0 mean in a random sample of cycles FIGURE 7. CYCLE-TO-CYCLE JITTER TN TN+1 TJIT(CC)= |TN-TN+1 | The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs 9 xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 FIGURE 8. PERIOD JITTER T0 TJIT(Per)= |TN-1/f0 | The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles FIGURE 9. OUTPUT TRANSITION TIME TEST R EFERENCE VCC=3.3V VCC=2.5V tor tof 10 2.4V 1.8V 0.55V 0.6V xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 PACKAGE DIMENSIONS 32 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.4 mm TQFP) rev. 2.00 D D1 24 17 16 25 D1 32 D 9 1 8 B e A2 C A α Seating Plane A1 L Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.055 0.063 1.40 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.012 0.018 0.30 0.45 C 0.004 0.008 0.09 0.20 D 0.346 0.362 8.80 9.20 D1 0.272 0.280 6.90 7.10 e 0.0315 BSC 0.80 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° 11 xr XRK39351 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER REV. 1.0.0 REVISION HISTORY REVISION # 1.0.0 DATE DESCRIPTION November 2006 Initial FINAL release. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet November 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 12