EXAR XRK4991AIJ-7

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PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
FEBRUARY 2005
REV. P1.0.2
FUNCTIONAL DESCRIPTION
The XRK4991A 3.3V High-Speed Low-Voltage
Programmable Skew Clock Buffer offers user
selectable control over system clock functions to
optimize the timing of high-performance computer
systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified
output skews and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or
function configurations. Delay increments of 0.7 to
1.5 ns are determined by the operating frequency
with outputs able to skew up to ±6 time units from
their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission
line delay effects to be canceled. When this “zero
delay” capability is combined with the selectable
output skew functions, the user can create output-tooutput delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are
provided for additional flexibility in designing complex
clock systems. When combined with the internal PLL,
these divide functions allow distribution of a lowfrequency clock that can be multiplied by two or four
at the clock destination. This feature minimizes clock
distribution difficulty while allowing maximum system
clock speed and flexibility.
FEATURES
• Ref input is 5V tolerant
• 3 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable
positive
or
negative
edge
synchronization: Excellent for DSP applications
• Synchronous output enable
• Output frequency: 3.75MHz to 85MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 2 skew grades
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• 32-pin PLCC package
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
• Green packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK4991A
TEST
PE
FB_IN PHASE
CLKIN
FREQ
DET
FILTER
VCO AND TIME
UNIT GENERATOR
0E
FSEL
QD0
SELD0
SELD1
QD1
Select Inputs
SELC0
SKEW
QC0
SELC1
SELECT
QC1
SELB0
SELB1
QB0
MATRIX
QB1
SELA0
QA0
SELA1
QA1
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRK4991A
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
ACCURACY
OPERATING TEMPERATURE RANGE
XRK4991AIJ-5
500 ps
-40°C to +85°C
XRK4991ACJ-5
500 ps
0°C to +70°C
XRK4991ACJ-7
750 ps
0°C to +70°C
XRK4991AIJ-7
750 ps
-40°C to +85°C
SELC0
FSEL
VCCQ
CLKIN
GND
TEST
SELB1
FIGURE 2. PIN OUT OF THE XRK4991
4
3
2
1
32
31
30
SELC1
5
29
SELB0
SELD0
6
28
OE
SELD1
7
27
SELA1
PE
8
26
1F0
VCCN
9
25
VCCN
QD1
10
24
QA0
QDO
11
23
QA1
GND
12
22
GND
GND
13
21
GND
14
15
16
17
18
19
20
QD1
QC0
VCCN
FB_IN
VCCN
QB1
QB0
XRK4991A
2
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PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
PIN DESCRIPTIONS
PIN NAME
PIN #
TYPE
DESCRIPTION
CLKIN
1
I
Reference frequency input. This input supplies the frequency and timing against
which all functional variation is measured.
FB_IN
17
I
PLL feedback input (typically connected to one of the eight outputs).
FSEL
3
I
Three-level frequency range select. Set Table 2.
SELA0
SELA1
26
27
I
Three-level function selects inputs for output pair 1 (QA0, QA0]). Table 3.
SELB0
SELB1
29
30
I
Three-level function selects inputs for output pair 2 (QB0, QB1). Table 3.
SELC0
SELC1
4
5
I
Three-level function selects inputs for output pair 3 (QC0, QC1). See Table 3.
SELD0
SELD1
7
1
I
Three-level function selects inputs for output pair 4 (QD0, QD1). See Table 3.
TEST
31
I
Three-level select. See test mode section under the block diagram descriptions.
OE
28
I
Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0])
in a "Low" state - QC[1:0] may be used as the feedback signal to maintain phase
lock. When TEST is held at MID level and OE is "High", the nF[1:0] pins act as
output disable controls for individual banks when nF[1:0] = LL. Set OE "Low" for
normal operation.
PE
8
I
Selectable positive or negative edge control. When "Low"/"High" the outputs are
synchronized with the negative/positive edge of the reference clock.
QA0
QA1
24
23
O
Output pair 1. See Table 2.
QB0
QB1
20
19
O
Output pair 2. See Table 2.
QC0
QC1
15
14
O
Output pair 3. See Table 2.
QD0
QD1
11
10
O
Output pair 4. See Table 2.
VCCN
9
16
18
25
PWR
Power supply for output drivers.
VCCQ
2
PWR
Power supply for internal circuitry.
GND
12
13
21
22
32
PWR
Ground.
3
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XRK4991A
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
EXTERNAL FEEDBACK
By providing external feedback, the XRK4991A gives users flexibility with regard to skew adjustment. The
FB_IN signal is compared with the input CLKIN signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO to adjust upwards or downwards accordingly. An internal loop filter moderates the
response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide
minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
TABLE 1: PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FSEL = LOW
FSEL = MID
FSEL = HIGH
Timing Unit Calculation (tU)
1/(44 x FNOM)
1/(26 x FNOM)
1/(16 x FNOM)
VCO Frequency Range (FNOM) (1,2)
15 to 35MHz
25 to 60MHz
40 to 100MHz
+9.09ns
+9.23ns
+9.38ns
ns
+49°
+83°
+135°
Phase Degrees
+14%
+23%
+37%
% of Cycle Time
Skew Adjustment Range (3)
Max Adjustment:
Example 1, FNOM = 15MHz
tU = 1.52ns
Example 2, FNOM = 25MHz
tU = 0.91ns
tU = 1.54ns
Example 3, FNOM = 30MHz
tU = 0.76ns
tU = 1.28ns
Example 4, FNOM = 40MHz
tU = 0.96ns
tU = 1.56ns
Example 5, FNOM = 50MHz
tU = 0.77ns
tU = 1.25ns
Example 6, FNOM = 80MHz
COMMENTS
tU = 0.78ns
NOTES:
1.
The device may be operated outside recommended frequency ranges without damage, but functional operation is
not guaranteed. Selecting the appropriate FSEL value based on input frequency range allows the PLL to operate
in its ‘sweet spot’ where jitter is lowest.
2.
The level to be set on FSEL is determined by the nominal operating frequency of the VCO and Time Unit
Generator. The VCO frequency always appears at QA[1:0], QB[1:0] and the higher outputs when they are
operated in their undivided modes. The frequency appearing at the CLKIN and FB_IN inputs will be the same as
the VCO when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be
1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output
as the FB_IN input.
3.
Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for
feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other
outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’
range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
4
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PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
TABLE 2: FREQUENCY RANGE SELECT AND tU CALCULATION [1]
fNOM (MHZ)
tU = 1 / fNOM X N
APPROXIMATE
FREQUENCY (MHZ) AT
FSEL[2,3]
MIN
MAX
LOW
15
30
44
22.7
MID
25
50
26
38.5
HIGH
40
85
16
62.5
WHERE
N=
WHICH tU
= 1.0ns
SKEW SELECT MATRIX
The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout
drivers (Qx[0:1]), and two corresponding three-level function select (SELx[0:1]) inputs. Table 2 below shows
the nine possible output functions for each section as determined by the function select inputs. All times are
measured with respect to the CLKIN input assuming that the output connected to the FB_IN input has 0tU
selected.
TABLE 3: PROGRAMMABLE SKEW CONFIGURATIONS [1]
FUNCTION SELECTS
OUTPUT FUNCTIONS
SELX1
SELX0
QA[1:0], QB[1:0]
QC[1:0]
QD[1:0]
LOW
LOW
-4tU
Divide by 2
Divide by 2
LOW
MID
-3tU
-6tU
-6tU
LOW
HIGH
-2tU
-4tU
-4tU
MID
LOW
-1tU
-2tU
-2tU
MID
MID
0tU
0tU
0tU
MID
HIGH
+1tU
+2tU
+2tU
HIGH
LOW
+2tU
+4tU
+4tU
HIGH
MID
+3tU
+6tU
+6tU
HIGH
HIGH
+4tU
Divide by 4
Inverted
NOTES:
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID
indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2.
2.
The level to be set on FSEL is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit
Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at QA0 and the other outputs
when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN
inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN
inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output
as the FB_IN input.
3.
When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached
2.8V.
5
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XRK4991A
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
t0+6tU
t0+5tU
t0+4tU
t0+3tU
t0+2tU
t0+1tU
t0
t0-1tU
t0-2tU
t0-3tU
t0-4tU
t0-5tU
t0-6tU
FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT [4]
FB_IN
SELA-QA[1:0] SELC-QC[1:0] CLKIN
SELB-QB[1:0] SELD-QD[1:0]
-6tU
(N/A)
LM
-4tU
LL
LH
-3tU
LM
(N/A)
-2tU
LH
ML
-1tU
ML
(N/A)
0tU
MM
MM
+1tU
MH
(N/A)
+2tU
HL
MH
+3tU
HM
(N/A)
+4tU
HH
HL
+6tU
(N/A)
HM
(N/A)
LL/HH DIVIDED
(N/A)
HH
INVERT
NOTES:
4.
FB_IN connected to an output selected for "zero" skew (i.e. SELx1 = SELx0 = MID).
TEST MODE
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the
XRK4991 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a
removable jumper to ground, or be tied LOW through a 100Ω resistor. This will allow an external tester to
change the state of these pins.)
If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop
disconnected, and input levels supplied to CLKIN will directly control all outputs. Relative output to output
functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of
their own function select inputs (SELx[1:0]) and the waveform characteristics.
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PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (5)
Storage Temperature
–65°C to +150°C
Ambient Temperature with Power Applied
–55°C to +125°C
Supply Voltage to Ground
–0.5V to +7.0V
DC Input Voltage
–0.5V to +7.0V
Output Current into Outputs (LOW)
64 mA
Static Discharge Voltage (per MIL-STD-883, Method 3015)
>2001V
Latch-Up Current.
>200 mA
NOTES:
5.
Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
TABLE 4: DC ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
CONDITION
VIH
Input HIGH Voltage
(CLKIN, FB_IN, OE, PE)
2.0
VCC
V
Guaranteed Logic HIGH
(CLKIN, FB_IN, OE, PE Inputs Only)
VIL
Input LOW Voltage
(CLKIN, FB_IN, OE, PE)
0.8
V
Guaranteed Logic LOW
(CLKIN, FB_IN, OE, PE Inputs Only)
VCC-0.6
VCC
V
3-Level Inputs Only
VCC/2-0.3
VCC/2/+0.3
V
3-Level Inputs Only
3-Level Inputs Only
VIHH
Three-Level Input HIGH Voltage [6]
VIMM
Three-Level Input MID Voltage [6]
VILL
Three-Level Input LOW Voltage [6]
0.6
V
IIN
Input Leakage Current
(CLKIN and FB_IN inputs only)
±5
µΑ
VCC = Max.
I3
3-Level Input DC Current
(TEST, FSEL)
±200
µΑ
VIN = VCC
HIGH Level
±50
µΑ
VIN = VCC/2
MID Level
±200
µΑ
VIN = GND
LOW Level
VIN = VCC or GND
IIPU
Input Pull-Up Current (PE)
±100
µΑ
VCC = Max
VIN = GND
IIPD
Input Pull-Down Current (OE)
±100
µA
VCC = Max
VIN = VCC
VOH
Output HIGH Voltage
V
VCC = Min., IOH = -12mA
VOL
Output LOW Voltage
V
VCC = Min., IOL = 12mA
2.4
0.55
NOTES:
6.
These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected
inputs to VCC/2. If these inputs are switched (during operation), the function and timing of the outputs may be
glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
7
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XRK4991A
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
TABLE 5: POWER REQUIREMENTS (VCC = 3.3V + 10% OPERATING RANGE)
SYMBOL
ICCQ
PARAMETER
TEST CONDITIONS
Quiescent Power Supply Current
VCC=Max., TEST=MID, CLKIN=LOW
TYP
MAX.
UNIT
8
25
mA
PE=LOW, OE=LOW,
All outputs unloaded
∆ICC
Power Supply Current per Input HIGH
VCC = Max., VIN = 3V
1
30
µA
ICCD
Dynamic Power Supply Current per Output
VCC = Max., CL = 0pF
55
90
µA/MHz
ITOT
Total Power Supply Current
VCC=3.3V, FCLKIN=20MHz,
29
mA
(1)
CL=160pF
VCC=3.3V, FCLKIN=33MHz,
42
(1)
CL=160pF
VCC=3.3V, FCLKIN=66MHz,
76
CL=160pF(1)
NOTE: (1) For eight outputs, each loaded with 20pF.
TABLE 6: INPUT TIMING REQUIREMENTS
DESCRIPTION(1)
SYMBOL
MIN.
MAX.
UNIT
10
ns/V
tR, tF
Maximum input rise and fall times, 0.8V to 2V
tPWC
Input clock pulse, HIGH or LOW
3
Input duty cycle
10
90
%
3.75
85
MHz
DH
CLKIN
Reference Clock Input
NOTE: (1) Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
8
ns
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PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
TABLE 7: SWITCHING CHARACTERISTICS (3.3V + 10% OPERATING RANGE)
SYMBOL
XRK4991A-2
PARAMETER
MIN
TYP
MAX
XRK4991A-5
MIN
TYP
MAX
XRK4991A-7
MIN
TYP
MAX
UNIT
FNOM
VCO Frequency Range
tRPWH
CLKIN Pulse Width HIGH(11)
3
3
3
ns
tRPWL
CLKIN Pulse Width LOW(11)
3
3
3
ns
tu
See PLL Programmable Skew Range and Resolution Table
Programmable Skew Time Unit
See Control Summary Table
tSKEWPR Zero Output Matched-Pair Skew (Qx[1:0])
0.05
0.2
0.1
0.25
0.1
0.25
ns
[1,2,3]
tSKEW0
Zero Output Skew (All Outputs) [1, 4]
0.1
0.25
0.25
0.5
0.3
0.75
ns
tSKEW1
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs [1, 6]
0.25
0.5
0.6
0.7
0.6
1
ns
tSKEW2
Output Skew (Rise-Fall, Divided-Divided)
0.3
1.2
0.5
1.2
1
1.5
ns
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) [1, 6]
0.25
0.5
0.5
0.7
0.7
1.2
ns
tSKEW4
Output Skew
0.5
0.9
0.5
1
1.2
1.7
ns
1.65
ns
[1, 6]
(Rise-Fall, Nominal-Divided,
[1, 2]
tDEV
Device-to-Device Skew [1, 2, 7]
tPD
CLKIN Input to FB_IN Propagation Delay
tODCV
Output Duty Cycle Variation from 50% [1]
tPWH
Output HIGH Time Deviation from 50% [1,
0.75
1.25
-0.25
0
0.25
-0.5
0
0.5
-0.7
0
0.7
ns
-1.2
0
1.2
-1.2
0
1.2
-1.2
0
1.2
ns
[1, 9]
2
2.5
3
ns
1.5
3
3.5
ns
10]
tPWL
Output LOW Time Deviation from 50%
[1,11]
tORISE
Output Rise Time [1]
0.15
1
1.2
0.15
1
1.8
0.15
1.5
2.5
ns
tOFALL
Output Fall Time [1]
0.15
1
1.2
0.15
1
1.8
0.15
1.5
2.5
ns
tLOCK
PLL Lock Time [1,8]
tJR
Cycle-to-Cycle Output
Jitter [1]
0.5
0.5
0.5
ns
RMS
25
25
25
ps
Peak-to-Peak
200
200
200
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been
selected when all are loaded with the specified load.
3. tSKEWPR is the skew between a pair of outputs (Qx[1:0]) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
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XRK4991A
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
5.
For XRK4993-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.
6.
There are 2 classes of outputs: Nominal (multiple of tU delay), and Divided (QC[1:0] only in Divide-by-2 or Divide-by-4
mode).
7.
tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature,
air flow, etc.)
8.
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and
within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or
FB_IN until tPD is within specified limits.
9.
tPD is measured with CLKIN input rise and fall times (from 0.8V to 2V) of 1ns.
10.
Measured at 2V.
11.
Measured at 0.8V.
FIGURE 4. AC TEST LOADS AND WAVEFORMS
VCC
150Ω
Output
150Ω
20pF
tOFALL
tORISE
tPWH
2.0V
0.8V
tPWL
LVTTL Output Waveform
<1ns
3.0V
2.0V
Vth = 1.5V
0.8V
0V
LVTTL Input Test Waveform
10
<1ns
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PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
FIGURE 5. AC TIMING DIAGRAM
tREF
tRPWH
tRPWL
CLKIN
tPD
tODCV
tODCV
FB_IN
tJR
Any Q
tSKEWPR,
tSKEW0, 1
tSKEWPR,
tSKEW0, 1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3, 4
tSKEW3, 4
tSKEW3, 4
CLKIN DIVIDED BY 2
tSKEW1, 3, 4
tSKEW2, 4
CLKIN DIVIDED BY 4
NOTES:
1.
PE: The AC Timing Diagram applies to PE=VCC. For PE=GND, the negative edge of FB_IN aligns with the
negative edge of CLKIN, divided outputs change on the negative edge of CLKIN, and the positive edges of the
divide-by-2 and the divide-by-4 signals align.
2.
Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay
has been selected when all are loaded with 20pF and terminated with 75Ω to VCC/2.
3.
tSKEWPR: The skew between a pair of outputs (Qx[1:0]) when all eight outputs are selected for 0tU.
4.
tSKEW0: The skew between outputs when they are selected for 0tU.
5.
tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient
temperature, air flow, etc.)
6.
tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and
tSKEW4 specifications.
7.
tPWH is measured at 2V.
8.
tPWL is measured at 0.8V.
9.
tORISE and tOFALL are measured between 0.8V and 2V.
10.
tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at CLKIN or FB_IN until tPD is within specified limits.
11
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XRK4991A
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
PACKAGE DIMENSIONS
32 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
D
A1
D1
A2
30° x H1
2
1
32
45° x H2
B1
Corner Chamfer
E1
E3
B
E
D2
e
7°±2 deg typ.
C
D3
R
A
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.120
0.140
3.05
3.56
A1
0.075
0.095
1.91
2.41
A2
0.020
--0.51
--B
0.013
0.021
0.33
0.53
B1
0.026
0.032
0.66
0.81
C
0.008
0.013
0.19
0.32
D
0.485
0.495
12.33
12.58
D1
0.448
0.454
11.39
11.54
D2
0.400
0.440
10.17
11.18
0.300 typ.
7.62 typ.
D3
E
0.585
0.595
14.87
15.11
E1
0.545
0.557
13.85
14.15
E2
0.500
0.540
12.71
13.72
E3
0.400 typ.
10.16 typ.
e
0.050 BSC
1.27 BSC
H1
0.023
0.029
0.58
0.74
H2
0.042
0.048
1.07
1.22
R
0.025
0.045
0.64
1.14
Note: The control dimension is in inches.
12
SEATING PLANE
xr
PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
REV. P1.0.2
REVISION HISTORY
REVISION #
P1.0.0
P1.0.1
P1.0.2
DATE
DESCRIPTION
February 2004 Initial release
July 2004
Update block diagram.
February 2005 Renamed pins to Exar convention., removed reference to 2.5V operation. Made edits
to text.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2004 EXAR Corporation
Datasheet February 2005.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
13