54ABT16374 16-Bit D Flip-Flop with TRI-STATE ® Outputs General Description Features The ABT16374 contains sixteen non-inverting D flip-flops with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. Separate control logic for each byte 16-bit version of the ABT374 Edge-triggered D-type inputs Buffered Positive edge-triggered clock High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Guaranteed latch-up protection n Standard Microcircuit Drawing (SMD) 5962-9320101 n n n n n Ordering Code: Commercial Package Package Description Number 54ABT16374W-QML WA48A 48-Lead Cerpack Connection Diagram Logic Symbol Pin Assignment for Cerpack DS100224-1 Pin Description Pin Description Names OEn TRI-STATE Output Enable Input (Active Low) CPn Clock Pulse Input (Active Rising Edge) D0–D15 Data Inputs O0–O15 TRI-STATE Outputs DS100224-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS100224 www.national.com 54ABT16374 16-Bit D Flip-Flop with TRI-STATE Outputs July 1998 54ABT16374 Functional Description Truth Tables The ABT16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Inputs Outputs CP1 OE1 D0–D7 O0–O7 N L H H N L L L L L X (Previous) X H X Z CP2 OE2 D8–D15 O8–O15 N L H H N L L L L L X (Previous) X H X Z Inputs Outputs H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance Logic Diagrams Byte 1 (0:7) DS100224-3 Byte 2 (8:15) DS100224-4 www.national.com 2 Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) −65˚C to +150˚C −55˚C to +125˚C −55˚C to +175˚C −350 mA −500 mA 10V Recommended Operating Conditions −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −0.5V to 5.5V −0.5V to VCC twice the rated IOL (mA) −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter ABT16374 Units VCC Conditions Min Typ Max VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current 2.0 V 0.8 V −1.2 V Recognized HIGH Signal Recognized LOW Signal Min IIN = −18 mA 54ABT 2.5 V Min IOH = −3 mA 54ABT 2.0 V Min IOH = −24 mA 0.55 V Min IOL = 48 mA 5 µA Max VIN = 2.7V (Note 4) 54ABT 5 VIN = VCC IBVI Input HIGH Current Breakdown Test 7 µA Max VIN = 7.0V IIL Input LOW Current −5 µA Max VIN = 0.5V (Note 4) VID Input Leakage Test V 0.0 IID = 1.9 µA −5 4.75 VIN = 0.0V All Other Pins Grounded IOZH Output Leakage Current 50 µA 0−5.5V VOUT = 2.7V; OE = 2.0V IOZL Output Leakage Current −50 µA 0−5.5V VOUT = 0.5V; OE = 2.0V IOS Output Short-Circuit Current −275 mA Max VOUT = 0.0V ICEX Output High Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others VCC or GND ICCH Power Supply Current 2.0 mA Max All Outputs HIGH ICCL Power Supply Current 62 mA Max All Outputs LOW ICCZ Power Supply Current Max OE = VCC; All Others at VCC or GND Max Enable Input VI = VCC − 2.1V ICCT Additional ICC/Input −100 2.0 mA Outputs Enabled 2.5 mA Outputs TRI-STATE 2.5 mA Outputs TRI-STATE 2.5 mA VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 4) 0.30 MHz Max Outputs Open OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8-bit toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested. 3 www.national.com 54ABT16374 Absolute Maximum Ratings (Note 1) 54ABT16374 DC Electrical Characteristics Conditions Symbol Parameter Min Max Units VCC CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 1.1 V 5.0 TA = 25˚C (Note 5) VOLV Quiet Output Minimum Dynamic VOL -0.45 V 5.0 TA = 25˚C(Note 5) Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. AC Electrical Characteristics 54ABT TA = −55˚C to +125˚C Symbol VCC = 4.5V to 5.5V Parameter Units CL = 50 pF Min fmax Max Clock Max 150 MHz Frequency tPLH Propagation Delay tPHL CP to On 1.5 6.9 tPZH Output Enable Time 0.8 6.5 1.2 6.5 1.5 9.6 1.5 7.2 1.5 tPZL tPHZ Output Disable Time tPLZ 6.9 ns ns ns AC Operating Requirements 54ABT TA = −55˚C to +125˚C Symbol Parameter VCC = 4.5V to 5.5V Units CL = 50 pF Min ts(H) Setup Time, HIGH 1.3 ts(L) or LOW Dn to CP 1.3 th(H) Hold Time, HIGH 1.5 th(L) or LOW Dn to CP 1.5 tw(H) Pulse Width, CP 3.3 tw(L) HIGH or LOW 3.3 Max ns ns ns Capacitance Symbol Parameter Typ Units Conditions (TA = 25˚C) CIN Input Capacitance 5.0 pF VCC = 0V COUT (Note 6) Output Capacitance 11.0 pF VCC = 5.0V Note 6: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 4 54ABT16374 AC Loading DS100224-6 *Includes jig and probe capacitance DS100224-10 FIGURE 1. Standard AC Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100224-7 FIGURE 2. Propagation Delay Waveforms for Inverting and Non-Inverting Functions DS100224-11 FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms DS100224-8 FIGURE 3. Test Input Pulse Requirements DS100224-12 Amplitude Rep Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 7. TRI-STATE Output HIGH and LOW Enable and Disable Times FIGURE 4. Test Input Signal Requirements 5 www.national.com 54ABT16374 16-Bit D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Cerpack NS Package Number WA48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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