54AC821 • 54ACT821 10-Bit D Flip-Flop with TRI-STATE ® Outputs General Description The ’AC/’ACT821 is a 10-bit D flip-flop with TRI-STATE outputs arranged in a broadside pinout. The ’AC/’ACT821 is functionally identical to the AM29821. Features n n n n Noninverting outputs Outputs source/sink 24 mA ’ACT821 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’ACT821: 5962-88705 — ’AC821: 5962-91606 n TRI-STATE outputs for bus interfacing Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100355-1 IEEE/IEC DS100355-3 Pin Assignment for LCC DS100355-2 Pin Names Description D0–D9 Data Inputs O0–O9 Data Outputs OE Output Enable Input CP Clock Input DS100355-4 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100355 www.national.com 54AC821 • 54ACT821 10-Bit D Flip-Flop with TRI-STATE Outputs August 1998 Functional Description The ’AC/’ACT821 consists of ten D-type edge-triggered flip-flops. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ’AC/’ACT821 is functionally and pin compatible with the AM29821. Function Table Inputs OE CP D Internal Outputs Q O Function H N L L Z High Z H N H H Z High Z L N L L L Load L N H H H Load H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance N = LOW-to-HIGH Clock Transition Logic Diagram DS100355-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. 175˚C DC Characteristics for ’AC Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC (V) 54AC TA = −55˚C to +125˚C Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 Maximum Input Units Conditions Guaranteed Limits VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOL = 12 mA 3.0 0.50 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA 5.5 ± 10.0 µA V IOL = 24 mA IOL = 24 mA VI = VCC, GND Leakage Current IOZ Maximum TRI-STATE Current 3 VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND www.national.com DC Characteristics for ’AC Family Devices Symbol IOLD Parameter (Note 3) VCC (V) (Continued) 54AC TA = −55˚C to +125˚C Units Conditions Guaranteed Limits 5.5 50 mA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Minimum Dynamic IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 160.0 µA Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC 54ACT TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input Units Conditions V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 5) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 5) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA 5.5 ± 10.0 µA VI = VIL, VIH VO = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V 5.5 50 mA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Leakage Current IOZ Maximum TRI-STATE Current ICCT Maximum ICC/Input IOLD (Note 6) Minimum Dynamic IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 160.0 µA Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. www.national.com 4 AC Electrical Characteristics Symbol Parameter 54AC TA = −55˚C to +125˚C CL = 50 pF VCC (V) (Note 8) fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Min Maximum Clock 3.3 95 Frequency 5.0 100 Units Fig. No. Max MHz Propagation Delay 3.3 1.0 13.0 CP to On 5.0 1.5 9.5 Propagation Delay 3.3 1.0 13.0 CP to On 5.0 1.5 9.5 Output Enable Time 3.3 1.0 13.0 OE to On 5.0 1.5 9.5 Output Enable Time 3.3 1.0 13.0 OE to On 5.0 1.5 9.5 Output Disable Time 3.3 1.0 12.0 OE to On 5.0 1.5 10.0 Output Disable Time 3.3 1.0 12.0 OE to On 5.0 1.5 10.0 ns ns ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Note 9: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements (V) 54AC TA = −55˚C to +125˚C CL = 50 pF (Note 10) Guaranteed Minimum Setup Time, HIGH or LOW 3.3 3.0 Dn to CP 5.0 3.0 Symbol ts th tw Parameter VCC Hold Time, HIGH or LOW 3.3 3.0 Dn to CP 5.0 3.0 CP Pulse Width 3.3 6.0 HIGH or LOW 5.0 5.0 Units Fig. No. ns ns ns Note 10: Voltage Range 3.3 is 3.3V ± 0.3V Note 11: Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) (Note 12) Min fmax Maximum Clock Fig. to +125˚C CL = 50 pF Units No. Max 5.0 85 MHz 5.0 1.5 11.5 ns 5.0 1.5 11.5 ns 5.0 1.5 12.5 ns Frequency tPLH Propagation Delay CP to On tPHL Propagation Delay CP to On tPZH Output Enable Time OE to On 5 www.national.com AC Electrical Characteristics (Continued) 54ACT TA = −55˚C VCC Symbol Parameter (V) (Note 12) tPZL Output Enable Time Fig. to +125˚C CL = 50 pF Units Min Max 5.0 1.5 13.0 ns 5.0 1.5 13.5 ns 5.0 1.5 12.5 ns No. OE to On tPHZ Output Disable Time OE to On tPLZ Output Disable Time OE to On Note 12: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 13) Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 4.0 ns 5.0 3.0 ns 5.0 6.0 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP tw CP Pulse Width HIGH or LOW Note 13: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 35.0 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 28 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24 Lead Slim (0.300" Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 7 www.national.com 54AC821 • 54ACT821 10-Bit D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24 Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.