54ACTQ821 Quiet Series 10-Bit D Flip-Flop with TRI-STATE ® Outputs General Description Features The ACTQ821 is a 10-bit D flip-flop with non-inverting TRI-STATE outputs arranged in a broadside pinout. The ACTQ821 utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. n Guaranteed simultaneous switching noise level and dynamic threshold performance n Non-inverting TRI-STATE outputs for bus interfacing n 4 kV minimum ESD immunity n Outputs source/sink 24 mA n Functionally identical to the AM29821 Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100247-1 IEEE/IEC DS100247-3 Pin Assignment for LCC DS100247-2 Pin Names Description D0–D9 Data Inputs O0–O9 Data Outputs OE Output Enable Input CP Clock Input DS100247-4 GTO™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100247 www.national.com 54ACTQ821 Quiet Series 10-Bit D Flip-Flop with TRI-STATE Outputs August 1998 Functional Description The ACTQ821 consists of ten D-type edge-triggered flip-flops. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ACTQ821 is functionally and pin compatible with the AM29821. Function Table Inputs OE CP D Internal Outputs Q O Function H N L L Z H N H H Z High Z L N L L L Load L N H H H Load High Z H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance N = LOW-to-HIGH Clock Transition Logic Diagram DS100247-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) DC Latch-Up Source or Sink Current Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) −0.5V to +7.0V ± 300 mA 175˚C Recommended Operating Conditions −20 mA +20 mA −0.5V to VCC + 0.5V Supply Voltage (VCC) ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACTQ Minimum Input Edge Rate ∆V/∆t ’ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 2: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C. DC Electrical Characteristics for ’ACTQ Family Devices Symbol Parameter VCC 54ACTQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 3) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 3) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA 5.5 ± 10.0 µA VI = VIL, VIH VO = VCC, GND Leakage Current IOZ Maximum TRI-STATE Leakage Current ICCT Maximum ICC/Input 5.5 1.6 mA IOLD (Note 4) Minimum Dynamic Output Current 5.5 50 mA VI = VCC − 2.1V VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min IOHD 3 www.national.com DC Electrical Characteristics for ’ACTQ Family Devices Symbol Parameter VCC 54ACTQ TA = (V) −55˚C to +125˚C (Continued) Units Conditions Guaranteed Limits ICC Maximum Quiescent µA VIN = VCC 5.0 V (Notes 6, 7) 5.0 V (Notes 6, 7) 5.5 160.0 Supply Current VOLP Quiet Output or GND (Note 5) Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C. Note 6: Plastic DIP package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 8: Maximum number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. AC Electrical Characteristics 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 9) Min fmax Maximum Clock Fig. Units No. Max 5.0 95 MHz 5.0 2.5 11.5 ns 5.0 2.5 13.0 ns 5.0 1.0 9.0 ns Frequency tPLH, Propagation Delay tPHL CP to On tPZH, Output Enable Time tPZL OE to On tPHZ, Output Disable Time tPLZ OE to On Note 9: Voltage Range 5.0 is 5.0V ± 0.5V Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements 54ACTQ TA = −55˚C VCC Symbol Parameter (V) (Note 11) to +125˚C CL = 50 pF Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 3.0 ns 5.0 2.0 ns 5.0 4.0 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP tw CP Pulse Width HIGH or LOW Note 11: Voltage Range 5.0 is 5.0V ± 0.5V www.national.com 4 No. Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 55.0 pF Conditions VCC = OPEN VCC = 5.0V Capacitance 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 28 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24 Lead Slim (0.300" Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 7 www.national.com 54ACTQ821 Quiet Series 10-Bit D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24 Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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