SPICE Device Model SUM110N08-05 Vishay Siliconix N-Channel 75-V (D-S) 200°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70511 09-Jun-04 www.vishay.com 1 SPICE Device Model SUM110N08-05 Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Simulated Data Measured Data Symbol Test Conditions Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 3.1 V On-State Drain Currenta ID(on) VDS > 5 V, VGS = 10 V 1197 A VGS = 10 V, ID = 30 A 0.0038 Drain-Source On-State Resistancea rDS(on) VGS = 10 V, ID = 30 A, TJ = 125°C 0.0063 VGS = 10 V, ID = 30 A, TJ = 200°C 0.0084 Unit Static 0.0038 Ω Forward Transconductancea gfs VDS = 15 V, ID = 30 A 109 Forward Voltage a VSD IS = 110 A, VGS = 0 V 0.92 1 7663 7900 936 950 S V Dynamic b Input Capacitance Ciss VGS = 0 V, VDS = 25 V, f = 1 MHz Output Capacitance Coss Reverse Transfer Capacitance Crss 406 550 Total Gate Chargec Qg 139 145 36 30 c Qgs Gate-Drain Charge Qgd 45 45 Turn-On Delay Time c td(on) 88 25 110 200 Gate-Source Charge c c tr Turn-Off Delay Time c td(off) Rise Time Fall Time c tf Reverse Recovery Time trr VDS = 35 V, VGS = 10 V, ID = 110 A VDD = 35 V, RL = 0.40 Ω ID ≅ 110 A, VGEN = 10 V, RG = 2.5 Ω IF = 85 A, di/dt = 100 A/µs 130 65 149 165 55 80 Pf NC Ns Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 70511 09-Jun-04 SPICE Device Model SUM110N08-05 Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 70511 09-Jun-04 www.vishay.com 3 SPICE Device Model SUM110N08-05 Vishay Siliconix www.vishay.com 4 Document Number: 70511 09-Jun-04