Revised July 1999 74F190 Up/Down Decade Counter with Preset and Ripple Clock General Description Features The 74F190 is a reversible BCD (8421) decade counter featuring synchronous counting and asynchronous presetting. The preset feature allows the 74F190 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. ■ High-speed—125 MHz typical count frequency ■ Synchronous counting ■ Asynchronous parallel load ■ Cascadable Ordering Code: Order Number Package Number Package Description 74F190SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F190PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009494 www.fairchildsemi.com 74F190 Up/Down Decade Counter with Preset and Ripple Clock April 1988 74F190 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Description CE Count Enable Input (Active LOW) 1.0/3.0 20 µA/−1.8 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA PL Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA U/D Up/Down Count Control Input 1.0/1.0 20 µA/−0.6 mA Q0–Q3 Flip-Flop Outputs 50/33.3 −1 mA/20 mA RC Ripple Clock Output (Active LOW) 50/33.3 −1 mA/20 mA TC Terminal Count Output (Active HIGH) 50/33.3 −1 mA/20 mA Functional Description stage counters. For a discussion and illustrations of the various methods of implementing multistage counters, please see the 74F191 data sheet. The 74F190 is a synchronous up/down BCD decade counter containing four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. It has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOWto-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table, CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. RC Truth Table Inputs TC* L H H X X L Output X H CP RC X H Mode Select Table Inputs Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches 9 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi- www.fairchildsemi.com CE PL CE U/D H L L H L H L X X H H X *TC is generated internally H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition = LOW Pulse 2 Mode CP Count Up Count Down X Preset (Asyn.) X No Change (Hold) 74F190 State Diagram Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F190 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max −150 mA Max VOUT = 0V 55 mA Max VO = LOW VOL Output LOW 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage Voltage 2.0 Units VIH 10% VCC Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage Circuit Current IIL Input LOW Current Recognized as a HIGH Signal Recognized as a LOW Signal −1.8 IOS Output Short-Circuit Current ICCL Power Supply Current www.fairchildsemi.com −60 38 4 IIN = −18 mA IOH = −1 mA IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V, except CE VIN = 0.5V, CE 74F190 AC Electrical Characteristics Symbol Parameter TA = +25°C TA −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 100 125 Max Min Max tPLH Propagation Delay 3.0 5.5 tPHL CP to Qn 5.0 8.5 11.0 5.0 13.5 5.0 12.0 tPLH Propagation Delay 6.0 10.0 13.0 6.0 16.5 6.0 14.0 tPHL CP to TC 5.0 8.5 11.0 5.0 13.5 5.0 12.0 tPLH Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5 tPHL CP to RC 3.0 5.0 7.0 3.0 9.0 3.0 8.0 tPLH Propagation Delay 3.0 5.0 7.0 3.0 9.0 3.0 8.0 tPHL CE to RC 3.0 5.5 7.0 3.0 9.0 3.0 8.0 tPLH Propagation Delay 7.0 11.0 18.0 7.0 22.0 7.0 20.0 tPHL U /D to RC 5.5 9.0 12.0 5.5 14.0 5.5 13.0 tPLH Propagation Delay 4.0 7.0 10.0 4.0 13.5 4.0 11.0 tPHL U /D to TC 4.0 6.5 10.0 4.0 12.5 4.0 11.0 75 7.5 3.0 Min Max 90 9.5 3.0 Units MHz 8.5 tPLH Propagation Delay 3.0 4.5 7.0 3.0 9.0 3.0 8.0 tPHL Pn to Qn 6.0 10.0 13.0 6.0 16.0 6.0 14.0 tPLH Propagation Delay 5.0 8.5 11.0 5.0 13.0 5.0 12.0 tPHL PL to Qn 5.5 9.0 12.0 5.5 14.5 5.5 13.0 ns ns ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 4.5 6.0 5.0 tS(L) Pn to PL 4.5 6.0 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH(L) Pn to PL 2.0 2.0 2.0 tS(L) Setup Time, LOW 10.0 10.5 10.0 0 0 0 Units Max ns ns CE to CP tH(L) Hold Time, LOW CE to CP tS(H) Setup Time, HIGH or LOW 12.0 12.0 12.0 tS(L) U /D to CP 12.0 12.0 12.0 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) U /D to CP 0 0 0 ns tW(L) PL Pulse Width, LOW 6.0 8.5 6.0 ns tW(L) CP Pulse Width, LOW 5.0 7.0 5.0 ns tREC Recovery Time PL to CP 6.0 7.5 6.0 ns 5 www.fairchildsemi.com 74F190 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 74F190 Up/Down Decade Counter with Preset and Ripple Clock Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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