Revised February 2005
74LVX02
Low Voltage Quad 2-Input NOR Gate
General Description
Features
The LVX02 contains four 2-input NOR gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.
■ Input voltage level translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code
Order Number
Package
Package Description
Number
74LVX02M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX02SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX02MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX02MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
© 2005 Fairchild Semiconductor Corporation
Description
An , Bn
Inputs
On
Outputs
DS011600
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74LVX02 Low Voltage Quad 2-Input NOR Gate
May 1993
74LVX02
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 3)
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI
Supply Voltage (VCC)
0.5V
20 mA
0.5V to 7V
DC Input Voltage (VI)
VO
0V to 5.5V
Output Voltage (VO)
DC Output Diode Current (IOK)
VO
2.0V to 3.6V
Input Voltage (VI)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
0.5V
VCC 0.5V
20 mA
20 mA
0.5V to VCC 0.5V
DC Output Voltage (VO)
Input Rise and Fall Time ('t/'V)
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC Output Source
r25 mA
or Sink Current (IO)
DC VCC or Ground Current
r50 mA
65qC to 150qC
(ICC or IGND)
Storage Temperature (TSTG)
Power Dissipation
0 ns/V to 100 ns/V
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
180 mW
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter
TA
VCC
Min
25qC
40qC to 85qC
TA
Typ
Max
Min
HIGH Level Input
2.0
1.5
1.5
Voltage
3.0
2.0
2.0
3.6
2.4
2.4
Max
2.0
0.5
0.5
Voltage
3.0
0.8
0.8
3.6
0.8
0.8
2.0
1.9
2.0
1.9
Voltage
3.0
2.9
3.0
2.9
3.0
2.58
Conditions
V
LOW Level Input
HIGH Level Output
Units
V
VIN
VIL or VIH IOH
50 PA
IOH
50 PA
V
2.48
LOW Level Output
2.0
0.0
Voltage
3.0
0.0
0.1
IOH
0.1
0.1
0.1
3.0
0.36
0.44
VIN
50 PA
IOL
50 PA
IOL
4 mA
V
IIN
Input Leakage Current
3.6
r0.1
r1.0
PA
VIN
5.5V or GND
ICC
Quiescent Supply Current
3.6
2.0
20.0
PA
VIN
VCC or GND
Noise Characteristics
Symbol
(Note 4)
Parameter
VCC
TA
25qC
(V)
Typ
Limit
Units
Conditions
CL (pF)
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.3
0.5
V
50
VOLV
Quiet Output Minimum Dynamic VOL
3.3
0.3
0.5
V
50
VIHD
Minimum HIGH Level Dynamic Input Voltage
3.3
2.0
V
50
VILD
Maximum LOW Level Dynamic Input Voltage
3.3
0.8
V
50
Note 4: Input tr
tf
3ns
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2
4 mA
VIL or VIH IOL
74LVX02
AC Electrical Characteristics
Symbol
tPLH
VCC
Parameter
(V)
Propagation Delay Time
TA
Min
2.7
tPHL
3.3 r 0.3
25qC
40qC to 85qC
TA
Typ
Max
Min
Max
5.9
10.7
1.0
13.5
8.4
14.2
1.0
17.0
4.5
6.6
1.0
8.0
7.0
10.1
1.0
11.5
tOSLH
Output to Output Skew
2.7
1.5
1.5
tOSHL
(Note 5)
3.3
1.5
1.5
Note 5: Parameter guaranteed by design. tOSLH
|tPLHmtPLHm|, tOSHL
CL
Units
(pF)
15
50
ns
15
50
50
ns
|tPHLm–tPHLm|
Capacitance
Symbol
TA
Parameter
Min
25qC
TA
Typ
Max
10
CIN
Input Capacitance
4
CPD
Power Dissipation
15
40qC to 85qC
Min
Units
Max
10
pF
pF
Capacitance (Note 6)
Note 6: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation:
3
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74LVX02
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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4
74LVX02
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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74LVX02 Low Voltage Quad 2-Input NOR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
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1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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6