ETC 74LVX273MTCX

Revised March 1999
74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Features
■ Input voltage translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX273M
74LVX273SJ
74LVX273MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
© 1999 Fairchild Semiconductor Corporation
DS011614.prf
Description
Data Inputs
MR
Master Reset
CP
Clock Pulse Input
Q0–Q7
Data Outputs
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74LVX273 Low Voltage Octal D-Type Flip-Flop
June 1993
74LVX273
Truth Table
Operating Mode
Reset (Clear)
Inputs
Outputs
MR
CP
Dn
Qn
L
X
X
L
H
H
L
L
Load ’1’
H
Load ’0’
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions (Note 2)
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
Supply Voltage (VCC)
VI = −0.5V
−20 mA
−0.5V to 7V
DC Input Voltage (VI)
2.0V to 3.6V
Input Voltage (VI)
0V to 5.5V
Output Voltage (VO)
DC Output Diode Current (IOK)
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
VO = −0.5V
−20 mA
VO = VCC +0.5V
+20 mA
Input Rise and Fall Time (∆t/∆V)
−0.5V to VCC + 0.5V
DC Output Voltage (VO)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC Output Source
±25 mA
or Sink Current (IO)
DC VCC or Ground Current
±75 mA
(ICC or IGND)
0 ns/V to 100 ns/V
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
−65°C to +150°C
Storage Temperature (TSTG)
Power Dissipation
180 mW
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
IOZ
Parameter
VCC
TA = +25°C
Min
TA = −40°C to +85°C
Typ
Max
Min
HIGH Level
2.0
1.5
1.5
Input Voltage
3.0
2.0
2.0
3.6
2.4
2.4
2.0
0.5
0.5
Input Voltage
3.0
0.8
0.8
3.6
0.8
0.8
2.0
1.9
2.0
1.9
Output Voltage
3.0
2.9
3.0
2.9
3.0
2.58
Conditions
V
LOW Level
HIGH Level
Units
Max
V
VIN = VIH or VIL IOH = −50 µA
IOH = −50 µA
V
IOH = −4 mA
2.48
VIN = VIH or VIL IOL = 50 µA
LOW Level
2.0
0.0
0.1
0.1
Output Voltage
3.0
0.0
0.1
0.1
3.0
0.36
0.44
3.6
±0.25
±2.5
µA
VIN = VIH or VIL
3-STATE Output
IOL = 50 µA
V
IOL = 4 mA
VOUT = VCC or GND
Off-State Current
IIN
Input Leakage Current
3.6
±0.1
±1.0
µA
VIN = 5.5V or GND
ICC
Quiescent Supply Current
3.6
4.0
40.0
µA
VIN = VCC or GND
Noise Characteristics (Note 3)
Symbol
VCC
(V)
Parameter
TA = 25°C
Typ
Units
CL (pF)
Limit
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.5
0.8
V
50
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.5
−0.8
V
50
VIHD
Minimum HIGH Level Dynamic Input Voltage
3.3
2.0
V
50
VILD
Maximum LOW Level Dynamic Input Voltage
3.3
0.8
V
50
Note 3: Input tr = tf = 3ns
3
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74LVX273
Absolute Maximum Ratings(Note 1)
74LVX273
AC Electrical Characteristics
Symbol
Parameter
tPLH
Propagation
tPHL
Delay Time
CP to Qn
tPHL
Propagation Delay
VCC
(V)
TA = +25°C
Min
2.7
3.3 ± 0.3
2.7
MR to Qn
3.3 ± 0.3
tS
Setup Time
Dn to CP
tH
tREC
Max
16.9
1.0
20.5
15
20.0
1.0
24.0
50
7.1
11.0
1.0
13.0
9.6
14.5
1.0
16.5
17.8
1.0
20.5
15
21.1
1.0
24.0
50
7.3
11.5
1.0
13.5
9.8
15.0
1.0
17.0
2.7
8.0
9.5
3.3 ± 0.3
5.5
6.5
1.0
1.0
2.7
4.0
4.0
3.3 ± 0.3
2.5
2.5
Maximum
2.7
8.0
9.5
3.3 ± 0.3
5.5
6.5
ns
15
50
ns
ns
ns
ns
2.7
7.5
8.5
3.3 ± 0.3
5.0
6.0
2.7
55
110
45
15
45
60
40
50
95
150
80
60
90
50
Clock
Frequency
15
50
9.3
1.0
MR Pulse
ns
11.8
1.0
Clock Pulse
CL (pF)
9.0
2.7
Removal Time
Units
11.5
3.3 ± 0.3
Width
fMAX
Min
Dn to CP
Width
tW
Max
Hold Time
MR to CP
tW
TA = −40°C to +85°C
Typ
3.3 ± 0.3
ns
MHz
15
50
tOSLH
Output to Output
2.7
1.5
1.5
tOSHL
Skew (Note 4)
3.3
1.5
1.5
50
ns
Note 4: Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|
Capacitance
Symbol
TA = +25°C
Parameter
Min
TA = −40°C to +85°C
Typ
Max
10
Min
Max
10
Units
CIN
Input Capacitance
4
COUT
Output Capacitance
6
pF
CPD
Power Dissipation
31
pF
Capacitance (Note 5)
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
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4
pF
74LVX273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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74LVX273 Low Voltage Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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