PRELIMINARY ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL 75MHZ FREQUENCY SYNTHESIZER W/SSC GENERAL DESCRIPTION FEATURES The ICS843301I-108 is a 75MHz Frequency ICS Generator and a member of the HiPerClocks TM HiPerClockS™ family of high perfor mance devices from IDT. The ICS843301I-108 uses a 20MHz crystal to synthesize 75MHz output. The device supports 0.5% downspread spread spectrum clocking. The ICS843301I108 has excellent <1ps phase jitter performance, over an integration range of 900kHz - 7.5MHz. The device is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One differential 3.3V or 2.5V LVPECL output • Crystal oscillator interface designed for 20MHz, 18pF parallel resonant crystal • Output frequency: 75MHz • Supports SSC, 0.5% downspread • RMS phase jitter @ 75MHz, using a 20MHz crystal (900kHz - 7.5MHz): 0.73ps (typical) • Full 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages SSC FUNCTION TABLE Input Mode SSC 0 (default) SSC Off 1 0.5% Downspread BLOCK DIAGRAM PIN ASSIGNMENT 20MHz PLL XTAL_IN OSC XTAL_OUT SSC Pulldown Phase Detector VCO 600MHz Q N Div ÷8 nQ VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ SSC ICS843301I-108 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M Div ÷30 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 1 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name 1 VCCA Power 2 Power 5 VEE XTAL_OUT, XTAL_IN SSC 6, 7 nQ, Q Output Differential clock outputs. LVPECL interface levels. 8 VCC Power Core and output supply pin. 3, 4 Type Input Input Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown SSC control pin. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Pin Capacitance Test Conditions 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 2 Minimum Typical Maximum Units ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3. 3 3.465 V VCC – 0.10 3. 3 VCC V ICCA Analog Supply Current 10 mA IEE Power Supply Current 106 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V VCC – 0.09 2. 5 VCC V ICCA Analog Supply Current 9 mA IEE Power Supply Current 100 mA TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VIH Parameter Input High Voltage Test Conditions Minimum VCC = 3.3V Typical Maximum Units 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0. 8 V VCC = 2.5V -0.3 VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.465V or 2.625V IIL Input Low Current VCC = 3.465V or 2.625V, VIN = 0V 0.7 V 15 0 µA -5 µA TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 3 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 20 MHz Equivalent Series Resistance (ESR) 90 Ω Shunt Capacitance 7 pF 300 µW Drive Level TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT SSCred Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 SSC Modulation Frequency; NOTE 3 SSC Modulation Factor; NOTE 3 Spectral Reduction; NOTE 3 t R / tF Output Rise/Fall Time tjit(Ø) FM FMF Test Conditions Minimum 75MHz (Integration Range: 900kHz - 7.5MHz) FOUT = 75MHz Typical Maximum MHz 0.73 ps 29 33.33 FOUT = 75MHz Units 75 kHz 0.5 % FOUT = 75MHz 8 dB 20% to 80% 475 ps 50 % odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Spread Spectrum clocking disabled. NOTE 3: Spread Spectrum clocking enabled. TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT SSCred Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 SSC Modulation Frequency; NOTE 3 SSC Modulation Factor; NOTE 3 Spectral Reduction; NOTE 3 t R / tF Output Rise/Fall Time tjit(Ø) FM FMF Test Conditions Minimum 75MHz (Integration Range: 900kHz - 7.5MHz) FOUT = 75MHz Typical Maximum Units 75 MHz 0.72 ps 29 33.33 kHz FOUT = 75MHz 0.4 % FOUT = 75MHz 7.5 dB 20% to 80% 450 ps 50 % odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Spread Spectrum clocking disabled. NOTE 3: Spread Spectrum clocking enabled. IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 4 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY PARAMETER MEASUREMENT INFORMATION 2V 2V 2V 2V VCC Qx SCOPE VCC VCCA Qx SCOPE VCCA LVPECL LVPECL nQx nQx VEE VEE -1.3V ± 0.165V -0.5V ± 0.125V 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT VOH VREF 80% 80% VSW I N G VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Clock Outputs 20% 20% tR tF Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) OUTPUT RISE/FALL TIME PERIOD JITTER nQ Q t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 5 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843301I-108 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a 0.01μF bypass capacitor should be connected to each VCCA pin. 3.3V or 2.5V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843301I-108 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 20MHz, 18pF parallel XTAL_IN C1 X1 Crystal XTAL_OUT C2 FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 6 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE SPREAD SPECTRUM Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32kHz triangle waveform is used with 0.5% down-spread (+0.0% / TBD%) from the nominal 75MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 4A below. quency (+0.0% / TBD%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 4B. The ratio of this difference to the fundamental frequency is typically 0.5%, and will not exceed TBD%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 4B. It is important to note the ICS843301I-108 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. The ICS843301I-108 triangle modulation frequency deviation will not exceed TBD% down-spread from the nominal clock fre- ➤ Δ − 8 dBm Fnom B (1 - δ) Fnom A δ = 0.5% ➤ ➤ ➤ 0.5/fm 1/fm FIGURE 4A. TRIANGLE FREQUENCY MODULATION FIGURE 4B. 75MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN (A) S PREAD -SPECTRUM OFF (B) SPREAD -S PECTRUM ON IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 7 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY TERMINATION FOR 3.3V LVPECL OUTPUT 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 5A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 84Ω FIGURE 5B. LVPECL OUTPUT TERMINATION 8 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY TERMINATION FOR 2.5V LVPECL OUTPUT Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 9 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843301I-108. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843301I-108 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 106mA = 367.29mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 370.75mW + 30mW = 397.29mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.397W * 90.5°C/W = 120.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W 10 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50Ω VCC - 2V FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCC_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) = L L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) = L L [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 11 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS843301I-108 is: 3792 IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 12 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY PACKAGE OUTLINE - G SUFFIX 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 13 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 843301BGI-108 BI108 8 lead TSSOP tube -40°C to 85°C 843301BGI-108T BI108 8 lead TSSOP 2500 tape & reel -40°C to 85°C 843301BGI-108LF B108L 8 lead "Lead-Free" TSSOP tube -40°C to 85°C 843301BGI-108LFT BI08L 8 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC 14 ICS843301BGI-108 REV. A OCTOBER 9, 2007 ICS843301I-108 FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA