a CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator AD6121 FEATURES Fully Compliant with IS98A and PCS Specifications CDMA, W-CDMA, AMPS, and TACS Operation Linear IF Amplifier 5.9 dB Noise Figure –47.5 dB to +47 dB Linear-in-dB Gain Control Quadrature Demodulator Demodulates IFs from 50 MHz to 350 MHz Integral Low Dropout Regulator 200 mV Voltage Drop Accepts 2.9 V to 4.2 V Input from Battery Low Power 10 mA at Midgain <1 A Sleep Mode Operation Companion Transmitter IF Chip Available (AD6122) GENERAL DESCRIPTION The AD6121 is a low power receiver IF subsystem specifically designed for CDMA applications. It consists of high dynamic range IF amplifiers with voltage controlled gain, a divide-by-two quadrature generator, an I and Q demodulator, and a powerdown control input. An integral low dropout regulator allows operation from battery voltages from 2.9 V to 4.2 V. The gain control input accepts an external gain control voltage input from a DAC. It provides 94.5 dB of gain control with a nominal 52.5 dB/V scale factor when using an internal voltage reference. The gain control interface reference input can be connected to either the internal reference or an external reference. The I and Q demodulator provides differential quadrature baseband outputs to interface with CDMA baseband converters. A divide-by-two quadrature generator followed by dual polyphase filters ensures maximum ± 2.5° quadrature accuracy. APPLICATIONS CDMA, W-CDMA, AMPS, and TACS Operation QPSK Receivers The AD6121 IF Subsystem is fabricated using a 25 GHz f t BiCMOS silicon process and is packaged in a 28-lead SSOP and a 32-leadless LPCC chip scale package (5 mm × 5 mm). FUNCTIONAL BLOCK DIAGRAM ROOFING FILTER IF OUTPUT DEMODULATOR INPUT IOUT CDMA INPUT IOUT IF AMPLIFIERS I 2 LOCAL OSCILLATOR INPUT Q QOUT AD6121 FM INPUT QOUT QUADRATURE DEMODULATOR INPUT STAGE VREG PTAT TEMPERATURE COMPENSATION CDMA/FM SELECT GAIN CONTROL SCALE FACTOR GAIN CONTROL VOLTAGE INPUT LOW DROPOUT REGULATOR VPOS POWER- POWERDOWN 2 DOWN 1 GAIN 1.23V CONTROL REFERENCE VOLTAGE OUTPUT REFERENCE INPUT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 (TA = +25ⴗC, VCC = 3.0 V, LO = 2 ⴛ IF, REFIN = 1.23 V, LDO Enabled, unless otherwise IN is noted. AD6121–SPECIFICATIONS noted) Note: All power measurements in dBm are referred to 1 k⍀ unless Z Specification TOTAL GAIN Maximum Gain Minimum Gain IF AMPLIFIER CDMA and FM Input Noise Figure Input Third-Order Intercept Input 1 dB Compression Point Gain Flatness CDMA Input Capacitance CDMA Input Resistance FM Input Capacitance FM Input Resistance Output Capacitance Output Resistance GAIN CONTROL INTERFACE Gain Scaling Gain Scaling Accuracy Gain Control Response Time Input Resistance at REFIN Input Resistance at VGAIN DEMODULATOR Differential Input Impedance Differential Input Capacitance at Demodulator Input Input Third Order Intercept Demodulation Gain I/Q Output Differential Output Voltage Bandwidth Resistance Quadrature Accuracy Amplitude Balance LO Input Impedance LO Input Capacitance CONTROL INTERFACES Logic Threshold High Logic Threshold Low Input Current for Logic High Mode Control Response Time Turn-On Response Time Turn-Off Response Time LOW DROPOUT REGULATOR Conditions Min Max Units IF Amplifiers and Demodulator Powered Up IF Amplifiers Powered Up and Demodulator Powered Down IF Amplifier and Demodulator Powered Up +47 +41.4 –47.5 dB dB dB IF = 85.38 MHz Maximum Gain Maximum Gain Maximum Gain IF ± 630 kHz, CDMA Mode Differential Differential Differential Differential Differential Differential 5.9 –42.8 –51.6 ± 0.25 2.8 850 2.3 670 1.35 1.1 dB dBm dBm dB pF Ω pF Ω pF kΩ 52.5 ±3 695 10 100 dB/V dB/V ns MΩ kΩ 1 kΩ 2.9 –6.1 5.6 pF dBm dB Using Internal Reference Within a Gain Control Range of 90 dB Minimum Gain to Maximum Gain LO = 172.76 MHz , –15 dBm Referred to 50 Ω, Baseband Frequency = 1 MHz 10 kΩ, 2 pF Differential Parallel Load Impedance –3 dB Single-Ended 700 16 630 Differential Differential ± 0.1 1.5 4.16 CDMA/FM Pin High Selects CDMA, Low Selects FM PD1 and PD2 Pins Low Select IC ON, High Selects IC OFF To 200 µA Supply Current 1.34 1.30 0.1 430 2.8 6.8 V V µA ns µs µs mV p-p MHz Ω ± 2.5 Degree ± 0.35 dB kΩ pF 4.2 2.70 200 1.23 V V mV V 2.9–5.0 2.7–3.6 10 0.78 V V mA µA External PNP Pass Transistor, VCE SAT = –0.4 V Max hFE = 100/300 Min/Max Input Range Nominal Output Voltage Drop Reference Output POWER SUPPLY Supply Range Using Internal LDO Supply Range Bypassing Internal LDO Supply Current Standby Current Typ 2.9 Supply Input at Pin LDOE Supply Input at Pins DVCC, IFVCC, LDOC VGAIN = 1.5 V OPERATING TEMPERATURE TMIN to TMAX –40 +85 °C Specifications subject to change without notice. –2– REV. B AD6121 ABSOLUTE MAXIMUM RATINGS 1 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 28-lead SSOP Package: θJA = 115.25°C/W. Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . . . +5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C PIN CONFIGURATION DEMIPP IFOPN DEMIPN IFOPP CDMAIPP CDMA/FM LPCC Package CDMAIPN SSOP Package 28 IFOPP CDMAIPP 2 27 IFOPN CDMAIPN 3 26 DEMIPN IFGND 4 25 DEMIPP IFGND 1 24 LDOGND FMIPP 5 24 LDOGND IFGND 2 23 LDOGND FMIPN 6 23 IOPP FMIPP 3 22 IOPP 22 IOPN TOP VIEW (Not to Scale) 21 DGND 8 QOPP LDOB 13 16 VGAIN LDOE 14 15 PD2 LOIPN 8 17 REFOUT 9 10 11 12 13 14 15 16 REFIN 17 REFIN 19 QOPN 18 PD1 VGAIN 18 REFOUT LDOC 12 DGND 6 PD2 DVCC 11 20 QOPP LOIPP 7 LDOE 19 PD1 LDOB 20 QOPN 21 IOPN AD6121 Top View (Not to Scale) IFVCC 5 LDOC LOIPP 9 LOIPN 10 FMIPN 4 NC AD6121 32 31 30 29 28 27 26 25 DVCC IFVCC 7 NC CDMA/FM 1 NC = NO CONNECT ORDERING GUIDE Model Temperature Range Package Description Package Option AD6121ARS AD6121ARSRL AD6121ACP AD6121ACPRL –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Shrink Small Outline Package (SSOP) 28-Lead SSOP on Tape and Reel Chip Scale Package (LPCC) 32-Leadless LPCC on Tape and Reel RS-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6121 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– CP-32 WARNING! ESD SENSITIVE DEVICE AD6121 PIN FUNCTION DESCRIPTIONS SSOP Pin Number LPCC Pin Number Pin Label Description Function 1 2 3 4 5 6 7 8 9 10 CDMA/FM CDMAIPP CDMAIPN IFGND FMIPP FMIPN IFVCC DGND LOIPP LOIPN NC DVCC LDOC 13 12 LDOB 14 13 LDOE 15 14 PD2 16 15 VGAIN Selects CDMA or FM Input CDMA “Positive” Input CDMA “Negative” Input IF Ground FM “Positive” Input FM “Negative” Input IF VCC Digital Ground Local Oscillator “Positive” Input Local Oscillator “Negative” Input No Connect Digital VCC Low Dropout Regulator Pass Transistor Collector Connection Low Dropout Regulator Pass Transistor Base Connection Low Dropout Regulator Pass Transistor Emitter Connection Demodulator Power-Down Control Input Gain Control Voltage Input CMOS-compatible; HIGH = CDMA, LOW = FM. AC-coupled, IF input from CDMA SAW filter. AC-coupled, IF input from CDMA SAW filter. Ground. AC-coupled, IF input from FM SAW filter. AC-coupled, IF input from FM SAW filter. VCC for IF AGC amplifiers. Ground. AC-coupled, Differential Local Oscillator Input. AC-coupled, Differential Local Oscillator Input. 11 12 30 31 32 1, 2 3 4 5 6 7 8 9, 25 10 11 17 16 REFIN 18 17 REFOUT 19 18 PD1 20 21 22 23 24 25 26 27 28 19 20 21 22 23, 24 26 27 28 29 QOPN QOPP IOPN IOPP LDOGND DEMIPP DEMIPN IFOPN IFOPP VCC for control logic. Connects to collector of external PNP pass transistor. Connects to base of external PNP pass transistor. Connects to emitter of external PNP pass transistor and DVCC, IFVCC. Demodulator Power-Down Control Input CMOScompatible; HIGH = Modulator Off, LOW = Modulator On. Accepts gain control input voltage from external DAC. Max Gain = 2.5 V. Min Gain = 0.5 V. Gain Control Reference Input Accepts 1.23 V reference input from REFOUT (Pin 17) or external reference. Reference Output Provides 1.23 V reference output to REFIN (Pin 18) and CDMA baseband IC reference input so that gain control DAC and AD6121 use same reference. IF Amplifier Power-Down IF Amplifier Power-Down Control Input, CMOS comControl Input patible; HIGH = Entire IC Powers Down, LOW = IF Amplifier On. Q Output “Negative” Connects to Q “Negative” Input of baseband IC. Q Output “Positive” Connects to Q “Positive” Input of baseband IC. I Output “Negative” Connects to I “Negative” Input of baseband IC. I Output “Positive” Connects to I “Positive” Input of baseband IC. Ground Ground. Demodulator “Positive” IF Input Demodulator input from roofing filter. Demodulator “Negative” IF Input Demodulator input from roofing filter. IF Amplifier “Negative” IF Output IF output to roofing filter. IF Amplifier “Positive” IF Output IF output to roofing filter. –4– REV. B AD6121 Test Figures AD6121 1:8 110⍀ 10nF RF SOURCE 909⍀ 110⍀ 10nF CDMAIPP IFOPP 1k⍀ CDMAIPN 10nF 453⍀ 10nF 453⍀ 4:1 TO SPECTRUM ANALYZER 205⍀ IFOPN INDUCTOR CHOSEN FOR PEAK RESPONSE AT THE TEST FREQUENCY (SEE TEXT) a. CDMA Input Port Characterization Impedance Match AD6121 453⍀ 10nF RF SOURCE FMIPP IFOPP FMIPN IFOPN 50⍀ 10nF b. FM Input Port Characterization Impedance Match Figure 1. Quadrature Modulator Characterization Input and Output Impedance Matches 0.1F +15V 1:4 453⍀ RF SOURCE 10nF DEMIPP 205⍀ 453⍀ X1 IOPP X2 IOPN 10nF DEMIPN V–1 VP A=1 Y1 Y2 V–1 VN OUT 50⍀ I CHANNEL AD830 0.1F AD6121 –15V QUADRATURE DEMODULATOR 0.1F LO SOURCE 10nF +15V LOIPP LOIPN X1 QOPP X2 QOPN 10nF V–1 VP A=1 Y1 Y2 V–1 VN ALL SIGNAL PATHS MUST BE EQUAL LENGTHS FOR I/Q MEASUREMENTS OUT 50⍀ Q CHANNEL AD830 0.1F –15V Figure 2. IF Amplifier Characterization Input and Output Impedance Matches R&S SMT03 RF CDMA IN SYNC REFERENCE R&S SMT03 RF DEMOD IN LO INPUT HP8508A VECTOR VOLTMETER I CHANNEL CH2 Q CHANNEL DC I/O RF R&S FSEA SPECTRUM ANALYZER RF INPUT HPE3610 POWER SUPPLY HP34970A DATA ACQUISITION & SWITCH CONTROL ALL DC MEASUREMENT AND CONTROL SIGNALS Figure 3. General Test Set REV. B CH1 FM IN SYNC REFERENCE R&S SMT03 IF OUT AD6121 –5– 50⍀ TERMINATOR AD6121 AD6121 REACTIVE CONJUGATE MATCH NOISE SOURCE 1:8 10nF CDMAIPP 10nF IFOPP 1k⍀ 10nF 4:1 450⍀ 205⍀ 10nF 450⍀ CDMAIPN TO NOISE FIGURE METER IFOPN INDUCTOR CHOSEN FOR PEAK RESPONSE AT THE TEST FREQUENCY Figure 4. IF Amplifier Noise Figure Test Set HP8116A FUNCTION GEN ROHDE & SCHWARZ SMT03 4kHz, 0.5V TO 2.5V SQ WAVE 80MHz, –50dBm TEKTRONIX TDS 744A CH 1 WITH 10 VGAIN PROBE CDMA IN AD6121 CHARACTERIZATION BOARD CH 2 WITH COAX CABLE 50⍀ IF OUT a. Response Time From Gain Control to IF Output HP8116A FUNCTION GEN ROHDE & SCHWARZ SMT03 4kHz, 0V TO 2.7V SQ WAVE 80MHz, –50dBm TEKTRONIX TDS 744A CH 1 WITH 10 PD1, PD2 AD6121 PROBE CDMA IN CHARACTERIZATION BOARD CH 2 WITH COAX CABLE 50⍀ IF OUT b. Response Time From PD1 and PD2 Control to IF Output Figure 5. Response Time Setup Typical Performance Characteristics 60.00 60.00 40.00 40.00 20.00 20.00 GAIN – dB GAIN – dB TA = +25ⴗC 0.00 –20.00 0.00 –20.00 TA = +85ⴗC TA = +85ⴗC TA = –40ⴗC –40.00 –40.00 TA = +25ⴗC –60.00 0.5 TA = –40ⴗC 1 1.5 VGAIN – Volts 2 –60.00 0.5 2.5 Figure 6. IF Amplifier’s Gain vs. VGAIN, IF = 70 MHz, TA = –40 °C, +25 °C and +85 °C 1 1.5 VGAIN – Volts 2 2.5 Figure 7. IF Amplifier’s Gain vs. VGAIN, IF = 85 MHz, TA = –40 °C, +25 °C and +85 °C –6– REV. B AD6121 –30.00 40.00 –32.00 –34.00 20.00 –36.00 0.00 IIP3 – dBm GAIN – dB TA = +85ⴗC –20.00 –38.00 –40.00 –42.00 –44.00 TA = +25ⴗC –46.00 –40.00 –48.00 TA = –40ⴗC –60.00 0.5 1.5 VGAIN – Volts 1 2 –50.00 0 2.5 Figure 8. IF Amplifier’s Gain vs. VGAIN, IF = 210 MHz, TA = –40 °C, +25 °C and +85 °C 50 100 150 200 FREQUENCY – MHz 250 300 Figure 11. IF Amplifier’s Input IP3 vs. Frequency, VGAIN = +2.5 V, TA = +25 °C 25 4.00 3.50 NOISE FIGURE – dB GAIN STEP ERROR – dB 20 3.00 2.50 2.00 TA = +85ⴗC 1.50 15 2.7VPOS 10 1.00 5 TA = +25ⴗC 3.6VPOS 0.50 3.0VPOS TA = –40ⴗC 0.00 0 2 1 1.5 VGAIN – Volts 0.5 0 –10 2.5 Figure 9. IF Amplifier’s Gain Error vs. VGAIN, TA = –40 °C, +25 °C and +85 °C 25 –10 20 NOISE FIGURE – dB 0 –20 IF = 85MHz –30 50 15 2.7VPOS 10 3.6VPOS –40 –20 0 GAIN – dB 20 40 0 –10 60 0 10 3.0VPOS 20 GAIN – dB 30 40 Figure 13. IF Amplifier Noise Figure vs. GAIN, IF= 210 MHz, TA = +25 °C Figure 10. IF Amplifier’s Input IP3 vs. Gain, IF = 85 MHz, 210 MHz, TA = +25 °C REV. B 40 5 –40 –50 –60 30 Figure 12. IF Amplifier Noise Figure vs. GAIN, IF= 85 MHz, TA = +25 °C IF = 210MHz IIP3 – dBm 20 GAIN – dB 10 0 –7– 50 AD6121 –10 50.00 TA = –40ⴗC –20 TA = +85ⴗC INPUT P1dB – dBm MAXIMUM GAIN – dB 40.00 TA = +25ⴗC 30.00 20.00 –30 –40 –50 10.00 –60 0.5 0.00 0 50 100 150 200 FREQUENCY – MHz 250 300 1 1.5 VGAIN – V 2 2.5 Figure 17. IF Amplifier Input 1 dB Compression Point vs. VGAIN, IF = 85.38 MHz Figure 14. IF Amplifier Maximum Gain vs. Frequency, TA = –40 °C, +25 °C and +85 °C 6 60.00 TA = –40ⴗC 40.00 5 20.00 4 GAIN – dB GAIN – dB VGAIN = +2.5V 0.00 VGAIN = +1.5V TA = +25ⴗC TA = +85ⴗC 3 2 –20.00 1 –40.00 VGAIN = +0.5V 0 –60.00 0 100 200 FREQUENCY – MHz 300 0 10 5 BASEBAND FREQUENCY – MHz 15 Figure 18. Demodulator I Channel Gain vs. Baseband Frequency, IF = 85 MHz Figure 15. IF Amplifier Gain vs. Frequency, VGAIN = +0.5 V, +1.5 V and = +2.5 V 20 –40.00 –42.00 –44.00 10 TA = –40ⴗC TA = +25ⴗC TA = +85ⴗC –48.00 GAIN – dB P1dB – dBm –46.00 –50.00 –52.00 –54.00 0 –10 –56.00 –58.00 –60.00 0 50 200 100 150 FREQUENCY – MHz 250 –20 0 300 300 100 200 INTERMEDIATE FREQUENCY – MHz 400 Figure 19. Demodulator I Channel Gain vs. IF, Baseband Frequency = 1 MHz, TA = –40 °C, +25 °C and +85 °C Figure 16. IF Amplifier 1 dB Compression Point vs. Frequency, VGAIN = +2.5 V –8– REV. B AD6121 2.5 0.25 PHASE ERROR – Degrees AMPLITUDE BALANCE I–Q – dB 0.3 0.2 IF = 210MHz IF = 85MHz 0.15 0.1 2.0 TA = –40ⴗC 1.5 TA = +25ⴗC TA = +85ⴗC 1.0 0.05 0 0 10 5 BASEBAND FREQUENCY – MHz 0.5 0 15 Figure 20. Demodulator I and Q Amplitude Balance vs. Baseband Frequency, IF = 85 MHz and 210 MHz 10 5 BASEBAND FREQUENCY – MHz 15 Figure 23. Demodulator Phase Error vs. Baseband Frequency, IF = 85 MHz, TA = –40 °C, +25 °C and +85 °C 5 6 IF = 85MHz TA = +85ⴗC 4 0 IIP3 – dBm GAIN – dB TA = +25ⴗC 2 –5 TA = –40ⴗC –10 0 IF = 210MHz –2 0 10 5 BASEBAND FREQUENCY – MHz –15 15 Figure 21. Demodulator I Channel Gain vs. Baseband Frequency, IF = 85 MHz and 210 MHz 3 REGULATOR OUTPUT VOLTAGE – Volts PHASE ERROR I–Q – Degrees TA = +25ⴗC 2.0 TA = –40ⴗC 1.5 TA = +85ⴗC 1.0 0.5 TA = +85ⴗC 2 TA = +25ⴗC 1 TA = –40ⴗC 0 –1 0 100 200 300 INTERMEDIATE FREQUENCY – MHz 400 2 2.5 3 3.5 4 4.5 REGULATOR INPUT VOLTAGE – Volts 5 Figure 25. LDO Regulator Output Voltage vs. Input Voltage, TA = –40 °C, +25 °C and +85 °C Figure 22. Demodulator Phase Error vs. IF, Baseband Frequency = 1 MHz, TA = –40 °C, +25 °C and +85 °C REV. B 400 Figure 24. Demodulator Input IP3 vs. IF, Baseband Frequency = 1 MHz, TA = –40 °C, +25 °C and +85 °C 2.5 0 100 200 300 INTERMEDIATE FREQUENCY – MHz 0 –9– AD6121 amplifiers. The gain and input bandwidth of the AD6121 are identical for both the FM and CDMA operating modes. When the CDMA/FM pin is high, CDMA mode is enabled. When the pin is low, FM mode is enabled. 16 CURRENT CONSUMPTION – mA 14 TA = +85ⴗC TA = +25ⴗC 12 The IF amplifiers operate in two different configurations, one with the I and Q demodulator powered up and another with the I and Q demodulator powered down. The I and Q demodulator power setting is configured with pin PD2. The power-down control is further discussed in the section of this data sheet entitled Power-Down Control. 10 8 TA = –40ⴗC 6 4 When the demodulator is powered up, the outputs of the IF amplifiers are internally dc-biased and there is no need for external pull-up inductors. A roofing filter is required (see section entitled Roofing Filter in this data sheet) when using the IF amplifiers with the I and Q demodulator powered up. Under these conditions, the IF amplifiers and the low noise attenuator input stage has +41.4 dB of gain. 2 0 0.5 1 1.5 VGAIN – Volts 2 2.5 Figure 26. Current Consumption vs. VGAIN, TA = –40 °C, +25 °C and +85 °C THEORY OF OPERATION The AD6121 consists of high dynamic range IF amplifiers with voltage controlled gain, a divide-by-two quadrature generator, an I and Q demodulator, a low dropout regulator and powerdown control inputs (Figure 27). The AD6121 accommodates both the desired CDMA signal and an interferer 42 dB larger—approximately 6 mV p-p for the desired signal and 700 mV p-p for the interferer—as specified in the CDMA system. IF Amplifiers and Gain Control The IF gain is provided by two sections: a CDMA or FM input stage followed by three cascaded IF amplifiers. The CDMA and FM input stages use differential, continuously-variable attenuators based on Analog Devices’ patented X-AMP™ topology. These low noise attenuators consist of a differential R-2R ladder network, linear interpolator, and a fixed gain amplifier. The bulk of the IF gain is provided by three cascaded, wideband When the I and Q demodulator is powered down, the IF amplifiers have open collector outputs resulting in the need for pullup inductors. Under this configuration, and with the output of the IF amplifiers loaded with 1 kΩ, the gain of the IF amplifiers and low noise attenuator input stage is +47 dB. The pull-up inductors should be chosen so that the parasitic capacitance seen at the output of the IF amplifiers is resonated at the frequency of interest. Figure 28 shows how to configure the pull-up inductors at the output of the IF amplifiers. The 10 nF capacitors are used for ac coupling. In order to resonate the parasitic capacitors, rearrange Equation 1 to solve for L. f0 = 1 (1) 2 π LCPAR where f0 is the IF frequency in Hertz, CPAR is the total parasitic capacitance in Farads, and L is the total shunt inductor value in henrys. ROOFING FILTER IF OUTPUT DEMODULATOR INPUT IOUT CDMA INPUT IOUT IF AMPLIFIERS I 2 LOCAL OSCILLATOR INPUT Q QOUT AD6121 FM INPUT QOUT QUADRATURE DEMODULATOR INPUT STAGE VREG PTAT TEMPERATURE COMPENSATION CDMA/FM SELECT GAIN CONTROL SCALE FACTOR GAIN CONTROL VOLTAGE INPUT LOW DROPOUT REGULATOR VPOS POWER- POWERDOWN 2 DOWN 1 GAIN 1.23V CONTROL REFERENCE VOLTAGE OUTPUT REFERENCE INPUT Figure 27. Functional Block Diagram X-AMP is a trademark of Analog Devices, Inc. –10– REV. B AD6121 AD6121 2CPAR L/2 2CPAR L/2 the slope of the gain curve will change as a result of a change in the required range for VGAIN. Figure 30 shows the piecewise linear approximation of the gain curve for the AD6121. 10nF IFOPP VCC 10nF 10nF MAXIMUM GAIN GAIN – V/V IFOPN Figure 28. IF Amplifiers’ Output Configuration When I and Q Demodulator Is Powered Down MINIMUM GAIN In order to confirm whether the pull-up inductors have been properly designed, sweep the IF frequency and view the output of the IF amplifiers on a spectrum analyzer. If the inductor value is correct, the signal should peak at the IF frequency. VGAIN – Volts Figure 30. Piecewise Linear Approximation for the AD6121 Gain Curve The gain of the two amplifier sections (input stage followed by amplifiers) changes sequentially for optimum signal-to-noise ratio. For example, in CDMA mode, the gain of the CDMA input amplifier first increases to maximum and then the gain of the cascaded IF amplifiers increases to maximum. Likewise, when decreasing gain, the gain of the cascaded amplifiers decreases to minimum before the gain of the CDMA input amplifier. Because the minimum and maximum gains for the AD6121 are constant, we can approximate the VGAIN range for a given REFIN voltage by using Equation 2. VGAIN = The gain control circuits contain both temperature compensation circuitry and a choice of internal or external reference for adjusting the gain scale factor. The gain control input accepts an external gain control voltage from a DAC. It provides 94.5 dB of gain control range with a nominal 52.5 dB/V scale factor. Either an internal or external reference may be used to set the gain control scale factor. The external gain control input signal should be free of noise. In a typical wireless application, it is recommended to filter this signal in order to reduce the noise that results from the DAC that generates it. A simple RC filter can be employed, but care should be taken with its design. If too big a resistor is used, a large voltage drop may occur across the resistor resulting in lower gain than expected (as a result of a lower voltage reaching the AD6121). An RC filter with a 1 kHz bandwidth, employing a 1 kΩ resistor is appropriate. This results in a 150 nF capacitor. The resulting circuit is shown in Figure 29. (GAIN – MinGain) × 1.6 REFIN + 0.4 REFIN MaxGain – MinGain (2) Where MaxGain is the maximum gain (+47 dB) in dB, MinGain is the minimum gain (–47.5 dB) in dB, REFIN is the reference input voltage, in volts, VGAIN is the gain control voltage input, in volts, and GAIN is the particular gain, in dB, we would have for a given REFIN and VGAIN. Consequently, for any REFIN we choose, we can calculate the VGAIN range by solving Equation 2 for VGAIN. For example, in order to determine the VGAIN value for the maximum gain condition, given a 1.23 V REFIN, we can solve Equation 2 for VGAIN by substituting 47 dB for GAIN and MaxGain, –47.5 dB for MinGain and 1.23 V for REFIN. VGAIN can then be calculated to be 2.46 V, or approximately 2.5 V. For the minimum gain condition, we can determine the VGAIN value by substituting 47 dB for MaxGain, –47.5 dB for Gain and MinGain and 1.23 V for REFIN. VGAIN can then be calculated to be 0.492 V or approximately 0.5 V. I and Q Demodulator AD6121 FROM BASEBAND CONVERTER 1k⍀ VGAIN 150nF 100k⍀ Figure 29. Gain Voltage Filtering The AD6121’s overall gain, expressed in decibels, is linear in dB with respect to the automatic gain control (AGC) voltage, VGAIN. Either REFOUT, or an external reference voltage connected to REFIN, may be used to set the voltage range for VGAIN. When the internal 1.23 V reference, REFOUT, is connected to REFIN, VGAIN will control the AGC range when it is typically set between 0.5 V and 2.5 V. Minimum gain occurs at minimum voltage on VGAIN and maximum gain occurs at maximum voltage on VGAIN. The maximum and minimum gain will not change with a change in voltage at REFIN. Rather, REV. B The I and Q demodulator provides differential quadrature baseband outputs to CDMA baseband converters. The demodulator provides 5.6 dB of voltage gain in addition to the gain provided by the IF amplifier stage. The outputs of the I and Q demodulator are filtered with a low-pass filter, which typically has a 16 MHz bandwidth. A divide-by-two quadrature generator followed by dual polyphase filters ensures a typical ± 1° quadrature accuracy (Figure 31). –11– I 2 IF LO INPUT I 2 QUADRATURE OUTPUT TO DEMODULATOR POLYPHASE FILTERS 180 2 Q Q Figure 31. Simplified Quadrature Generator Circuit AD6121 Power-Down Control ROOFING FILTER The AD6121 can operate with the IF amplifier and I and Q demodulator stages both powered up, the IF amplifiers powered up alone or both the IF amplifiers and demodulator powered down. The AD6121 cannot operate with the demodulator powered up and the IF amplifiers powered down. The control for these different modes is performed via the PD1 and PD2 pins. Table I shows the decoding of the logic inputs. When the IF amplifiers and I and Q demodulator of the AD6121 are both powered up, the parasitic impedances seen at the output of the IF amplifiers and inputs of the I and Q demodulator are high enough to create a low-pass filter, which may attenuate the IF signal. Consequently, the parasitic capacitance must be cancelled by using an external inductor to form a parallel resonant circuit. The external inductor that is required and the internal parasitic capacitors form what is known as the roofing filter, with the resonant frequency given by Equation 1 (see IF Amplifiers and Gain Control section of this data sheet). Table I. AD6121 Operating Modes PD1 PD2 IF Amplifiers Demodulator 0 0 1 1 0 1 0 1 ON ON INVALID STATE OFF ON OFF INVALID STATE OFF Low Dropout Regulator The AD6121 incorporates an integrated low dropout regulator. The regulator accepts inputs from 2.9 V to 4.2 V and supplies 2.7 V at LDOC. The 2.7 V signal can be used to provide the dc voltages required for the DVCC and IFVCC dc supplies. In order to configure the low dropout regulator, an external pass transistor is required. A pnp transistor with a minimum hFE of 100 and a maximum hFE of 300 and a VCE(Sat.) of –0.4 V is required. In order to use the low dropout regulator, configure the transistor as shown in Figure 32. The 10 nF capacitor in Figure 32 is used for decoupling the 2.7 V dc signal. In addition to the low dropout regulator, there is a bandgap voltage reference which produces a 1.23 V reference voltage at pin REFOUT. This reference voltage will be present whenever a voltage is applied to IFVCC and DVCC. This 1.23 V reference voltage can then be used to provide the gain reference voltage for the receive ADCs in the baseband converter. LDOC 2.7V 10nF PASS TRANSISTOR LDOE 2.7V TO 4.2V Figure 32. AD6121 LDOB 1.23V REFOUT Configuring the Low Dropout Regulator It is possible to bypass the low dropout regulator on the AD6121 and use an external regulator instead. In order to bypass the integrated low dropout regulator, connect pins LDOE, LDOB and LDOC together and then connect them all to the external regulator voltage. This configuration is shown in Figure 33. Even when the low dropout regulator is bypassed, the 1.23 V reference voltage at pin REFOUT is still present. AD6121 LDOB LDOE AD6121 IFOPP 2CPAR L 2CPAR IFOPN 10nF DEMIPP 10nF DEMIPN Figure 34. Roofing Filter Configuration In order to confirm whether the roofing filter has been correctly designed, sweep the IF frequency and view the output of the I and Q demodulator on a spectrum analyzer. The output level of the I or Q signal should be approximately flat from dc to 16 MHz, after which the low-pass filters at the I and Q output will attenuate the signal. With the correct roofing filter inductor, the I and Q output signal will be higher than for any other roofing filter inductor value. It should be noted that the roofing filter is only required when cascading the output from the IF amplifiers to the input of the I and Q demodulator. If we are looking at the output of the IF amplifiers, no roofing filter is required. Because the IF amplifiers’ outputs are open collector when the I and Q demodulator is powered down, pull-up inductors will be required in order to set the dc voltage (see the section of this data sheet entitled IF Amplifiers and Gain Control) and to resonate the parasitic capacitors that are present under these conditions. LEVEL DIAGRAM LDOC FROM EXTERNAL VOLTAGE REGULATOR The roofing filter may be composed of a shunt inductor between the IF amplifiers differential output pins. Because the demodulator is powered up when the output of the IF amplifiers are fed into the I and Q demodulator, the output of the IF amplifiers are not open collector. As a result, pull up inductors are not required. This configuration is shown in Figure 34. The 10 nF capacitors are used for ac coupling. REFOUT 1.23V Figure 33. Configuration for Bypassing the Low Dropout Regulator Figure 35 is provided in order to better understand the different voltage and power levels you can expect to see at different points on the AD6121. It represents the levels that would be seen on Rev. B of the AD6121 Customer Evaluation Board. When trying to make these measurements, a high impedance (10 MΩ) active FET probe (for example, the TEK P6204 from Tektronix) should be used to minimize the effects of loading the circuits with the probe. –12– REV. B AD6121 IOUT –19.6dBm DIFFERENTIAL REFERRED TO 700⍀ 247.8mV p-p DIFFERENTIAL f = 85.38MHz –61dBm DIFFERENTIAL REFERRED TO 500⍀ 1.78mV p-p DIFFERENTIAL f = 85.38MHz –60dBm REFERRED TO 50⍀ 632.5mV p-p DIFFERENTIAL SIGNAL GENERATOR IOUT –14dBm DIFFERENTIAL REFERRED TO 700⍀ 472mV p-p DIFFERENTIAL I LOCAL OSCILLATOR INPUT 168.76MHz 100mV p-p DIFFERENTIAL 2 Q VGAIN = 2.5V GAIN = +41.4dB QOUT QOUT AD830 50⍀ ZIN = 700⍀ AT 85.38MHz SPECTRUM ANALYZER 50⍀ AD830 1:8 50⍀ 50⍀ 50⍀ 1k⍀ –5.55dBm REFERRED TO 100⍀ 472mV p-p ZIN = 500⍀ –8.55dBm REFERRED TO 50⍀ 236mV p-p Figure 35. AD6121 Signal Level Diagram for AD6121 Customer Sample Board, Rev. B CDMA/FM AD6121 CDMAIPN CDMAIPP IFOPP IFOPN IFGND CDMA BASEBAND IC DEMIPN FMIPN DEMIPP FMIPP LDOGND IOPP IOPN IFVCC DGND I INPUT POS I INPUT NEG I LOIPP 2 LOIPN Q QOPP QOPN DVCC LDOC LDOB VCC LDOE Q INPUT POS Q INPUT NEG PD1 REFOUT LOW DROPOUT REGULATOR GAIN CONTROL SCALE FACTOR VGAIN PD2 TEMP COMP EXT REF IN REFIN 1k⍀ RX AGC DAC 159nF Figure 36. Typical Application Showing Interface to Baseband IC with SSOP Package add matching networks. The board is configured for an IF frequency of 85.38 MHz when shipped. OUTPUT INTERFACES The AD6121 interfaces to CDMA baseband converters requiring either IF or baseband inputs. The baseband output is provided by direct connection of the AD6121’s baseband output to the baseband input of the baseband converter (Figure 36). The output interfaces are controlled by the AD6121’s power-down modes. The AD830s are used to provide differential to single ended conversion for analysis of the differential I and Q outputs. As a result, the output can be displayed on a spectrum analyzer or other test equipment requiring a single ended input. AD6121 CUSTOMER EVALUATION BOARD The AD6121 customer evaluation board consists of an AD6121, I/O connectors, 3 two-pin headers, a 20-pin dual header and two AD830 High Speed Video Difference Amplifiers. It allows the user to evaluate the AD6121’s I and Q demodulator and IF amplifiers operating together or separately. The board is identical for both the SSOP and LPCC packages. Because the AD6121 can operate at any IF frequency from 50 MHz to 350 MHz, pads are provided on the LOIPP, IFIP, CDMAIP and DMOD IN inputs as well as the IF OUT output ports to allow the user to REV. B Prior to applying a CDMA or FM input signal, the appropriate mode must be selected. FM mode will be selected by shorting the two pins of the two pin header labeled FM/CDMA. Open circuiting these two pins will select CDMA mode. In order to test the power-down modes of the AD6121, locate the bank of 3 two-pin headers on the evaluation board. In order to have both the IF amplifiers and the I and Q demodulator powered up, short circuit each of the two pins on the two pin headers labeled PD1 and PD2. In order to power down the demodulator and keep the IF amplifiers powered up, short circuit the 2 pins on the header labeled PD1 and open circuit –13– AD6121 the header labeled PD2. As described in Table I of this data sheet, it is invalid to have PD1 open circuited and PD2 short circuited. In order to power down the IF amplifiers and demodulator, open circuit both PD1 and PD2. Table III lists the connections for the 20-pin power supply connector. As shipped, the board is configured as follows: Pin Number Table III. 20-Pin Power Supply Connection Information 1. J1 is open circuited and J2 is short circuited. This enables the LDO regulator. In order to bypass the LDO regulator, short circuit J1 and open circuit J2. 2. X18, X26, X25 and X23 are short circuited resulting in the IF amplifiers’ output being connected to the I and Q demodulator’s input. 2 3. L4, the roofing filter inductor is optimized for an IF frequency of 85.38 MHz. 4. L2 and L3 are open circuited, although the components are soldered on one pad of each set of solder pads. In order to evaluate the IF amplifiers and I and Q demodulator independent of each other, the roofing filter will have to be removed from the circuit and the pull up inductors will have to be added at the output of the IF amplifiers. When evaluating the IF amplifiers alone, the I and Q demodulator should be powered down as described earlier in this section. The 470 nH pull up inductors required for the 85.38 MHz IF frequency are provided with the board, however, they will need to be soldered down to pads L2 and L3. The roofing filter should be disconnected from the circuit and the output ports for the IF amplifiers as well as the input ports for the I and Q demodulator should be connected. This is accomplished by open circuiting X18, X25, X26 and X33 and short circuiting X19, X21, X27 and X29. Table II describes the high frequency signal connectors on the AD6121 customer sample board. Table II. Evaluation Board SMA Signal Connector Descriptions Connector Description LOIPP FMIP Local oscillator positive input at 2 × IF frequency FM signal input port. The differential to single ended conversion performed on board by a balun. Impedance matched to 50 Ω for a 85.38 MHz IF frequency. CDMA signal input port. The differential to single ended conversion performed on board by a balun. Impedance matched to 50 Ω for a 85.38 MHz IF frequency. IF Amplifier output port. The differential to single ended conversion performed on board by a balun. Impedance matched to 50 Ω for a 85.38 MHz IF frequency. Demodulator input port. The differential to single ended conversion performed on board by a balun. Impedance matched to 50 Ω for a 85.38 MHz IF frequency. I channel output port for the I and Q demodulator. Q channel output port for the I and Q demodulator CDMAIP IF OUT DMOD IN I CH Q CH 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function VPOS for AD6121. 2.9 V–4.2 V using the LDO Regulator. 2.7 V–4.2 V bypassing the LDO Regulator. VPOS for AD6121. 2.9 V–4.2 V using the LDO Regulator. 2.7 V–4.2 V bypassing the LDO Regulator. Ground. Ground. Ground. Ground. Ground. PD1. Connects to 2-pin header labeled PD1. Ground. PD2. Connects to 2-pin header labeled PD2. Ground. FM/CDMA. Selects FM or CDMA mode. Connected to 2-pin header labeled FM/CDMA. Ground. REFOUT. 1.23 V output reference voltage from Pin 18 on AD6121. Ground. VGAIN. Gain control voltage input. Connected to Pin 16 on AD6121. Ground. VREGOUT. The 2.7 V output of the LDO regulator when it is enabled. Connects to Pin 12 on AD6121. –15 V for AD830 Amplifier. +15 V for AD830 Amplifier. A schematic diagram of the evaluation board is shown in Figure 37. –14– REV. B AD6121 VREGOUT C23 L2 10nF 470nH C12 10nF VREGOUT FM/CDMA X2 0⍀ C1 10nF X5 0⍀ 1:8 2 CDMAIP X3 120nH X1 T1 X9 0⍀ X7 0⍀ Z = 500⍀ X8 X13 1k⍀ X11 T2 5 C4 10nF X7 0⍀ IFVCC 6 7 8 C6 0.01F X16 0⍀ 9 LO IN X15 C7 10nF X17 10 DVCC C9 10nF VREGOUT AD6121 CDMA/FM IFOPP CDMAIPP IFOPN CDMAIPN DEMIPN IFGND DEMIPP C24 L3 10nF 470nH 28 X18 0⍀ 11 12 13 J2 0⍀ FMMT4403CT-ND 14 VREG IN L4 620nH FMIPP LDOGND FMIPN IOPP U1 IOIPN IFVCC QOPP DGND LOIPP QOPN LOIPN PD1 DVCC REFOUT LDOC REFIN –15V P1 1 3 5 7 9 11 13 15 17 19 P2 2 4 6 8 10 12 14 16 18 20 L1 470nH R4 10k⍀ R5 10k⍀ X24 X26 0⍀ C14 10nF 26 C13 10nF X25 0⍀ C15 10nF 25 X29 X33 0⍀ 8:1 X31 68nH DMOD IN X30 180nH X28 X32 T4 24 C16 0.1F +15V 23 X1 X2 V–1 22 U2 VP A=1 Y1 21 Y2 V–1 VN SOIC PACKAGE OUT AD830 I CH R7 50⍀ 20 –15V C17 0.1F 19 PD1 C18 0.1F 18 +15V 17 X1 LDOB LDOE VGAIN PD2 X2 V–1 16 15 PD2 C21 10nF R9 0⍀ R6 10k⍀ A=1 Y2 V–1 C20 10nF U3 VP Y1 J5 0⍀ VN SOIC PACKAGE OUT AD830 R8 50⍀ Q CH –15V C19 0.1F REFOUT VGAIN VREG IN 2.9V – 4.2V IFVCC PD1 PD2 FM/CDMA REFOUT VGAIN 0.5V – 2.5V VREGOUT PD1 PD2 FM/CDMA DVCC +15V INDICATES A 50⍀ TRACE Figure 37. Schematic Diagram of AD6121 Evaluation Board REV. B IF OUT C23 27 VPOS VPOS 2.9V – 4.2V X22 4pF X20 X21 X23 150nH T3 J1 Q1 8:1 X27 FMIP X10 150nH 3 4 C3 10nF X5 0⍀ 1:8 R1 1k⍀ C2 10nF X6 X4 1 X19 –15– C5 18pF R3 10⍀ C11 10nF C8 18pF R2 10⍀ C10 10nF VREGOUT VREGOUT AD6121 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 28 C00945b–.5–6/00 (rev. B) 0.407 (10.34) 0.397 (10.08) 15 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 1 14 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) PIN 1 0.068 (1.73) 0.0256 0.008 (0.203) (0.65) 0.002 (0.050) BSC 0.015 (0.38) SEATING 0.010 (0.25) PLANE 0.009 (0.229) 0.005 (0.127) 8 0 0.03 (0.762) 0.022 (0.558) 32-Leadless Chip Scale Package (LPCC) (CP-32) 0.205 (5.20) 0.197 (5.00) SQ 0.189 (4.80) 0.128 (3.25) 0.106 (2.70) SQ 0.049 (1.25) 32 1 25 24 0.015 (0.38) 0.012 (0.30) 0.009 (0.23) BOTTOM VIEW 17 PIN 1 INDICATOR 8 9 16 0.138 (3.50) BSC 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) 0.039 (1.00) 0.035 (0.90) 0.031 (0.80) 0.010 (0.25) REF 0.020 (0.50) BSC 0.002 (0.05) 0.001 (0.02) 0.000 (0.00) PRINTED IN U.S.A. CONTROLLING DIMENSIONS ARE IN MILLIMETERS DIMENSIONS MEET JEDEC MO-220-VHHD-2 –16– REV. B