FEATURES CONNECTION DIAGRAMS Low cost single (AD8057) and dual (AD8058) High speed 325 MHz, −3 dB bandwidth (G = +1) 1000 V/μs slew rate Gain flatness: 0.1 dB to 28 MHz Low noise 7 nV/√Hz Low power 5.4 mA/amplifier typical supply current @ 5 V Low distortion −85 dBc @ 5 MHz, RL = 1 kΩ Wide supply range from 3 V to 12 V Small packaging AD8057 is available in an 8-lead SOIC and 5-lead SOT-23 AD8058 is available in an 8-lead SOIC and an 8-lead MSOP AD8057 VOUT 1 5 +VS 4 –IN +IN 3 (Not to Scale) 01064-001 –VS 2 Figure 1. RT-5 (SOT-23) AD8057 NC 1 8 NC –IN 2 7 +VS +IN 3 6 VOUT –VS 4 5 NC (Not to Scale) 01064-002 NC = NO CONNECT Figure 2. R-8 (SOIC) APPLICATIONS Imaging DVD/CD Photodiode preamp Analog-to-digital driver Professional cameras filters OUT1 1 –IN1 AD8058 8 +VS 2 7 OUT2 +IN1 3 6 –IN2 –VS 4 5 +IN2 (Not to Scale) 01064-003 Data Sheet Low Cost, High Performance Voltage Feedback, 325 MHz Amplifier AD8057/AD8058 Figure 3. RM-8 (MSOP) and R-8 (SOIC) GENERAL DESCRIPTION Rev. D 4 3 2 1 G = +1 0 –1 G = +5 –2 G = +2 –3 G = +10 –4 –5 1 10 100 FREQUENCY (MHz) 1000 01064-004 The AD8057 and AD8058 are available in standard SOIC packaging as well as tiny 5-lead SOT-23 (AD8057) and 8-lead MSOP (AD8058) packages. These amplifiers are available in the industrial temperature range of −40°C to +85°C. 5 GAIN (dB) The AD8057 (single) and AD8058 (dual) are very high performance amplifiers with a very low cost. The balance between cost and performance make them ideal for many applications. The AD8057 and AD8058 reduce the need to qualify a variety of specialty amplifiers. The AD8057 and AD8058 are voltage feedback amplifiers with the bandwidth and slew rate normally found in current feedback amplifiers. The AD8057 and AD8058 are low power amplifiers having low quiescent current and a wide supply range from 3 V to 12 V. They have noise and distortion performance required for high end video systems as well as dc performance parameters rarely found in high speed amplifiers. Figure 4. Small Signal Frequency Response Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved. 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AD8057/AD8058 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications ....................................................................................... 1 Test Circuits ..................................................................................... 12 Connection Diagrams ...................................................................... 1 Applications Information .............................................................. 13 General Description ......................................................................... 1 Driving Capacitive Loads .......................................................... 13 Revision History ............................................................................... 2 Video Filter .................................................................................. 13 Specifications..................................................................................... 3 Differential Analog-to-Digital Driver ..................................... 14 Absolute Maximum Ratings............................................................ 5 Layout .......................................................................................... 14 Maximum Power Dissipation ..................................................... 5 Outline Dimensions ....................................................................... 15 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 15 REVISION HISTORY 9/13—Rev. C to Rev. D Changes to Output Voltage Swing Parameter, Table 3 ................. 4 Updated Outline Dimensions ........................................................15 Changes to Ordering Guide ...........................................................16 10/10—Rev. B to Rev. C Updated Format .................................................................. Universal Change to Third-Order Intercept Parameter, Table 1 ................. 3 Changes to Input Common-Mode Voltage Range Parameter, Table 2 ................................................................................................ 4 Changes to Figure 32 ...................................................................... 10 Changes to Figure 35 ...................................................................... 11 Changes to Figure 41 and Figure 42 ............................................. 12 Changes to Figure 44 and Figure 45............................................. 13 Changes to Ordering Guide .......................................................... 16 8/03—Rev. A to Rev. B Renumbered Figures and TPCs ........................................ Universal Changes to Ordering Guide .............................................................4 Change to Figure 8 ......................................................................... 12 Update Outline Dimensions ......................................................... 14 Rev. D | Page 2 of 16 Data Sheet AD8057/AD8058 SPECIFICATIONS @ TA = 25°C, VS = ±5 V, RL = 100 Ω, RF = 0 Ω, gain = +1, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion SFDR Third-Order Intercept Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Overload Recovery DC PERFORMANCE Input Offset Voltage Conditions Min MHz MHz MHz MHz V/µs V/µs ns fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, VO = 2 V p-p, RL = 150 Ω f = 5 MHz, VO = 2 V p-p f = 5 MHz, G = +2 f = 100 kHz f = 100 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 1 kΩ NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 1 kΩ VIN = 200 mV p-p, G = +1 –85 –62 –68 −35 −60 7 0.7 0.01 0.02 0.15 0.01 30 dBc dBc dB dBm dB nV/√Hz pA/√Hz % % Degrees Degrees ns 1 2.5 3 0.5 3.0 VO = ±2.5 V, RL = 2 kΩ 50 55 mV mV μV/°C µA µA µA dB VO = ±2.5 V, RL = 150 Ω 50 52 dB 10 2 MΩ pF V dB TMIN to TMAX Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current for AD8057 Quiescent Current for AD8058 Power Supply Rejection Ratio Unit 325 95 175 30 850 1150 30 Input Offset Voltage Drift Input Bias Current INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Max G = +1, VO = 0.2 V p-p G = –1, VO = 0.2 V p-p G = +1, VO = 2 V p-p G = +1, VO = 0.2 V p-p G = +1, VO = 2 V step, RL = 2 kΩ G = +1, VO = 4 V step, RL = 2 kΩ G = +2, VO = 2 V step TMIN to TMAX Input Offset Current Open-Loop Gain Typ 5 2.5 ±0.75 +Input RL = 1 kΩ VCM = ±2.5 V RL = 2 kΩ RL = 150 Ω 30% overshoot −4.0 48 −4.0 Rev. D | Page 3 of 16 +4.0 V V pF ±6 7.5 15 V mA mA dB ±3.9 30 ±1.5 VS = ±5 V to ±1.5 V +4.0 60 54 ±5.0 6.0 14.0 59 AD8057/AD8058 Data Sheet @ TA = 25°C, VS = 5 V, RL = 100 Ω, RF = 0 Ω, gain = +1, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Conditions Min MHz MHz MHz V/µs ns fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, G = +2 f = 100 kHz f = 100 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 1 kΩ NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 1 kΩ –75 –54 −60 7 0.7 0.05 0.05 0.10 0.02 dBc dBc dB nV/√Hz pA/√Hz % % Degrees Degrees 1 2.5 3 0.5 3.0 VO = ±1.5 V, RL = 2 kΩ to midsupply 50 55 mV mV μV/°C µA µA µA dB VO = ±1.5 V, RL = 150 Ω to midsupply 45 52 dB 48 10 2 0.9 to 3.4 60 MΩ pF V dB 0.9 to 3.8 1.2 to 3.4 30 V V pF Input Offset Voltage Drift Input Bias Current TMIN to TMAX Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current for AD8057 Quiescent Current for AD8058 Power Supply Rejection Ratio Unit 300 155 28 700 35 TMIN to TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Max G = +1, VO = 0.2 V p-p G = +1, VO = 2 V p-p VO = 0.2 V p-p G = +1, VO = 2 V step, RL = 2 kΩ G = +2, VO = 2 V step DC PERFORMANCE Input Offset Voltage Input Offset Current Open-Loop Gain Typ 5 2.5 0.75 +Input RL = 1 kΩ VCM = ±2.5 V RL = 2 kΩ RL = 150 Ω 30% overshoot 3 54 Rev. D | Page 4 of 16 5.0 5.4 13.5 58 10 7.0 14 V mA mA dB Data Sheet AD8057/AD8058 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 3. Lead Temperature (Soldering 10sec) 1 0.8 W 0.5 W 0.6 W ±VS ±4.0 V Observe power derating curves −65°C to +125°C −40°C to +85°C 2.0 TJ = 150°C 300°C Specification is for device in free air: 8-lead SOIC package: θJA = 160°C/W 5-lead SOT-23-5 package: θJA = 240°C/W 8-Lead MSOP package: θJA = 200°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1.5 8-LEAD SOIC 1.0 8-LEAD MSOP 0.5 SOT-23-5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE (°C) 70 80 90 Figure 5. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. D | Page 5 of 16 01064-005 Storage Temperature Range (R) Operating Temperature Range (A Grade) The maximum power that can be safely dissipated by the AD8057/AD8058 is limited by the associated rise in junction temperature. Exceeding a junction temperature of 175°C for an extended period can result in device failure. Although the AD8057/AD8058 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. Rating 12.6 V MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage (+VS to –VS) Internal Power Dissipation1 SOIC Package (R) SOT-23-5 Package (RT) MSOP Package (RM) Input Voltage (Common Mode) Differential Input Voltage Output Short-Circuit Duration AD8057/AD8058 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 4.5 (+) OUTPUT VOLTAGE 4.0 –1.0 –2.5V SWING RL = 150Ω –1.5 ABS (–) OUTPUT VOLTS (V) 2.5 2.0 –2.0 –2.5 –3.0 1.5 –3.5 1.0 –4.0 0.5 –5V SWING RL = 150Ω –4.5 10 100 10k 1k LOAD RESISTANCE (Ω) 100k –5.0 –40 –30 –20 –10 01064-006 0 Figure 6. Output Swing vs. Load Resistance 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 85 01064-009 OUTPUT VOLTAGE (V) 3.5 3.0 –1.5V SWING RL = 150Ω –0.5 Figure 9. Negative Output Voltage Swing vs. Temperature –3.0 6 –3.5 4 –4.0 2 –5.0 –ISUPPLY @ ±1.5V VOS (mV) –ISUPPLY (mA) –4.5 –5.5 –6.0 –ISUPPLY @ ±5V VOS @ ±1.5V 0 VOS @ ±5V –2 –6.5 –7.0 –4 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 85 –6 –40 –30 –20 –10 01064-007 –8.0 –40 –30 –20 –10 Figure 7. −ISUPPLY vs. Temperature 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 85 Figure 10. VOS vs. Temperature 5.0 4.5 0 01064-010 –7.5 3.5 +5V SWING RL = 150Ω 3.0 AVOL @ ±5V 4.0 2.5 AVOL (mV/V) 3.0 2.5 2.0 1.5 1.0 2.0 AVOL @ ±2.5V 1.5 +2.5V SWING RL = 150Ω 1.0 +1.5V SWING RL = 150Ω 0.5 0 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 85 0 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 Figure 11. Open-Loop Gain vs. Temperature Figure 8. Positive Output Voltage Swing vs. Temperature Rev. D | Page 6 of 16 70 80 85 01064-011 0.5 01064-008 VOLTS (V) 3.5 Data Sheet AD8057/AD8058 0 100mV –0.1 –0.2 20mV/DIV IB (µA) –0.3 –0.4 +IB @ ±5V –0.7 –IB @ ±2.5V –IB @ ±5V +IB @ ±1.5V –IB @ ±1.5V –0.8 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 85 01064-016 –0.6 +IB @ ±2.5V –100mV 01064-012 –0.5 4ns/DIV Figure 15. Small Signal Step Response G = +1, RL = 1 kΩ, VS = ±5 V, See Figure 41 for Test Circuit Figure 12. Input Bias Current vs. Temperature 4 5V 3 PSRR (mV/V) PSRR @ ±1.5V ±5V 1V/DIV 2 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 85 –5V 01064-013 0 –40 –30 –20 –10 4ns/DIV 01064-017 1 Figure 16. Large Signal Step Response G = +1,RL = 1 kΩ, VS = ±5.0 V, See Figure 41 for Test Circuit Figure 13. PSRR vs. Temperature 100mV 0 –10 20mV/DIV –PSRR VS = ±2.5V 0V –30 +PSRR VS = ±2.5V –40 –60 0.1 1 10 FREQUENCY (MHz) 100 1000 –100mV 4ns/DIV Figure 14. PSRR vs. Frequency Figure 17. Small Signal Step Response G = –1, RL = 1 kΩ, See Figure 42 for Test Circuit Rev. D | Page 7 of 16 01064-019 –50 01064-014 PSRR (dB) –20 AD8057/AD8058 Data Sheet 5 5V 4 3 2 GAIN (dB) 1V/DIV 1 G = –2 G = –1 0 –1 –2 G = –5 –3 01064-020 –5V 4ns/DIV –5 1 Figure 21. Large Signal Frequency Response 5 0.5 4 0.4 3 0.3 2 0.2 1 0.1 GAIN (dB) GAIN (dB) Figure 18. Large Signal Step Response G = –1, RL = 1 kΩ , See Figure 42 for Test Circuit G = +1 0 1000 10 100 FREQUENCY (MHz) 01064-023 G = –10 –4 –1 VOUT = 0.2V G = +2 RL = 1.0kΩ RF = 1.0kΩ 0 –0.1 G = +5 –2 –0.2 G = +2 –3 –0.3 G = +10 –4 100 10 FREQUENCY (MHz) 1000 –0.5 1 Figure 19. Small Signal Frequency Response, VOUT = 0.2 V p-p 10 100 FREQUENCY (MHz) 1000 01064-024 1 01064-021 –5 –0.4 Figure 22. 0.1 dB Flatness G = +2 5 –50 4 –60 3 DISTORTION (dBc) 1 G = +1 0 G = +5 –1 –2 –3 SECOND –80 THIRD –90 –100 1 100 10 FREQUENCY (MHz) 1000 –110 Figure 20. Large Signal Frequency Response, VOUT = 2 V p-p 1 10 100 FREQUENCY (MHz) Figure 23. Distortion vs. Frequency, RL = 150 Ω Rev. D | Page 8 of 16 1000 01064-025 G = +10 –4 –5 THD –70 G = +2 01064-022 GAIN (dB) 2 Data Sheet AD8057/AD8058 –40 VOUT = –1V TO + 1V OR +1V TO –1V G = +2 RL = 100Ω/1kΩ 0.4% 0.3% DISTORTION (dBc) –50 0.2% 20MHz 0.1% 0% –60 –0.1% –0.2% 5MHz –70 –0.3% 0 0.4 0.8 1.2 2.0 2.4 1.6 VOUT (V p-p) 3.2 2.8 3.6 4.0 0 01064-026 –80 Figure 24. Distortion vs. VOUT @ 20 MHz, 5 MHz, RL = 150 Ω, VS = ±5.0 V 10 20 30 40 50 TIME (ns) 4.5 2.5V 3.5 VS = ±2.5V RL = 1kΩ G = +1 INPUT SIGNAL OUTPUT RESPONSE 500mV/ DIV 3.0 2.5 2.0 0V FALL TIME 1.5 RISE TIME 1.0 0 1 2 VOUT (V p-p) 3 4 20ns/DIV 01064-027 0 Figure 28. Input Overload Recovery, VS = ±2.5 V Figure 25. Rise Time and Fall Time vs. VOUT, G = +1, RL = 1 kΩ, RF = 0 Ω 5 VS = ±5.0V RL = 1kΩ G = +1 4 INPUT SIGNAL 5V 5.0V 1V/DIV 3 OUTPUT SIGNAL = 4.0V RISE TIME 2 FALL TIME 0V 1 0 0 1 2 VOUT (V p-p) 3 4 01064-028 RISE TIME AND FALL TIME (ns) 01064-030 0.5 20ns/DIV Figure 26. Rise Time and Fall Time vs. VOUT, G = +2, RL = 100 Ω, RF = 402 Ω Rev. D | Page 9 of 16 Figure 29. Output Overload Recovery, VS = ±5.0 V 01064-031 RISE TIME AND FALL TIME (ns) 60 Figure 27. Settling Time 5.0 4.0 01064-029 –0.4% AD8057/AD8058 Data Sheet 0 0 –10 –20 CROSSTALK (dB) CMRR (dB) –20 –30 –40 –40 –60 SIDE B DRIVEN –80 –50 SIDE A DRIVEN 1 10 FREQUENCY (MHz) 100 –120 0.1 01064-032 –70 0.1 Figure 30. CMRR vs. Frequency 10 FREQUENCY (MHz) 100 Figure 33. Crosstalk (Output-to-Output) vs. Frequency 1.8V OUTPUT SIGNAL 1.7V 1 01064-035 –100 –60 0.015 VS = ±2.5V R1 = 1kΩ G = +4 DIFFERENTIAL GAIN (%) 0.010 VS = ±5.0V RL = 150Ω 0.005 0 –0.005 200mV/ DIV –0.010 –0.015 INPUT SIGNAL = 0.6V DIFFERENTIAL PHASE (Degrees) 20ns/DIV VS = ± 5.0V RL = 150Ω 1st Figure 31. Output Overload Recovery, VS = ±2.5 V 0.015 2nd 3rd 4th 5th 6th 7th VS = ±5.0V RL = 1kΩ 0.005 VS = ±5V R1 = 1kΩ G = +4 9th 10th 11th DIFFERENTIAL GAIN (%) 0.010 4.5V 8th 01064-036 01064-033 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 –0.02 0 –0.005 –0.010 –0.015 500mV/ DIV DIFFERENTIAL PHASE (Degrees) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 –0.02 Figure 32. Output Overload Recovery, VS = ±5.0 V 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 01064-037 1st 01064-034 20ns/DIV VS = ±5.0V RL = 1kΩ Figure 34. Differential Gain and Differential Phase One Back Terminated Load (150 Ω) (Video Op Amps Only) Rev. D | Page 10 of 16 Data Sheet AD8057/AD8058 100 135 60 90 40 45 GAIN 20 0 0 VNOISE (nV/√Hz) PHASE (Degrees) 80 10 1 0.1 1 10 FREQUENCY (MHz) 100 –90 1000 0.1 10 01064-038 –20 0.01 Figure 35. Open-Loop Gain and Phase vs. Frequency 0.01 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 10M 100M 01064-041 –45 Figure 38. Voltage Noise vs. Frequency DIFFERENTIAL GAIN (%) 100 VS = +5V RL = 150Ω 0 –0.01 –0.02 INOISE (pA/√Hz) –0.03 –0.04 –0.05 DIFFERENTIAL PHASE (Degrees) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 –0.02 10 1 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 01064-039 1st 0.1 10 Figure 36. Differential Gain and Differential Phase, RL = 150 Ω 0.01 100 1k 10k 100k FREQUENCY (Hz) 1M 01064-042 VS = +5V RL = 150Ω Figure 39. Current Noise vs. Frequency DIFFERENTIAL GAIN (%) 100 VS = +5V RL = 1kΩ 0 –0.01 –0.02 –0.03 10 ZOUT (Ω) –0.04 –0.05 DIFFERENTIAL PHASE (Degrees) 1 VS = +5V RL = 1kΩ 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.1 0.1 Figure 37. Differential Gain and Differential Phase, RL = 1 kΩ 1 10 FREQUENCY (MHz) 100 Figure 40. Output Impedance vs. Frequency Rev. D | Page 11 of 16 1000 01064-043 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 –0.02 01064-040 OPEN-LOOP GAIN (dB) 180 AD8057/AD8058 Data Sheet TEST CIRCUITS 1kΩ +VS 4.7µF +VS 4.7µF 0.01µF AD8057 AD8058 HP8130A PULSE GENERATOR TR/TF = 1ns VOUT 0.001µF 1kΩ 0.001µF VIN 1kΩ 50Ω AD8057 AD8058 0.01µF 1kΩ 0.01µF 4.7µF –VS VOUT 0.001µF 4.7µF –VS Figure 42. Test Circuit, G = −1, RL = 1 kΩ Figure 41. Test Circuit, G = +1, RL = 1 kΩ Rev. D | Page 12 of 16 01064-018 VIN 50Ω 0.01µF 0.001µF 01064-015 HP8130A PULSE GENERATOR TR/TF = 1ns Data Sheet AD8057/AD8058 APPLICATIONS INFORMATION DRIVING CAPACITIVE LOADS When driving a capacitive load, most op amps exhibit overshoot in their pulse response. Figure 43 shows the relationship between the capacitive load that results in 30% overshoot and the closedloop gain of an AD8058. It can be seen that, under the gain = +2 condition, the device is stable with capacitive loads of up to 69 pF. In general, to minimize peaking or to ensure device stability for larger values of capacitive loads, a small series resistor (RS) can be added between the op amp output and the load capacitor (CL) as shown in Figure 44. Table 4. Recommended Value for Resistors RS, RF, RG vs. Capacitive Load, CL, Which Results in 30% Overshoot Gain 1 2 3 4 5 10 RF 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω RG CL (RS = 0 Ω) 11 pF 51 pF 104 pF 186 pF 245 pF 870 pF 100 Ω 50 Ω 33.2 Ω 25 Ω 11 Ω CL (RS = 2.4 Ω) 13 pF 69 pF 153 pF 270 pF 500 pF 1580 pF +OVERSHOOT 29.0% For the setup shown in Figure 44, the relationship between RS and CL was empirically derived and is shown in Table 4. 200mV 500 100mV 400 300 –200mV 200 RS = 2.4Ω 50ns/DIV Figure 45. Typical Pulse Response with CL = 65 pF, Gain = +2, and VS = ±2.5 100 RS = 0Ω 2 3 CLOSED-LOOP GAIN 4 5 01064-044 VIDEO FILTER 0 1 01064-046 100mV/DIV Figure 43. Capacitive Load Drive vs. Closed-Loop Gain RF +2.5V 0.1µF 10µF RG RS AD8058 VIN = 200mV p-p Figure 46 shows a circuit that uses an AD8057 to create a single 5 V supply, 3-pole Sallen-Key filter. This circuit uses a single RC pole in front of a standard 2-pole active section. To shift the dc operating point to midsupply, ac coupling is provided by R4, R5, and C4. FET PROBE VOUT CL 10µF –2.5V C2 680pF 01064-045 0.1µF Some composite video signals that are derived from a digital source contain some clock feedthrough that can cause problems with downstream circuitry. This clock feedthrough is usually at 27 MHz, which is a standard clock frequency for both NTSC and PAL video systems. A filter that passes the video band and rejects frequencies at 27 MHz can be used to remove these frequencies from the video signal. RF 1kΩ Figure 44. Capacitive Load Drive Circuit +5V +5V 2 R1 200Ω R2 499Ω C1 100pF R3 49.9Ω C4 0.1µF C3 36pF R4 10kΩ R5 10kΩ 3 0.1µF 7 AD8057 4 Figure 46. Low-Pass Filter for Video Rev. D | Page 13 of 16 + 10µF 6 01064-047 CL (pF) –100mV AD8057/AD8058 Data Sheet 1kΩ Figure 47 shows a frequency sweep of this filter. The response is down 3 dB at 5.7 MHz; therefore, it passes the video band with little attenuation. The rejection at 27 MHz is 42 dB, which provides more than a factor of 100 in suppression of the clock components at this frequency. +5V 0.1µF 1kΩ VIN 0V 10 0.1µF 1kΩ 3 2 +2.5V + 10µF +5V + 10µF 8 50Ω 1 AD8058 REF VINA 1kΩ 0 1kΩ 1kΩ 6 1kΩ 5 –20 –30 AD8058 AD9225 VINB 4 –40 0.1µF –50 50Ω 7 –5V 10µF + 1kΩ 01064-049 LOG MAGNITUDE (dB) –10 –60 Figure 48. Schematic Circuit for Driving AD9225 –70 In this circuit, one of the op amps is configured in the inverting mode whereas the other is in the noninverting mode. However, to provide better bandwidth matching, each op amp is configured for a noise gain of +2. The inverting op amp is configured for a gain of −1 and the noninverting op amp is configured for a gain of +2. Each of these produces a noise gain of +2, which is determined only by the inverse of the feedback ratio. The input signal to the noninverting op amp is divided by two to normalize its level and make it equal to the inverting output. For 0 V input, the outputs of the op amps want to be at 2.5 V, which is the midsupply level of the ADCs. This is accomplished by first taking the 2.5 V reference output of the ADC and dividing it by two by a pair of 1 kΩ resistors. The resulting 1.25 V is applied to the positive input of each op amp. This voltage is then multiplied by the gain of +2 of the op amps to provide a 2.5 V level at each output. The assumption for this circuit is that the input signal is bipolar with respect to ground and the circuit must be dc-coupled thereby implying the existence of a negative supply elsewhere in the system. This circuit uses −5 V as the negative supply for the AD8058. Tying the negative supply of the AD8058 to ground causes a problem at the input of the noninverting op amp. The input common-mode voltage can only go to within 1 V of the negative rail. Because this circuit requires that the positive inputs operate with a 1.25 V bias, there is not enough room to swing this voltage in the negative direction. The inverting stage does not have this problem because its common-mode input voltage remains fixed at 1.25 V. If dc coupling is not required, various ac coupling techniques can be used to eliminate this problem. –90 100k 1M 10M FREQUENCY (MHz) 100M 01064-048 –80 Figure 47. Video Filter Response DIFFERENTIAL ANALOG-TO-DIGITAL DRIVER As system supply voltages are dropping, many ADCs provide differential analog inputs to increase the dynamic range of the input signal while still operating on a low supply voltage. Differential driving can also reduce second and other evenorder distortion products. Analog Devices, Inc., offers an assortment of 12- and 14-bit high speed converters that have differential inputs and can be run from a single 5 V supply. These include the AD9220, AD9221, AD9223, AD9224, and AD9225 at 12 bits, and the AD9240, AD9241, and AD9243 at 14 bits. Although these devices can operate over a range of common-mode voltages at their analog inputs, they work best when the common-mode voltage at the input is at the midsupply or 2.5 V. Op amp architectures that require upwards of 2 V of headroom at the output have significant problems when trying to drive such ADCs while operating with a 5 V positive supply. The low headroom output design of the AD8057 and AD8058 make them ideal for driving these types of ADCs. The AD8058 can be used to make a dc-coupled, single-endedto-differential driver for one of these ADCs. Figure 48 is a schematic of such a circuit for driving an AD9225, 12-bit, 25 MSPS ADC. LAYOUT The AD8057 and AD8058 are high speed op amps for use in a board layout that follows standard high speed design rules. Make all signal traces as short and direct as possible. In particular, keep the parasitic capacitance on the inverting input of each device to a minimum to avoid excessive peaking and other undesirable performance. Bypass the power supplies very close to the power pins of the package with a 0.1 µF capacitor in parallel with a larger (approximately 10 µF) tantalum capacitor. Connect these capacitors to a ground plane that either is on an inner layer or fills the area of the board that is not used for other signals. Rev. D | Page 14 of 16 Data Sheet AD8057/AD8058 OUTLINE DIMENSIONS 3.20 3.00 2.80 5.15 4.90 4.65 5 8 3.20 3.00 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 6° 0° 0.40 0.25 0.80 0.55 0.40 0.23 0.09 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 49. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 50. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. D | Page 15 of 16 012407-A 8 4.00 (0.1574) 3.80 (0.1497) AD8057/AD8058 Data Sheet 3.00 2.90 2.80 1.70 1.60 1.50 5 1 4 2 3.00 2.80 2.60 3 0.95 BSC 1.90 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.50 MAX 0.35 MIN 0.20 MAX 0.08 MIN SEATING PLANE 10° 5° 0° 0.60 BSC 0.55 0.45 0.35 COMPLIANT TO JEDEC STANDARDS MO-178-AA 11-01-2010-A 1.30 1.15 0.90 Figure 51. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8057AR AD8057AR-REEL AD8057AR-REEL7 AD8057ARZ AD8057ARZ-REEL AD8057ARZ-REEL7 AD8057ACHIPS AD8057ART-R2 AD8057ART-REEL7 AD8057ARTZ-R2 AD8057ARTZ-REEL AD8057ARTZ-REEL7 AD8057AR-EBZ AD8057ART-EBZ AD8058AR AD8058AR-REEL7 AD8058ARZ AD8058ARZ-REEL AD8058ARZ-REEL7 AD8058ACHIPS AD8058ARM AD8058ARM-REEL7 AD8058ARMZ-REEL7 AD8058ARMZ AD8058ARMZ-REEL AD8058AR-EBZ AD8058ARM-EBZ 1 2 Notes 2 2 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N, 13” Tape and Reel 8-Lead SOIC_N, 7” Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13” Tape and Reel 8-Lead SOIC_N, 7” Tape and Reel Die 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 8-Lead SOIC_N Evaluation Board 5-Lead SOT-23 Evaluation Board 8-Lead SOIC_N 8-Lead SOIC_N, 7” Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13” Tape and Reel 8-Lead SOIC_N, 7” Tape and Reel Die 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N Evaluation Board 8-Lead MSOP Evaluation Board Z = RoHS Compliant Part. Bottom mark has # sign before date code ©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01064-0-9/13(D) Rev. D | Page 16 of 16 Package Option R-8 R-8 R-8 R-8 R-8 R-8 Waffle Pak RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 R-8 R-8 R-8 R-8 R-8 Waffle Pak RM-8 RM-8 RM-8 RM-8 RM-8 Branding H7A H7A H08 H08 H08 H8A H8A H8A H8A H8A