BB ADC574ATH

®
ADC574A
FPO
Microprocessor-Compatible
ANALOG-TO-DIGITAL CONVERTER
FEATURES
for freedom from latch-up and for optimum AC performance. It is complete with a self-contained +10V
reference, internal clock, digital interface for microprocessor control, and three-state outputs.
● COMPLETE 12-BIT A/D CONVERTER WITH
REFERENCE, CLOCK, AND 8-, 12-, or 16BIT MICROPROCESSOR BUS INTERFACE
The reference circuit, containing a buried zener, is lasertrimmed for minimum temperature coefficient. The
clock oscillator is current-controlled for excellent stability over temperature. Full-scale and offset errors may
be externally trimmed to zero. Internal scaling resistors
are provided for the selection of analog input signal
ranges of 0V to +10V, 0V to +20V, ±5V, and ±10V.
● IMPROVED PERFORMANCE SECOND
SOURCE FOR 574A-TYPE A/D
CONVERTERS
Conversion Time: 25µs max
Bus Access Time: 150ns max
AO Input: Bus Contention During Read
Operation Eliminated
● DUAL IN-LINE PLASTIC, PLCC AND
HERMETIC CERAMIC
● FULLY SPECIFIED FOR OPERATION ON
±12V OR ±15V SUPPLIES
● NO MISSING CODES OVER
TEMPERATURE:
0°C to +75°C: ADC574AJ and K Grades
–55°C to +125°C: ADC574ASH, TH
The converter may be externally programmed to provide 8- or 12-bit resolution. The conversion time for 12
bits is factory set for 25µs maximum.
Output data are available in a parallel format from TTLcompatible three-state output buffers. Output data are
coded in straight binary for unipolar input signals and
bipolar offset binary for bipolar input signals.
The ADC574A, available in both industrial and military
temperature ranges, requires supply voltages of +5V
and ±12V or ±15V. It is packaged in a 28-pin plastic
DIP, and a hermetic side-brazed ceramic DIP.
DESCRIPTION
The ADC574A is a 12-bit successive approximation
analog-to-digital converter, utilizing state-of-the-art
CMOS and laser-trimmed bipolar die custom-designed
Control
Inputs
Control Logic
Status
Bipolar
Offset
10V Range
Reference
Input
Comparator
12-Bit D/A
Converter
Reference
Output
Three-State Buffers
Successive
Approximation
Register
Clock
20V Range
Parallel
Data
Output
10V
Reference
International Airport Industrial Park • Mailing Address: PO Box 11400
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP •
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1984 Burr-Brown Corporation
PDS-550G
Printed in U.S.A., August, 1993
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, VCC = +12V or +15V, VEE = –12V or –15V, and VLOGIC = +5V unless otherwise specified.
ADC574AJP, JH, SH
PARAMETER
MIN
TYP
ADC574AKP, KH, TH
MAX
RESOLUTION
MIN
TYP
12
MAX
UNITS
*
Bits
*
*
V
V
kΩ
kΩ
INPUTS
ANALOG
Voltage Ranges: Unipolar
Bipolar
Impedance: 0 to +10V, ±5V
±10V, 0V to +20V
DIGITAL (CE, CS, R/C, AO, 12/8)
Over Temperature Range
Voltages: Logic 1
Logic 0
Current
Capacitance
4.7
9.4
+2
–0.5
–5
0 to +10, 0 to +20
±5, ±10
5
10
0.1
5
5.3
10.6
*
*
+5.5
+0.8
+5
*
*
*
*
*
*
*
*
*
*
V
V
µA
pF
±1/2
*
±4
LSB
LSB
LSB
*
% of FS(2)
Bits
LSB
±1
±1
±1/2
±3/4
LSB
LSB
±0.47
±0.75
±0.22
±0.5
±0.37
±0.5
±0.12
±0.25
% of FS
% of FS
% of FS
% of FS
Bits
*
*
TRANSFER CHARACTERISTICS
ACCURACY
At +25°C
Linearity Error
Unipolar Offset Error (Adjustable to Zero)
Bipolar Offset Error (Adjustable to Zero)
Full-Scale Calibration Error(1)
(Adjustable to Zero)
No Missing Codes Resolution (Diff. Linearity)
Inherent Quantization Error
TMIN to TMAX
Linearity Error: J, K Grades
S, T Grades
Full-Scale Calibration Error
Without Initial Adjustment(1): J, K Grades
S, T Grades
Adjusted to Zero at +25°C: J, K Grades
S, T Grades
No Missing Codes Resolution (Diff. Linearity)
±1
±2
±10
±0.25
11
12
±1/2
*
11
12
TEMPERATURE COEFFICIENTS (TMIN to TMAX)(3)
Unipolar Offset: J, K Grades
S, T Grades
Max Change: All Grades
Bipolar Offset: All Grades
Max Change: J, K Grades
S, T Grades
Full-Scale Calibration: J, K Grades
S, T Grades
Max Change: J, K Grades
S, T Grades
±10
±5
±2
±10
±2
±4
±45
±50
±9
±20
±5
±2.5
±1
±5
±1
±2
±25
±25
±5
±10
ppm/°C
ppm/°C
LSB
ppm/°C
LSB
LSB
ppm/°C
ppm/°C
LSB
LSB
POWER SUPPLY SENSITIVITY
Change in Full-Scale Calibration
+13.5V < VCC < +16.5V or +11.4V < VCC < + 12.6V
–16.5V < VEE < –13.5V or –12.6V < VEE < – 11.4V
+4.5V < VLOGIC < +5.5V
±2
±2
±1/2
±1
±1
*
LSB
LSB
LSB
*
•
µs
µs
*
V
V
µA
pF
CONVERSION TIME (4)
8-Bit Cycle
12-Bit Cycle
10
15
13
20
17
25
*
*
*
•
OUTPUTS
DIGITAL (DB11–DB0, STATUS)
(Over Temperature Range)
Output Codes: Unipolar
Bipolar
Logic Levels: Logic 0 (ISINK = 1.6mA)
Logic 1 (ISOURCE = 500µA)
Leakage, Data Bits Only, High -Z State
Capacitance
+2.4
–5
Unipolar Straight Binary (USB)
Bipolar Offset Binary (BOB)
+0.4
*
+5
*
0.1
5
®
ADC574A
2
*
*
*
SPECIFICATIONS
(CONT)
ELECTRICAL
At TA = +25°C, VCC = +12V or +15V, VEE = –12V or –15V, and VLOGIC = +5V unless otherwise specified.
ADC574AJP, JH, SH
ADC574AKP, KH, TH
PARAMETERS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE VOLTAGE
Voltage
Source Current Available for External Loads(5)
+9.9
2.0
+10.0
+10.1
*
*
*
*
V
mA
*
*
*
3.5
15
9
325
+16.5
–16.5
+5.5
5
20
15
450
*
*
*
*
*
*
*
*
*
*
*
V
V
V
mA
mA
mA
mW
+75
+125
+150
*
*
*
*
*
*
°C
°C
°C
POWER SUPPLY REQUIREMENTS
+11.4
–11.4
+4.5
Voltage: VCC
VEE
VLOGIC
Current: ICC
IEE
ILOGIC
Power Dissipation (±15V Supplies)
TEMPERATURE RANGE (Ambient: TMIN , TMAX )
Specifications: J, K Grades
S, T Grades
Storage
0
–55
–65
* Same specifications as ADC574AJP, AJH, ASH.
NOTES: (1) With fixed 50Ω resistor from REF OUT to REF IN. This parameter is also adjustable to zero at ±25°C (see Optional External Full Scale and Offset
Adjustments section). (2) FS in this specification table means Full Scale Range. That is, for a ±10V input range, FS means 20V; for a 0 to +10V range, FS means
10V. The term Full Scale for these specifications instead of Full-Scale Range is used to be consistent with other vendors' 574 and 574A type specifications tables.
(3) Using internal reference. (4) See Controlling the ADC574A section for detailed information concerning digital timing. (5) External loading must be constant during
conversion. The reference output requires no buffer amplifier with either ±12V or ±15V power supplies.
PIN CONFIGURATION
3
AO
4
R/C
5
CE
6
+V CC
7
Ref Out
8
Analog Common
9
Ref In
10
Control
Logic
Clock
10V
Reference
12-Bit
D/A
Converter
12 Bits
Comparator
V EE
11
Bipolar Offset
12
10kΩ
12 Bits
Nibble A
CS
Nibble B
2
Nibble C
12/8
Power-up Reset
Three-State Buffers and Control
1
Successive Approximation Register
+5VDC Supply (VLOGIC )
28
Status
27
DB11 (MSB)
26
DB10
25
DB9
24
DB8
23
DB7
22
DB6
21
DB5
20
DB4
19
DB3
18
DB2
17
DB1
16
DB0 (LSB)
15
Digital Common
5kΩ
10V Range
13
20V Range
14
5kΩ
®
3
ADC574A
ABSOLUTE MAXIMUM RATINGS
BURN-IN SCREENING
Burn-in screening is available for both plastic and ceramic
package ADC574s. Burn-in duration is 160 hours at the
temperature (or equivalent combination of time and temperature) indicated below:
VCC to Digital Common ......................................................... 0V to +16.5V
VEE to Digital Common .......................................................... 0V to –16.5V
VLOGIC Digital Common .............................................................. 0V to +7V
Analog Common to Digital Common .................................................... ±1V
Control Inputs (CE, CS, AO, 12/8, R/C)
to Digital Common .............................................. –0.5V to VLOGIC +0.5V
Analog Inputs (Ref In, Bipolar Offset, 10VIN )
to Analog Common ...................................................................... ±16.5V
20VIN to Analog Common .................................................................. ±24V
Ref Out .......................................................... Indefinite Short to Common,
Momentary Short to VCC
Max Junction Temperature ............................................................ +165°C
Power Dissipation ........................................................................ 1000mW
Lead Temperature (soldering,10s) ................................................. +300°C
Thermal Resistance, θJA : Ceramic ................................................ 50°C/W
Plastic ................................................. 100°C/W
Plastic “–BI” models: +85°C
Ceramic “–BI” models: +125°C
All units are 100% electrically tested after burn-in is completed. To order burn-in, add “–BI” to the base model
number (e.g., ADC574AKP-BI).
CAUTION: These devices are sensitive to electrostatic discharge.
Appropriate I.C. handling procedures should be followed.
ORDERING INFORMATION
MODEL
ADC574AJP
ADC574AKP
ADC574AJH
ADC574AKH
ADC574ASH
ADC574ATH
PACKAGE
TEMPERATURE
RANGE
LINEARITY
ERROR MAX
(TMINTO TMAX)
Plastic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
0°C to +75°C
0°C to +75°C
0°C to +75°C
0°C to +75°C
–55°C to +125°C
–55°C to +125°C
±1LSB
±1/2LSB
±1LSB
±1/2LSB
±1LSB
±3/4LSB
PACKAGE
TEMPERATURE
RANGE
BURN-IN TEMP
(160 Hours)
Plastic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
0°C to +75°C
0°C to +75°C
0°C to +75°C
0°C to +75°C
–55°C to +125°C
–55°C to +125°C
+85°C
+85°C
+125°C
+125°C
+125°C
+125°C
BURN-IN SCREENING OPTION
See text for details.
MODEL
ADC574AJP-BI
ADC574AKP-BI
ADC574AJH-BI
ADC574AKH-BI
ADC574ASH-BI
ADC574ATH-BI
PACKAGE INFORMATION
MODEL
ADC574AJP
ADC574AKP
ADC574AJH
ADC574AKH
ADC574ASH
ADC574ATH
PACKAGE
PACKAGE DRAWING
NUMBER(1)
Plastic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
215
215
149
149
149
149
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
ADC574A
4
DISCUSSION OF
SPECIFICATIONS
out the range. Thus, every input code width (quantum) must
have a finite width. If an input quantum has a value of zero
(a differential linearity error of –1LSB), a missing code will
occur.
LINEARITY ERROR
ADC574AKP, KN, KH and TH grades are guaranteed to
have no missing codes to 12-bit resolution over their respective specification temperature ranges.
Linearity error is defined as the deviation of actual code
transition values from the ideal transition values. Ideal
transition values lie on a line drawn through zero (or minus
full scale for bipolar operation) and plus full scale. The zero
value is located at an analog input value 1/2LSB before the
first code transition (000H to 001H). The full-scale value is
located at an analog value 3/2LSB beyond the last code
transition (FFEH to FFFH) (see Figure 1).
Full-Scale
Calibration
Error
Rotates
The
Line
FFFH
FFEH
FFDH
802H
Digital Output
UNIPOLAR OFFSET ERROR
An ADC574A connected for unipolar operation has an
analog input range of 0V to plus full scale. The first output
code transition should occur at an analog input value 1/2
LSB above 0V. Unipolar offset error is defined as the
deviation of the actual transition value from the ideal value.
The unipolar offset temperature coefficient specifies the
change of this transition value versus a change in ambient
temperature.
BIPOLAR OFFSET ERROR
A/D converter specifications have historically defined bipolar offset as the first transition value above the minus fullscale value. The ADC574A specification, however, follows
the terminology defined for the 574 converter several years
ago. Thus, bipolar offset is located near the midscale value
of 0V (bipolar zero) at the output code transition 7FFH to
800H.
801H
800H
7FFH
7FEH
Offset
Error
Shifts
The Line
002H
(Bipolar
Offset
Transaction)
001H
000H
1/2LSB
Zero
(–Full Scale)
Midscale
(Bipolar
Zero)
Zero
1/2LSB
(–Full-Scale
Calibration
Transition)
Analog Input
Bipolar offset error for the ADC574A is defined as the
deviation of the actual transition value from the ideal
transition value located 1/2LSB below 0V. The bipolar
offset temperature coefficient specifies the maximum change
of the code transition value versus a change in ambient
temperature.
3/2LSB
+Full
+Full-Scale Scale
Calibration
Transition
FIGURE 1. ADC574A Transfer Characteristics Terminology.
FULL SCALE CALIBRATION ERROR
The last output transition (FFEH to FFFH) occurs for an
analog input value 3/2LSB below the nominal full-scale
value. The full-scale calibration error is the deviation of the
actual analog value at the last transition point from the ideal
value. The full-scale calibration temperature coefficient
specifies the maximum change of the code transition value
versus a change in ambient temperature.
Thus, for a converter connected for biopolar operation and
with a full-scale range (or span) of 20V (±10V), the zero
value of –10V is 2.44mV below the first code transition
(000H to 001H at –9.99756V) and the plus full-scale value of
+10V is 7.32mV above the last code transition (FFEH to
FFFH at +9.99268) (see Table I).
NO MISSING CODES
(DIFFERENTIAL LINEARITY ERROR)
A specification which guarantees no missing codes requires
that every code combination to appear in a monotonicallyincreasing sequence as the analog input is increased through-
BINARY (BIN) OUTPUT
POWER SUPPLY SENSITIVITY
Electrical specifications for the ADC574A assume the
application of the rated power supply voltages of +5V and
±12V or ±15V. The major effect of power supply voltage
INPUT VOLTAGE RANGE AND LSB VALUES
Analog Input Voltage Range
Defined as:
±10V
±5V
0 to +10V
0 to +20V
One Least Significant Bit (LSB)
FSR
2n
n=8
n =12
20V
2n
78.13mV
4.88mV
10V
2n
39.06mV
2.44mV
10V
2n
39.06mV
2.44mV
20V
2n
78.13mV
4.88mV
+Full-Scale Calibration
Midscale Calibration (Bipolar Offset)
+10V – 3/2LSB
0 – 1/2LSB
+5 – 3/2LSB
0 – 1/2LSB
+10V – 3/2LSB
+5V – 1/2LSB
+10V – 3/2LSB
±10V – 1/2LSB
Output Transition Values
FFEH to FFFH
7FFH to 800H
TABLE I. Input Voltages, Transition Values, and LSB Values.
®
5
ADC574A
deviations from the rated values will be a small change in the
full-scale calibration value. This change, of course, results in
a proportional change in all code transition values (i.e., a
gain error). The specification describes the maximum change
in the full-scale calibration value from the initial value for a
change in each power supply voltage.
to obtain noise-free operation. Noise on the power supply
lines can degrade the converter’s performance. Noise and
spikes from a switching power supply are especially
troublesome.
ANALOG SIGNAL SOURCE IMPEDANCE
The signal source supplying the analog input signal to the
ADC574A will be driving into a nominal DC input impedance of either 5kΩ or 10kΩ. However, the output impedance
of the driving source should be very low, such as the output
impedance provided by a wideband, fast-settling operational
amplifier. Transients in A/D input current are caused by the
changes in output current of the internal D/A converter as it
tests the various bits. The output voltage of the driving
source must remain constant while furnishing these fast
current changes. If the application requires a sample/hold,
select a sample/hold with sufficient bandwidth to preserve
the accuracy or use a separate wideband buffer amplifier to
lower the output impedance.
TEMPERATURE COEFFICIENTS
The temperature coefficients for full-scale calibration, unipolar offset and bipolar offset specify the maximum change
from the +25°C value to the value at TMIN or TMAX.
QUANTIZATION UNCERTAINTY
Analog-to-digital converters have an inherent quantization
error of ±1/2LSB. This error is a fundamental property of the
quantization process and cannot be eliminated.
CODE WIDTH (QUANTUM)
Code width, or quantum, is defined as the range of analog
input values for which a given output code will occur. The
ideal code width is 1LSB.
RANGE CONNECTIONS
The ADC574A offers four standard input ranges: 0V to
+10V, 0V to +20V, ±5V, and ±10V. If a 10V input range is
required, the analog input signal should be connected to pin
13 of the converter. A signal requiring a 20V range is
connected to pin 14. In either case the other pin of the two
is left unconnected. Full-scale and offset adjustments are
described below.
INSTALLATION
LAYOUT PRECAUTIONS
Analog (pin 9) and digital (pin 15) commons are not connected together internally in the ADC574A, but should be
connected together as close to the unit as possible and to an
analog common ground plane beneath the converter on the
component side of the board. In addition, a wide conductor
pattern should run directly from pin 9 to the analog supply
common, and a separate wide conductor pattern from pin 15
to the digital supply common. Analog common (pin 9)
typically carries +8mA.
To operate the converter with a 10.24V (2.5mV LSB) or
20.48V (5mV LSB) input range, insert a 120Ω, 1% metalfilm resistor in series with pin 13 for the 10.24V range, or a
240Ω, 1% metal-film resistor in series with pin 14 for the
20.48V range. Offset and gain adjustments are still performed as described below. However, you must recalculate
full-scale adjustment voltages proportionately. A fixed metalfilm resistor can be used because the input impedance of the
ADC574A is trimmed to less than ±6% of the nominal
value.
If the single-point system common cannot be established
directly at the converter, pin 9 and 15 should still be
connected together at the converter; a single wide conductor
pattern then connects these two pins to the system common.
In either case, the common return of the analog input signal
should be referenced to pin 9 of the ADC. This prevents any
voltage drops that might occur in the power supply common
returns from appearing in series with the input signal.
CALIBRATION
OPTIONAL EXTERNAL FULL-SCALE
AND OFFSET ADJUSTMENTS
Offset and full-scale errors may be trimmed to zero using
external offset and full-scale trim potentiometers connected
to the ADC574A as shown in Figures 2 and 3 for unipolar
and bipolar operation.
Coupling between analog input and digital lines should be
minimized by careful layout. For instance, if the lines must
cross, they should do so at right angles. Parallel analog and
digital lines should be separated from each other by a pattern
connected to common.
If external full scale and offset potentiometers are used, the
potentiometers and associated resistors should be located as
close to the ADC574A as possible. If no trim adjustments
are used, the fixed resistors should likewise be as close as
possible.
CALIBRATION PROCEDURE —
UNIPOLAR RANGES
If adjustment of unipolar offset and full scale is not required,
replace R2 with a 50Ω, 1% metal-film resistor and connect
pin 12 to pin 9, omitting the adjustment network.
POWER SUPPLY DECOUPLING
Logic and analog power supplies should be bypassed with
10µF tantalum-type capacitors located close to the converter
If adjustment is required, connect the converter as shown in
Figure 2. Sweep the input through the end-point transition
voltage (0V + 1/2LSB; +1.22mV for the 10V range, +2.44mV
®
ADC574A
6
+VCC
Unipolar
Offset
Adjust
R1
100kΩ
Full-Scale
Adjust
Full-Scale Adjust
R2
10
Ref In
100Ω
ADC574A
100kΩ
8
–VCC
Ref Out
Bipolar
Offset
Adjust
100Ω
12
Analog
Input
10V
Range
Ref In
8
Ref Out
Bipolar Offset
12
Bipolar Offset
Analog
Input
13
ADC574A
R1 100Ω
10V
Range
20V
Range
Comparator
20V
Range
10
R2 100Ω
13
Comparator
14
14
9
9
Analog
Common
Analog
Common
FIGURE 2. Unipolar Configuration.
FIGURE 3. Bipolar Configuration.
for the 20V range) that causes the output code to be DB0 ON
(high). Adjust potentiometer R1 until DB0 is alternately
toggling ON and OFF with all other bits OFF. Then adjust
full scale by applying an input voltage of nominal full-scale
value minus 3/2LSB, the value which should cause all bits
to be ON. This value is +9.9963V for the 10V range and
+19.9927V for the 20V range. Adjust potentiometer R2 until
bits DB1-DB11 are ON and DB0 is toggling ON and OFF.
DB0 to toggle ON and OFF with all other bits OFF. To
adjust full-scale, apply a DC input signal which is 3/2LSB
below the nominal plus full-scale value (+4.9963V for ±5V
range, +9.9927V for ±10V range) and adjust R2 for DB0 to
toggle ON and OFF with all other bits ON.
CONTROLLING THE ADC574A
The Burr-Brown ADC574A can be easily interfaced to most
microprocessor systems and other digital systems. The microprocessor may take full control of each conversion, or the
converter may operate in a stand-alone mode, controlled
only by the R/C input. Full control consists of selecting an
8- or 12-bit conversion cycle, initiating the conversion, and
reading the output data when ready—choosing either 12 bits
all at once, or 8 bits followed by 4 bits in a left-justified
format. The five control inputs (12/8, CS, AO, R/C, and CE)
are all TTL/CMOS-compatible. The functions of the control
inputs are described in Table II. The control function truth
table is listed in Table III.
CALIBRATION PROCEDURE—BIPOLAR RANGES
If external adjustments of full-scale and bipolar offset are
not required, the potentiometers may be replaced by 50Ω,
1% metal-film resistors.
If adjustments are required, connect the converter as shown
in Figure 3. The calibration procedure is similar to that
described above for unipolar operation, except that the offset
adjustment is performed with an input voltage which is
1/2LSB above the minus full-scale value (–4.9988V for the
±5V range, –9.9976V for the ±10V range). Adjust R1 for
PIN
DESIGNATION
DEFINITION
FUNCTION
CE (Pin 6)
Chip Enable
(active high)
Must be high (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a conversion.
CS (Pin 3)
Chip Select
(active low)
Must be low (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate a conversion.
R/C(Pin 5)
Read/Convert
(“1” = read)
(“0” = convert)
Must be low (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion.
Must be high (“1”) to read output data. 0-1 edge may be used to initiate a read operation.
AO (Pin 4)
Byte Address
Short Cycle
In the start-convert mode, AO selects 8-bit (AO = “1”) or 12-bit (AO = "0") conversion mode. When reading output data
in two 8-bit bytes, AO = “0” accesses 8 MSBs (high byte) and AO = “1” accesses 4 LSBs and trailing “0s” (low byte).
12/8 (Pin 2)
Data Mode Select
(“1” = 12 bits)
(“0” = 8 bits)
When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the MSBs
or LSBs as determined by the AO line.
TABLE II. ADC574A Control Line Functions.
®
7
ADC574A
CE
CS
R/C
12/8
AO
0
X
X
1
0
0
X
X
0
0
0
0
X
X
X
X
X
X
X
X
1
0
0
X
X
0
1
0
1
0
1
X
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
OPERATION
None
None
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit output
Enable 8 MSBs only
Enable 4 LSBs plus
4 trailing zeros
tDS
Status
DB11-DB0
tHRH
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
STS Delay After Data Valid
High R/C Pulse Width
Data Access Time
TYP
MAX
50
200
25
300
150
400
1000
150
tHDR
tDDR
DB11– High-Z
DB0
Data Valid
tC
High-Z State
FIGURE 5. R/C Pulse High—Outputs Enabled Only While
R/C Is High.
an 8-bit conversion, the 3LSBs (DB0-DB2) will be low
(logic 0) and DB3 will be high (logic 1). AO is latched
because it is also involved in enabling the output buffers. No
other control inputs are latched.
CONVERSION START
The converter is commanded to initiate a conversion by a
transition occurring on any of three logic inputs (CE, CS,
and R/C) as shown in Table III. Conversion is initiated by
the last of the three to reach the required state and thus all
three may be dynamically controlled. If necessary, all three
may change states simultaneously, and the nominal delay
time is the same regardless of which input actually starts
conversion. If it is desired that a particular input establish the
actual start of conversion, the other two should be stable a
minimum of 50ns prior to the transition of that input. Timing
relationships for start of conversion timing are illustrated in
Figure 6. The specifications for timing are contained in
Table V.
UNITS
ns
ns
ns
ns
ns
ns
The STATUS output indicates the current state of the converter by being in a high state only during conversion.
During this time the three state output buffers remain in a
high-impedance state, and therefore data cannot be read
during conversion. During this period additional transitions
of the three digital inputs which control conversion will be
ignored, so that conversion cannot be prematurely terminated or restarted. However, if AO changes state after the
beginning of conversion, any additional start conversion
transition will latch the new state of AO, possibly resulting
in an incorrect conversion length (8 bits vs 12 bits) for that
conversion.
TABLE IV. Stand-Alone Mode Timing.
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the AO input, which is latched upon receipt of a conversion start transition (described below). If AO is latched high,
the conversion continues for 8 bits. The full 12-bit conversion will occur if AO is low. If all 12 bits are read following
®
ADC574A
Data Valid
tDS
Status
Figure 4 illustrates timing when conversion is initiated by an
R/C pulse which goes low and returns to the high state
during the conversion. In this case, the three-state outputs
go to the high-impedance state in response to the falling
edge of R/C and are enabled for external access of the data
after completion of the conversion. Figure 5 illustrates the
timing when conversion is initiated by a positive R/C pulse.
In this mode the output data from the previous conversion is
enabled during the positive portion of R/C. A new conversion is started on the falling edge of R/C, and the three-state
outputs return to the high-impedance state until the next
occurrence of a high R/C pulse. Table IV lists timing
specifications for stand-alone operation.
tHRL
tDS
tHDR
tHS
tHRH
tDDR
tHS
High-Z State
R/C
Conversion is initiated by a high-to-low transition of R/C.
The three-state data output buffers are enabled when R/C is
high and STATUS is low. Thus, there are two possible
modes of operation; conversion can be initiated with either
positive or negative pulses. In either case the R/C pulse must
remain low for a minimum of 50ns.
MIN
Data Valid
FIGURE 4. R/C Pulse Low—Outputs Enabled After Conversion.
STAND-ALONE OPERATION
For stand-alone operation, control of the converter is accomplished by a single control line connected to R/C. In this
mode CS and AO are connected to digital common and CE
and 12/8 are connected to VLOGIC (+5V). The output data are
presented as 12-bit words. The stand-alone mode is used in
systems containing dedicated input ports which do not
require full bus interface capability.
PARAMETER
tC
tHDR
TABLE III. Control Input Truth Table.
SYMBOL
tHRL
R/C
8
SYMBOL
Convert Mode
tDSC
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC
tC
Read Mode
tDD
tHD
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS
PARAMETER
MIN
STS Delay from CE
CE Pulse Width
CS to CE Setup time
CS low during CE high
R/C to CE setup
R/C low during CE high
AO to CE setup
AO valid during CE high
Conversion time, 12-bit cycle
8-bit cycle
50
50
50
50
50
0
50
15
10
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
AO to CE setup
CS valid after CE low
R/C high after CE low
AO valid after CE low
STS delay after data valid
TYP
MAX
UNITS
60
30
20
20
0
20
200
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
20
20
13
25
17
75
35
100
0
25
50
0
50
0
0
50
300
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
25
400
1000
NOTE: Specifications are at +25°C and measured at 50% level of transitions.
TABLE V. Timing Specifications.
CE
CE
tHEC
tSSR
tSSC
tHSR
CS
CS
tSRC
tHSC
tHRR
R/C
R/C
tSRR
tHRC
AO
AO
tHAR
tSAR
tSAC
STS
tHAC
STS
tDSC
DB11–
DB0
tHS
tC
DB11–
DB0
High Impedance
High-Z
tHD
Data Valid
tDD
tHL
FIGURE 6. Conversion Cycle Timing.
FIGURE 7. Read Cycle Timing.
READING OUTPUT DATA
desired. When 12/8 is high, all 12 output lines (DB0–DB11)
are enabled simultaneously for full data word transfer to a
12-bit or 16-bit bus. In this situation the AO state is ignored.
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C high, STATUS low,
CE high, and CS low. Upon satisfaction of these conditions
the data lines are enabled according to the state of inputs
12/8 and AO. See Figure 7 and Table V for timing relationships and specifications.
When 12/8 is low, the data is presented in the form of two
8-bit bytes, with selection of the byte of interest accomplished by the state of AO during the read cycle. Connection
of the ADC574A to an 8-bit bus for transfer of left-justified
data is illustrated in Figure 8. The AO input is usually driven
by the least significant bit of the address bus, allowing
storage of the output data word in two consecutive memory
locations.
In most applications the 12/8 input will be hard-wired in
either the high or low condition, although it is fully TTLand CMOS-compatible and may be actively driven if
®
9
ADC574A
When AO is low, the byte addressed contains the 8MSBs.
When AO is high, the byte addressed contains the 4LSBs
from the conversion followed by four logic zeros which
have been forced by the control logic. The left-justified
formats of the two 8-bit bytes are shown in Figure 8. The
design of the ADC574A guarantees that the AO input may be
toggled at any time with no damage to the converter; the
outputs which are tied together as illustrated in Figure 9
cannot be enabled at the same time.
In the majority of applications the read operation will be
attempted only after the conversion is complete and the
STATUS output has gone low. In those situations requiring
the earliest possible access to the data, the read may be
started as much as 1.15µs (tDD max + tHS min) before
STATUS goes low. Refer to Figure 7 for these timing
relationships.
Word 1
Word 2
Processor
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Converter
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
FIGURE 8. 12-Bit Data Format for 8-Bit Systems.
2
12/8
STATUS
28
DB11 (MSB)
27
26
AO
4
25
AO
24
Address
Bus
23
22
ADC574A
21
20
19
18
17
DB0 (LSB)
16
Digital Common
15
FIGURE 9. Connection to an 8-Bit Bus.
®
ADC574A
10
Data
Bus