AD ADN4604

4.25 Gbps,
16 × 16, Digital Crosspoint Switch
ADN4604
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DVCC
IP[15:0]
VCC
RX
VTTIE,
VTTIW
EQ
OP[15:0]
TX
16 × 16
SWITCH
MATRIX
PREEMPHASIS
IN[15:0]
VTTON,
VTTOS
ON[15:0]
CONNECTION
MAP 0
CONNECTION
MAP 1
OUTPUT
LEVEL
HOOKUP
TABLE
PER-PORT
OUTPUT
LEVEL
SETTINGS
RESET
UPDATE
I2C/SPI
ADDR1/SDI
ADDR0/CS
SDA/SDO
SCL/SCK
SERIAL
INTERFACE
CONTROL
LOGIC
ADN4604
VEE
07934-001
DC to 4.25 Gbps per port NRZ data rate
Programmable receive equalization
12 dB boost at 2 GHz
Compensates 40 inches of FR4 at 4.25 Gbps
Programmable transmit preemphasis/deemphasis
Up to 12 dB boost at 4.25 Gbps
Compensates 40 inches of FR4 at 4.25 Gbps
Low power: 130 mW per channel at 3.3 V (outputs enabled)
16 × 16, fully differential, nonblocking array
Double rank connection programming with dual
connection maps
Low jitter, typically 20 ps
Flexible I/O supply range
DC- or ac-coupled differential CML inputs
Programmable CML output levels
Per-lane input P/N pair inversion for routing ease
50 Ω on-chip I/O termination
Supports 8b/10b, scrambled or uncoded NRZ data
Serial (I2C slave or SPI) control interface
100-lead TQFP, Pb-free package
Figure 1.
APPLICATIONS
Fiber optic network switching
High speed serial backplane routing to OC-48 with FEC
XAUI: 10GBASE-KX4
Gigabit Ethernet over backplane: 1000BASE-KX
1×, 2×, and 4× Fibre Channel
InfiniBand®
Digital video (HDMI, DVI, DisplayPort, 3G-/HD-/SD-SDI)
Data storage networks
GENERAL DESCRIPTION
The ADN4604 is a 16 × 16 asynchronous, protocol agnostic,
digital crosspoint switch, with 16 differential PECL-/CMLcompatible inputs and 16 differential CML outputs.
The ADN4604 is optimized for nonreturn-to-zero (NRZ) signaling with data rates of up to 4.25 Gbps per port. Each port
offers a fixed level of input equalization and programmable
output swing and output preemphasis.
The ADN4604 nonblocking switch core implements a 16 × 16
crossbar and supports independent channel switching through
the serial control interface. The ADN4604 has low latency and
very low channel-to-channel skew.
An I2C® or SPI interface is used to control the device and provide access to advanced features, such as additional levels of
preemphasis and output disable.
The ADN4604 is packaged in a 100-lead TQFP package and
operates from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADN4604
TABLE OF CONTENTS
Features .............................................................................................. 1 Switch Core ................................................................................. 17 Applications ....................................................................................... 1 Transmitters ................................................................................ 19 Functional Block Diagram .............................................................. 1 Termination................................................................................. 23 General Description ......................................................................... 1 I C Serial Control Interface ........................................................... 24 Revision History ............................................................................... 2 Reset ............................................................................................. 24 Specifications..................................................................................... 3 I2C Data Write............................................................................. 24 Electrical Specifications ............................................................... 3 I2C Data Read.............................................................................. 25 I2C Timing Specifications ............................................................ 4 SPI Serial Control Interface .......................................................... 26 SPI Timing Specifications ........................................................... 5 Register Map ................................................................................... 28 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 32 ESD Caution .................................................................................. 6 Supply Sequencing ..................................................................... 34 Pin Configuration and Function Descriptions ............................. 7 Power Dissipation....................................................................... 34 Typical Performance Characteristics ........................................... 10 Output Compliance ................................................................... 34 Theory of Operation ...................................................................... 16 Printed Circuit Board (PCB) Layout Guidelines ................... 36 Introduction ................................................................................ 16 Outline Dimensions ....................................................................... 38 Receivers ...................................................................................... 16 Ordering Guide .......................................................................... 38 2
REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
ADN4604
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VCC = 3.3 V, VTTIx = 3.3 V, VTTOx = 3.3 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 Ω, data rate = 4.25 Gbps, ac-coupled inputs and outputs, differential
input swing = 800 mV p-p, TA = 27°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Data Rate (DR) per Channel (NRZ)
Deterministic Jitter
Random Jitter
Residual Deterministic Jitter with
Receive Equalization
Residual Deterministic Jitter with
Transmit Preemphasis
Propagation Delay
Channel-to-Channel Skew
Switching Time
Output Rise/Fall Time
INPUT CHARACTERISTICS
Differential Input Voltage Swing
Input Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Per-Port Output Current
TERMINATION CHARACTERISTICS
Resistance
Temperature Coefficient
POWER SUPPLY
Operating Range
VCC
DVCC
VTTIE, VTTIW
VTTON, VTTOS
Conditions
Min
Typ
DC
Data rate = 4.25 Gbps, no channel
RMS, no channel
Data rate = 4.25 Gbps, 20 in. FR4, EQ boost = 12 dB
Data rate = 4.25 Gbps, 30 in. FR4, EQ boost = 12 dB
Data rate = 4.25 Gbps, 40 in. FR4, EQ boost = 12 dB
Data rate = 4.25 Gbps, 20 in. FR4, PE boost = 4.2 dB
Data rate = 4.25 Gbps, 30 in. FR4, PE boost = 6 dB
Data rate = 4.25 Gbps, 40 in. FR4, PE boost = 6 dB
Input to output, EQ boost = 12 dB
Max
Unit
4.25
Gbps
ps p-p
ps rms
ps p-p
ps p-p
ps p-p
ps p-p
ps p-p
ps p-p
ps
ps
ns
ps
2000
mV p-p diff
V
V
20
1
27
43
70
23
25
35
800
±50
100
75
Update logic switching to 50% output data
20% to 80%
VICM 1 = VCC − 0.6 V; VCC = VMIN to VMAX, TA = TMIN to TMAX
Single-ended absolute voltage level, VL
Single-ended absolute voltage level, VH
200
VEE + 1.1
Differential, PE boost = 0 dB, default output level, at dc
Single-ended absolute voltage level, VL
Single-ended absolute voltage level, VH
PE boost = 0 dB, default output level
PE boost = 6 dB, default output level
600
VCC – 1.3
Single-ended, VCC = 2.7 V to 3.6 V, VTTI = 2.2 V to 3.6 V,
VTTO = 2.2 V to 3.6 V, TA = TMIN to TMAX;
44
VCC + 0.3
800
900
VCC + 0.2
mV p-p diff
V
V
mA
mA
56
Ω
16
32
50
0.025
VEE = 0 V
VEE = 0 V
VEE = 0 V
VEE = 0 V
2.7
2.7
1.3
2.2 2
Supply Current
ICC
IDVCC
ITTIE + ITTIW + ITTON + ITTOS
Outputs disabled
Supply Current
ICC
IDVCC
ITTIE + ITTIW + ITTON + ITTOS
Supply Current
ICC
IDVCC
ITTIE + ITTIW + ITTON + ITTOS
All outputs enabled, ac-coupled I/O, 400 mV I/O swings
(800 mV p-p differential), PE boost = 0 dB,
50 Ω far-end terminations
All outputs enabled, ac-coupled I/O, 400 mV I/O swings
(800 mV p-p differential), PE boost = 6 dB,
50 Ω far-end terminations
Rev. 0 | Page 3 of 40
Ω/°C
3.3
3.3
3.3
3.3
3.6
3.6
VCC + 0.3
VCC + 0.3
V
V
V
V
95
20
0
110
35
10
mA
mA
mA
342
20
256
370
35
280
mA
mA
mA
486
20
512
540
35
540
mA
mA
mA
ADN4604
Parameter
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
θJB
θJC
LOGIC CHARACTERISTICS
Input High Voltage Threshold (VIH)
Input Low Voltage Threshold (VIL)
Output High Voltage (VOH)
Output Low Voltage (VOL)
1
2
Conditions
Min
Typ
−40
Still air; JEDEC 4-layer test board
Still air
At the exposed pad
Max
Unit
+85
°C
°C/W
°C/W
°C/W
VCC
0.3 × VCC
V
V
V
V
24.9
11.6
0.95
DVCC = 3.3 V
DVCC = 3.3 V
2 kΩ pull-up resistor to DVCC
IOL = 3 mA
0.7 × VCC
VEE
DVCC
VEE
0.4
VICM is the input common-mode voltage.
Minimum VTTO is only applicable for a limited range of output current settings. Refer to the Power Dissipation section.
I2C TIMING SPECIFICATIONS
SDA
tSU:DAT
tf
tLOW
tf
tHD:STA
tf
tBUF
tf
tHD:STA
S
tHD:DAT
tSU:STA
tHIGH
07934-002
SCL
tSU:STO
Sr
P
S
Figure 2. I2C Timing Diagram
Table 2. I2C Timing Specifications
Parameter
SCL Clock Frequency
Hold Time for a Start Condition
Setup Time for a Repeated Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Data Hold Time
Data Setup Time
Rise Time for Both SDA and SCL
Fall Time for Both SDA and SCL
Setup Time for Stop Condition
Bus-Free Time Between a Stop Condition and a Start Condition
Bus Idle Time After a Reset
Reset Pulse Width
Rev. 0 | Page 4 of 40
Symbol
fSCL
tHD;STA
tSU;STA
tLOW
tHIGH
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
tBUF
Min
0
0.6
0.6
1.3
0.6
0
10
1
1
0.6
1
10
10
Max
400+
300
300
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
ns
ns
ns
ADN4604
SPI TIMING SPECIFICATIONS
CS
t1
t2
t7
SCK
SDI
A7
A6
A5
t5
A4
A3
t6
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
t4
SDO
X
X
X
X
X
X
X
X
X
t8
X
X
X
X
X
X
07934-003
t3
X
Figure 3. SPI Write Timing Diagram
t9
CS
t1
t2
t7
SCK
A7
A6
A5
t5
A4
A3
A2
t6
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
t8
t4
SDO
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
07934-004
t3
SDI
Figure 4. SPI Read Timing Diagram
Table 3. SPI Timing Specifications
Parameter
SCK Clock Frequency
CS to SCK Setup Time
SCK High Pulse Width
SCK Low Pulse Width
Data Access Time After SCK Falling Edge
Data Setup Time Prior to SCK Rising Edge
Data Hold Time After SCK Rising Edge
CS to SCK Hold Time
CS to SDO High Impedance
CS High Pulse Width
Symbol
fSCK
t1
t2
t3
t4
t5
t6
t7
t8
t9
Rev. 0 | Page 5 of 40
Min
0
10
40
40
Max
10
35
20
10
10
40
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADN4604
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VCC to VEE
DVCC to VEE
VTTIE, VTTIW
VTTON, VTTOS
Internal Power Dissipation 1
Differential Input Voltage
Logic Input Voltage
Storage Temperature Range
Lead Temperature Range
Junction Temperature
1
Rating
3.7 V
3.7 V
VCC + 0.6 V
VCC + 0.6 V
4.9 W
2.0 V
VEE – 0.3 V < VIN < VCC + 0.6 V
−65°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Internal power dissipation is for the device in free air.
TA = 27°C; θJA = 24.9°C/W in still air.
Rev. 0 | Page 6 of 40
ADN4604
SCL/SCK
OP8
ON8
VEE
OP9
ON9
VTTON
OP10
ON10
VCC
OP11
ON11
VEE
OP12
ON12
VCC
OP13
ON13
VTTON
OP14
ON14
VEE
OP15
ON15
DVCC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75 SDA/SDO
RESET 1
IP0
PIN 1
2
74 IN15
73 IP15
IN0 3
4
72 VCC
IP1 5
71 IN14
IN1 6
70 IP14
VCC
69 VTTIE
VTTIW 7
68 IN13
IP2 8
67 IP13
ADN4604
IN2 9
VEE 10
66 VEE
TOP VIEW
(Not to Scale)
IP3 11
65 IN12
64 IP12
IN3 12
VCC 13
63 VCC
IP4 14
62 IN11
IN4 15
61 IP11
VEE 16
60 VEE
IP5 17
59 IN10
IN5 18
58 IP10
57 VTTIE
VTTIW 19
56 IN9
IP6 20
IN6 21
55 IP9
VCC 22
54 VCC
IP7 23
53 IN8
IN7 24
52 IP8
51 ADDR0/CS
UPDATE 25
NOTES
1. THE ADN4604 TQFP HAS AN EXPOSED PADDLE (EPAD) ON THE UNDERSIDE OF THE PACKAGE THAT AIDS
IN HEAT DISSIPATION. THE EPAD MUST BE ELECTRICALLY CONNECTED TO THE VEE SUPPLY PLANE
TO MEET THERMAL SPECIFICATIONS.
2. SDA/SCL/ADDR1/0 FOR I2C OPERATION.
SCK/SDO/SDI/CS FOR SPI OPERATION.
Figure 5. Pin Configuration
Rev. 0 | Page 7 of 40
07934-005
ADDR1/SDI
ON7
OP7
VEE
ON6
OP6
VTTOS
ON5
OP5
VCC
ON4
OP4
VEE
ON3
OP3
VCC
ON2
OP2
VTTOS
ON1
OP1
VEE
ON0
OP0
I2C/SPI
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ADN4604
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
RESET
Type
Control
2
3
4, 13, 22, 35, 41, 54, 63,
72, 85, 91
5
6
7, 19
IP0
IN0
VCC
Input
Input
Power
IP1
IN1
VTTIW
Input
Input
Power
8
9
10, 16, 29, 38, 47, 60, 66,
79, 88, 97, EPAD
11
12
14
15
17
18
20
21
23
24
25
IP2
IN2
VEE
Input
Input
Power
IP3
IN3
IP4
IN4
IP5
IN5
IP6
IN6
IP7
IN7
UPDATE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Control
26
27
28
30
31
32, 44
33
34
36
37
39
40
42
43
45
46
48
49
50
51
52
53
55
56
I2C/SPI
OP0
ON0
OP1
ON1
VTTOS
OP2
ON2
OP3
ON3
OP4
ON4
OP5
ON5
OP6
ON6
OP7
ON7
ADDR1/SDI
ADDR0/CS
IP8
IN8
IP9
IN9
Control
Output
Output
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Control
Control
Input
Input
Input
Input
Description
Configuration Registers Reset, Active Low. This pin is normally pulled up
to DVCC.
High Speed Input.
High Speed Input Complement.
Positive Supply.
High Speed Input.
High Speed Input Complement.
Input Termination Supply (West). These pins are normally tied to the
VTTIE pins.
High Speed Input.
High Speed Input Complement.
Negative Supply.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
Second Rank Write Enable, Active Low. This pin is normally pulled up
to DVCC.
I2C/SPI Control Interface Selection, I2C Active Low.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
Output Termination Supply (South). These pins are normally tied to the VTTON pins.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
I2C Slave Address Bit 1 (MSB) or SPI Data Input.
I2C Slave Address Bit 0 (LSB) or SPI Chip Select (Active Low).
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
Rev. 0 | Page 8 of 40
ADN4604
Pin No.
57, 69
58
59
61
62
64
65
67
68
70
71
73
74
75
76
77
78
80
81
82, 94
Mnemonic
VTTIE
IP10
IN10
IP11
IN11
IP12
IN12
IP13
IN13
IP14
IN14
IP15
IN15
SDA/SDO
SCL/SCK
OP8
ON8
OP9
ON9
VTTON
Type
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Control
Control
Output
Output
Output
Output
Power
83
84
86
87
89
90
92
93
95
96
98
99
100
OP10
ON10
OP11
ON11
OP12
ON12
OP13
ON13
OP14
ON14
OP15
ON15
DVCC
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Description
Input Termination Supply (East). These pins are normally tied to the VTTIW pins.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
I2C Data or SPI Data Output.
I2C Clock or SPI Clock.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
Output Termination Supply (North). These pins are normally tied to
the VTTOS pins.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
Digital Positive Supply.
Rev. 0 | Page 9 of 40
ADN4604
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VTTIx = 3.3 V, VTTOx = 3.3 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 Ω, data rate = 4.25 Gbps, ac-coupled inputs and outputs, differential
input swing = 800 mV p-p, TA = 27°C, unless otherwise noted.
200mV/DIV
DATA OUT
2
50Ω CABLES
2
OUTPUT 2
PIN
INPUT
PIN
50Ω CABLES
2
50Ω
ADN4604
PATTERN
GENERATOR
AC-COUPLED
EVALUATION
BOARD
TP2
HIGH SPEED
SAMPLING
OSCILLOSCOPE
07934-006
TP1
0.167IU/DIV
REFERENCE EYE DIAGRAM AT TP1
0.167IU/DIV
0.167IU/DIV
Figure 8. 4.25 Gbps Input Eye (TP1 from Figure 6)
Figure 10. 4.25 Gbps Output Eye (TP2 from Figure 6)
Rev. 0 | Page 10 of 40
07934-010
0.167IU/DIV
07934-008
200mV/DIV
Figure 9. 3.25 Gbps Output Eye (TP2 from Figure 6)
200mV/DIV
Figure 7. 3.25 Gbps Input Eye (TP1 from Figure 6)
07934-009
200mV/DIV
0.167IU/DIV
07934-007
200mV/DIV
Figure 6. Standard Test Circuit
ADN4604
200mV/DIV
DATA OUT
2
50Ω CABLES
2
FR4 TEST BACKPLANE
2
50Ω CABLES
2
DIFFERENTIAL
STRIPLINE TRACES
TP1
TP2
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
LENGTHS = 10 INCHES, 20 INCHES,
30 INCHES, 40 INCHES
50Ω CABLES
2
50Ω
ADN4604
AC-COUPLED
EVALUATION
BOARD
TP3
HIGH
SPEED
SAMPLING
OSCILLOSCOPE
07934-011
PATTERN
GENERATOR
INPUT OUTPUT 2
PIN
PIN
0.167IU/DIV
REFERENCE EYE DIAGRAM AT TP1
0.167IU/DIV
0.167IU/DIV
07934-015
0.167IU/DIV
Figure 13. 4.25 Gbps Input Eye, 40-Inch FR4 Input Channel
(TP2 from Figure 11)
07934-013
200mV/DIV
Figure 14. 4.25 Gbps Output Eye, 20-Inch FR4 Input Channel, EQ = 12 dB
(TP3 from Figure 11)
200mV/DIV
Figure 12. 4.25 Gbps Input Eye, 20 Inch FR4 Input Channel
(TP2 from Figure 11)
07934-014
200mV/DIV
0.167IU/DIV
07934-012
200mV/DIV
Figure 11. Equalization Test Circuit
Figure 15. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, EQ = 12 dB
(TP3 from Figure 11)
Rev. 0 | Page 11 of 40
ADN4604
PATTERN
GENERATOR
2
50Ω CABLES
2
INPUT OUTPUT 2
PIN
PIN
50Ω CABLES
2
2
50Ω CABLES
2
50Ω
HIGH
DIFFERENTIAL
STRIPLINE TRACES
SPEED
TP2
TP3
SAMPLING
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
OSCILLOSCOPE
LENGTHS = 10 INCHES, 20 INCHES,
30 INCHES, 40 INCHES
ADN4604
TP1
FR4 TEST BACKPLANE
AC-COUPLED
EVALUATION
BOARD
07934-016
200mV/DIV
DATA OUT
0.167IU/DIV
REFERENCE EYE DIAGRAM AT TP1
0.167IU/DIV
0.167IU/DIV
Figure 18. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, PE = 0 dB
(TP3 from Figure 16)
07934-020
0.167IU/DIV
07934-018
200mV/DIV
Figure 19. 4.25 Gbps Output Eye, 20-Inch FR4 Input Channel, PE = 4.2 dB
(TP3 from Figure 16)
200mV/DIV
Figure 17. 4.25 Gbps Output Eye, 20-Inch FR4 Output Channel, PE = 0 dB
(TP3 from Figure 16)
07934-019
200mV/DIV
0.167IU/DIV
07934-017
200mV/DIV
Figure 16. Preemphasis Test Circuit
Figure 20. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, PE = 6 dB
(TP3 from Figure 16)
Rev. 0 | Page 12 of 40
ADN4604
100
1000
900
800
EYE HEIGHT (mV p-p DIFF)
DETERMINISTIC JITTER (ps)
80
60
40
EQ = 0dB
20
700
600
500
400
300
200
EQ = 12dB
1
2
3
4
5
DATA RATE (Gbps)
0
07934-036
0
0
1
2
3
DATA RATE (Gbps)
4
5
07934-029
100
0
Figure 24. Eye Height vs. Data Rate
Figure 21. Deterministic Jitter vs. Data Rate
1000
100
800
EYE HEIGHT (mV p-p DIFF)
60
40
EQ = 0dB
600
500
400
300
200
20
EQ = 12dB
100
0
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
07934-034
0
2.5
700
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
07934-028
DETERMINISTIC JITTER (ps)
900
80
Figure 25. Eye Height vs. Supply Voltage
Figure 22. Deterministic Jitter vs. Supply Voltage
1000
100
800
EYE HEIGHT (mV p-p DIFF)
80
60
40
EQ = 0dB
EQ = 12dB
600
500
400
300
–20
0
20
100
40
60
TEMPERATURE (°C)
80
0
–40
–15
10
35
60
TEMPERATURE (°C)
Figure 26. Eye Height vs. Temperature
Figure 23. Deterministic Jitter vs. Temperature
Rev. 0 | Page 13 of 40
85
07934-037
0
–40
700
200
20
07934-035
DETERMINISTIC JITTER (ps)
900
100
90
90
80
80
DETERMINISTIC JITTER (ps)
100
60
EQ = 0dB
50
40
EQ = 12dB
30
70
30
10
20
30
40
INPUT FR4 TRACE LENGTH (Inches)
7.8dB
12dB
40
10
10
6dB
50
20
0
4.2dB
2dB
60
20
0
0dB
9.5dB
0
0
10
20
30
40
50
60
70
OUTPUT FR4 TRACE LENGTH (Inches)
07934-030
70
07934-031
DETERMINISTIC JITTER (ps)
ADN4604
Figure 30. Deterministic Jitter vs. Output FR4 Channel Length
Figure 27. Deterministic Jitter vs. Input FR4 Channel Length
100
100
80
DETERMINISTIC JITTER (ps)
DETERMINISTIC JITTER (ps)
80
60
40
EQ = 0dB
60
40
EQ = 0dB
EQ = 12dB
20
20
0
1.0
0.5
1.5
2.0
DIFFERENTIAL INPUT SWING (V p-p)
0
0.9
07934-033
0
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
INPUT COMMON-MODE VOLTAGE (V)
Figure 31. Deterministic Jitter vs. Input Common-Mode Voltage
Figure 28. Deterministic Jitter vs. Differential Input Swing
0
90
OUTPUT LEVEL = 1200mV p-p DIFF
OUTPUT LEVEL = 800mV p-p DIFF
OUTPUT LEVEL = 200mV p-p DIFF
80
–2
–4
70
–6
LOSS (dB)
60
50
40
30
–8
–10
–12
–16
10
–18
0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
OUTPUT TERMINATION VOLTAGE VTTOx (V)
3.4
3.6
–20
100k
6"
10"
20"
30"
40"
1M
10M
100M
FREQUENCY (Hz)
Figure 32. S21 Test Traces
Figure 29. Deterministic Jitter vs. Output Termination Voltage (VTTO)
Rev. 0 | Page 14 of 40
1G
07934-038
–14
20
07934-025
DETERMINISTIC JITTER (ps)
1.2
07934-032
EQ = 12dB
100
500,000
90
450,000
80
400,000
70
350,000
FALL TIME
40
250,000
200,000
30
150,000
20
100,000
10
50,000
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
0
–7
950
950
900
900
DELAY (ps)
EQ = 12dB
750
700
600
550
3.1
3.2
3.3
3.4
1
2
3
4
5
6
3.5
3.6
SUPPLY VOLTAGE (V)
EQ = 0dB
700
550
3.0
0
EQ = 12dB
600
2.9
–1
750
650
2.8
–2
800
650
500
2.7
–3
850
500
–40 –30 –20 –10
07934-023
DELAY (ps)
1000
EQ = 0
–4
Figure 36. Random Jitter Histogram
1000
800
–5
JITTER (ps)
Figure 33. Rise/Fall Time vs. Temperature
850
–6
07934-024
RISE TIME
300,000
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
Figure 34. Propagation Delay vs. Supply Voltage
07934-022
50
SAMPLES
60
07934-026
RISE/FALL TIME (ps)
ADN4604
Figure 37. Propagation Delay vs. Temperature
25
5
20
–5
0
RETURN LOSS (dB)
–10
HITS
15
10
XAUI_SPEC
–15
–20
S22
–25
S11
–30
–35
5
–40
770
780
790
800
810
820
PROPAGATION DELAY (ps)
830
840
–50
10M
100M
1G
FREQUENCY (Hz)
Figure 38. Return Loss (S11, S22)
Figure 35. Propagation Delay Histogram
Rev. 0 | Page 15 of 40
10G
07934-027
760
07934-021
–45
0
750
ADN4604
THEORY OF OPERATION
INTRODUCTION
RECEIVERS
The ADN4604 is a 16 × 16, buffered, asynchronous crosspoint
switch that provides input equalization, output preemphasis,
and output level programming capabilities. The receivers
integrate an equalizer that is optimized to compensate for
typical backplane losses. The switch supports multicast and
broadcast operation, allowing the ADN4604 to work in
redundancy and port-replication applications. The part offers
extensively programmable output levels and preemphasis
settings.
Input Structure and Input Levels
DVCC
EQ
SIMPLIFIED RECEIVER INPUT CIRCUIT
VTTIx
TX
16 × 16
SWITCH
MATRIX
VTTIE,
VTTIW
VCC
VCC
RX
IP[15:0]
The ADN4604 receiver inputs incorporate 50 Ω termination
resistors, ESD protection, and a fixed equalizer that is optimized for
operation over long backplane traces. Each receive channel also
provides a positive/negative (P/N) inversion function, which allows
the user to swap the sign of the input signal path to eliminate the
need for board-level crossovers in the receiver channel.
RP
52Ω
OP[15:0]
PREEMPHASIS
IN[15:0]
VTTON,
VTTOS
RN
52Ω
RLN
RL
R1
750Ω
IPx
Q1
R3
1kΩ
ON[15:0]
RLP
RL
INx
Q2
CONNECTION
MAP 0
CONNECTION
MAP 1
I1
OUTPUT
LEVEL
HOOKUP
TABLE
VEE
PER-PORT
OUTPUT
LEVEL
SETTINGS
Figure 40. Simplified Input Circuit
Equalization
RESET
UPDATE
SERIAL
INTERFACE
CONTROL
LOGIC
ADDR0/CS
SDA/SDO
SCL/SCK
ADN4604
07934-039
I2C/SPI
ADDR1/SDI
07934-040
R2
750Ω
VEE
The ADN4604 receiver incorporates a continuous time equalizer
(EQ) that provides 12 dB of high frequency boost to compensate
up to 40 inches of FR4 at 4.25 Gbps. Each input has an equalizer
control bit. By default, the programmable boost is set to 12 dB.
The boost can be set to 0 dB by programming a Logic 0 to the
respective register bit for the corresponding channel.
Figure 39. Block Diagram
The configuration of the crosspoint is controlled through
a serial interface. This interface supports both I2C and SPI
protocols, which can be selected using the I2C /SPI dedicated
control pin. There are two I2C address pins available as
described in Table 6.
Table 6. Serial Interface Control Modes
75
I2C/SPI = 0
Pin
Function
I2C Address
MSB
ADDR0
I2C Address
LSB
SDA
I2C Data
76
SCL
Pin
No.
50
51
Pin
Name
ADDR1
I2C Clock
Pin
Name
SDI
CS
SDO
SCK
I2C/SPI = 1
Pin
Function
SPI Data
Input
SPI Chip
Select
SPI Data
Output
SPI Clock
Table 7. Equalization Control Registers
EQ[15:0]
0
1
Equalization Boost
0 dB
12 dB (default)
Lane Inversion
The receiver P/N inversion is a feature intended to allow the
user to implement the equivalent of a board-level crossover in
a much smaller area and without additional via impedance
discontinuities that degrade the high frequency integrity of the
signal path. The P/N inversion is available independently for
each of the 16 input channels and is controlled by writing to the
SIGN bit of the RX control registers (Addresses 0x12 and
Address 0x13). Note that using this feature to account for signal
inversions downstream of the receiver requires additional
attention when switching connectivity.
Table 8. Signal Path Polarity Control
SIGN[15:0]
0
1
Rev. 0 | Page 16 of 40
Signal Path Polarity
Noninverting (default)
Inverting
ADN4604
SWITCH CORE
The ADN4604 switch core is a fully nonblocking 16 × 16 array
that allows multicast and broadcast configurations. The configuration of the switch core is programmed through the serial
control interface. The crosspoint configuration map controls
the connectivity of the switch core. The crosspoint configuration
map consists of a double-rank register architecture where each
rank consists of an 8-byte configuration map as shown in
Figure 41. The second rank registers contain the current state of
the crosspoint. The first rank registers contain the next state.
Each entry in the connection map stores four bits per output,
which indicates which of the 16 inputs are connected to a given
output. An entire connectivity matrix can be programmed at
once by passing data from the first rank registers into the
second rank registers.
The first rank registers are two separate volatile 8-byte memory
banks which store connection configurations for the crosspoint. Map 0 is the default map and is located at Address 0x90
to Address 0x97. By default, Map 0 contains a diagonal
connection configuration whereby Input 15 is connected to
Output 0, Input 14 to Output 1, Input 13 to Output 2, and so
on. Similarly, by default, Map 1 contains the opposite diagonal
connection configuration where Input 0 is connected to output
0, Input 1 to Output 1, and so on. Both maps are read/write
accessible registers. The active map is selected by writing to
the XPT table select register (Address 0x81).
The crosspoint is configured by addressing the register
assigned to the desired output and writing the desired
connection data into the first rank of latches in either Map 0
or Map 1. The connection data is equivalent to the binary
coded value of the input number. This process is repeated until
each of the desired connections is programmed.
In situations where multiple outputs are to be programmed to
a single input, a broadcast command is available. A broadcast
command is issued by writing the binary value of the desired
input to the XPT broadcast register (Address 0x82). The broadcast is applied to the selected map as selected in the map table
select register (Address 0x81).
All output connections are updated simultaneously by passing
the data from the first rank of latches into the second rank by
writing 0x01 to the XPT update register (Address 0x80). This
is a write-only register. Alternatively, the UPDATE pin can be
strobed low. Otherwise, this pin should be left high.
The current state of the crosspoint connectivity is available
by reading the XPT status registers (Address 0xB0 to Address
0xB7). Register descriptions for the Map 0, Map 1 and XPT
status registers are provided in Table 9. A complete register
map is provided in Table 18.
FIRST RANK REGISTERS
XPT MAP 0
0
OUTPUTS
15
SECOND RANK REGISTERS
INPUTS
0
XPT CORE
0
0
OUTPUTS
15
15
0
INPUTS
REGISTER 0x90 TO REGISTER 0x97
XPT MAP 1
OUTPUTS
1
15
MAP TABLE
SELECT
REGISTER 0x81
INPUTS
15
UPDATE PIN
UPDATE
REGISTER 0x80
15
REGISTER 0x98 TO REGISTER 0x9F
XPT STATUS READ
REGISTER 0xB0 TO REGISTER 0xB7
Figure 41. Crosspoint Connection Map Block Diagram
Rev. 0 | Page 17 of 40
07934-041
0
0
ADN4604
Table 9. XPT Control Registers
Register Name
Update
Map Table Select
Address
0x80
0x81
Bit
0
0
Bit Name
UPDATE
MAP TABLE SELECT
XPT Broadcast
XPT Map 0 Control 0
0x82
0x90
XPT Map 0 Control 1
0x91
XPT Map 0 Control 2
0x92
XPT Map 0 Control 3
0x93
XPT Map 0 Control 4
0x94
XPT Map 0 Control 5
0x95
XPT Map 0 Control 6
0x96
XPT Map 0 Control 7
0x97
XPT Map 1 Control 0
0x98
XPT Map 1 Control 1
0x99
XPT Map 1 Control 2
0x9A
XPT Map 1 Control 3
0x9B
XPT Map 1 Control 4
0x9C
XPT Map 1 Control 5
0x9D
XPT Map 1 Control 6
0x9E
XPT Map 1 Control 7
0x9F
XPT Status 0
0xB0
XPT Status 1
0xB1
XPT Status 2
0xB2
XPT Status 3
0xB3
XPT Status 4
0xB4
XPT Status 5
0xB5
XPT Status 6
0xB6
XPT Status 7
0xB7
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
BROADCAST[3:0]
OUT1[3:0]
OUT0[3:0]
OUT3[3:0]
OUT2[3:0]
OUT5[3:0]
OUT4[3:0]
OUT7[3:0]
OUT6[3:0]
OUT9[3:0]
OUT8[3:0]
OUT11[3:0]
OUT10[3:0]
OUT13[3:0]
OUT12[3:0]
OUT15[3:0]
OUT14[3:0]
OUT1[3:0]
OUT0[3:0]
OUT3[3:0]
OUT2[3:0]
OUT5[3:0]
OUT4[3:0]
OUT7[3:0]
OUT6[3:0]
OUT9[3:0]
OUT8[3:0]
OUT11[3:0]
OUT10[3:0]
OUT13[3:0]
OUT12[3:0]
OUT15[3:0]
OUT14[3:0]
OUT1[3:0]
OUT0[3:0]
OUT3[3:0]
OUT2[3:0]
OUT5[3:0]
OUT4[3:0]
OUT7[3:0]
OUT6[3:0]
OUT9[3:0]
OUT8[3:0]
OUT11[3:0]
OUT10[3:0]
OUT13[3:0]
OUT12[3:0]
OUT15[3:0]
OUT14[3:0]
Description
Updates XPT switch core (active high, write only)
0: Map 0 is selected
1: Map 1 is selected
All outputs connection assignment, write only
Output 1 connection assignment
Output 0 connection assignment
Output 3 connection assignment
Output 2 connection assignment
Output 5 connection assignment
Output 4 connection assignment
Output 7 connection assignment
Output 6 connection assignment
Output 9 connection assignment
Output 8 connection assignment
Output 11 connection assignment
Output 10 connection assignment
Output 13 connection assignment
Output 12 connection assignment
Output 15 connection assignment
Output 14 connection assignment
Output 1 connection assignment
Output 0 connection assignment
Output 3 connection assignment
Output 2 connection assignment
Output 5 connection assignment
Output 4 connection assignment
Output 7 connection assignment
Output 6 connection assignment
Output 9 connection assignment
Output 8 connection assignment
Output 11 connection assignment
Output 10 connection assignment
Output 13 connection assignment
Output 12 connection assignment
Output 15 connection assignment
Output 14 connection assignment
Output 1 connection status, read only
Output 0 connection status, read only
Output 3 connection status, read only
Output 2 connection status, read only
Output 5 connection status, read only
Output 4 connection status, read only
Output 7 connection status, read only
Output 6 connection status, read only
Output 9 connection status, read only
Output 8 connection status, read only
Output 11 connection status, read only
Output 10 connection status, read only
Output 13 connection status, read only
Output 12 connection status, read only
Output 15 connection status, read only
Output 14 connection status, read only
Rev. 0 | Page 18 of 40
Default
N/A
0x00
N/A
0xEF
0xCD
0xAB
0x89
0x67
0x45
0x23
0x01
0x10
0x32
0x54
0x76
0x98
0xBA
0xDC
0xFE
0xEF
0xCD
0xAB
0x89
0x67
0x45
0x23
0x01
ADN4604
TRANSMITTERS
Output Structure and Output Levels
The ADN4604 transmitter outputs incorporate 50 Ω termination resistors, ESD protection, and output current switches.
Each channel provides independent control of both the absolute
output level and the preemphasis output level. Note that the
choice of output level affects the output common-mode level.
VCC
ESD
VTTOx
V3
VC
RP
50Ω
LOOKUP TABLE
BASIC SETTINGS
RN
50Ω
V2
VP
TABLE
ENTRY 0
OPx
V1
VN
TABLE
ENTRY 1
ONx
Q1
Q2
TABLE
ENTRY 2
IDC + IPE
VEE
TABLE
ENTRY 3
07934-042
IT
TABLE
ENTRY 4
Figure 42. Simplified TX Output Circuit
TABLE
ENTRY 5
Preemphasis
Transmission line attenuation can be equalized at the transmitter using preemphasis. The transmit equalizer setting can
be chosen by matching the channel loss to the amount of boost
provided by the preemphasis.
TABLE
ENTRY 6
TABLE
ENTRY 7
PER OUTPUT PORT
16
16
16
OPx
IPx
TX
16
ONx
INx
16
16
16
16
16
16
2
3
Basic Settings
PE[2:0]
In the basic mode of operation, predefined preemphasis settings
are available through a lookup table. Each table entry requires
two bytes of memory. The amount of preemphasis provided
is independent of the full-scale current output. Transmitter
preemphasis levels, as well as dc output levels, can be set
through the serial control interface. The output level and
amount of preemphasis can be independently programmed
through advanced registers. By default, however, the total
output amplitude and preemphasis setting space is reduced
to a single table of basic settings that provides eight levels of
output equalization to ease programming for typical FR4
channels.
Table 10 summarizes the absolute output level, preemphasis
level, and high frequency boost for control setting. The full
resolution of eight settings is available through the serial
interface by writing to Bits[2:0] (the TX PE[2:0] bits) of the
Basic TX Control registers shown in Table 11. A single setting
is programmed to all outputs simultaneously by writing to the
0x18 broadcast address.
The TX has four possible output enable states (disabled,
standby, squelched, and enabled) controlled by the TX EN[1:0]
bits as shown in Table 11. Disabled is the lowest power-down
state. When squelched, the output voltage at both P and N
outputs will be the common-mode voltage as defined by the
output current settings. In standby, the output level of both P
and N outputs will be pulled up to the termination supply
(VTTON or VTTOS).
TX CTL
SELECT
PER PORT
OUTPUT LEVEL
ADVANCED SETTINGS
TX EN[1:0]
07934-043
ON-CHIP TERMINATION
The TX CTL SELECT bit (Bit 6) in the TX[15:0] basic control
register determines whether the preemphasis and output
current controls for the channel of interest are selected from
the predefined lookup table or directly from the TX[15:0]
Drive Control[1:0] registers (per channel). Figure 43 is an
illustration of the TX control circuit. Setting the TX CTL
SELECT bit low (default setting) selects preemphasis control
from the predefined, optimized lookup table (Address 0x60
to Address 0x6F).
16
Figure 43. Transmitter Control Block Diagram
In applications where the default preemphasis settings in the
lookup table are not sufficient, the lookup table entries can be
modified by programming the TX lookup table registers (0x60
to 0x6F) shown in Table 12. In applications where the eight
table entries are insufficient, each output can be programmed
individually.
Table 10. Preemphasis Boost and Overshoot vs. Setting
PE
Setting
0
Main Tap
Current
(mA)
16
Delayed Tap
Current (mA)
0
Boost
(dB)
0.0
Overshoot
(%)
0
DC Swing
(mV p-p)
800
1
16
2
2.0
25
800
2
16
5
4.2
62.5
800
3
16
8
6.0
100
800
4
11
8
7.8
145
550
5
8
8
9.5
200
400
6
4
6
12.0
300
300
7
4
6
12.0
300
300
Rev. 0 | Page 19 of 40
ADN4604
Table 11 displays the TX Basic Control register. The TX Basic Control register consists of one byte (8 bits) for each of the 16 output
channels. Each TX Basic Control register has the same functionality. The mapping of register address to output channel is shown in the
first column.
Table 11. TX Basic Control Register
Address: Channel
0x18: Broadcast,
0x20: Output 0,
0x21: Output 1,
0x22: Output 2,
0x23: Output 3,
0x24: Output 4,
0x25: Output 5,
0x26: Output 6,
0x27: Output 7,
0x28: Output 8,
0x29: Output 9,
0x2A: Output 10,
0x2B: Output 11,
0x2C: Output 12,
0x2D: Output 13,
0x2E: Output 14,
0x2F: Output 15
Default
0x00
Register Name
TX basic control
Bit
6
Bit Name
TX CTL SELECT
5:4
TX EN[1:0]
3
2:0
Reserved
PE[2:0]
Description
0: PE and output level control is derived from
common lookup table
1: PE and output level control is derived from per port
drive control registers
00: TX disabled, lowest power state
01: TX standby.
10: TX squelched.
11: TX enabled
Reserved. Set to 0.
If TX CTL SELECT = 0, see Table 10
000: Table Entry 0
001: Table Entry 1
010: Table Entry 2
011: Table Entry 3
100: Table Entry 4
101: Table Entry 5
110: Table Entry 6
111: Table Entry 7
If TX CTL SELECT = 1, PE[2:0] are ignored
Table 12 displays the TX lookup table register. The TX lookup table register consists of two bytes (16 bits) for each of the eight possible
table entries selected by the PE[2:0] field in Table 11. The mapping of table entry to register address is shown in the first column. By
default, the TX Lookup Table register contains the preemphasis settings listed in Table 10, however, these values can be changed for a
flexible selection of output levels and preemphasis boosts. Table 13 lists a variety of possible output level and preemphasis boost settings
and the corresponding TX Drive 0 and TX Drive 1 codes.
Table 12. TX Lookup Table Registers
Address: Channel
0x60: Table Entry 0
0x62: Table Entry 1
0x64: Table Entry 2
0x66: Table Entry 3
0x68: Table Entry 4
0x6A: Table Entry 5
0x6C: Table Entry 6
0x6E: Table Entry 7
0x61: Table Entry 0
0x63: Table Entry 1
0x65: Table Entry 2
0x67: Table Entry 3
0x69: Table Entry 4
0x6B: Table Entry 5
0x6D: Table Entry 6
0x6F: Table Entry 7
Default
0xFF
0xFF
0xFF
0xFF
0xDC
0xBB
0x99
0x99
0x00
0x99
0xCC
0xFF
0xFF
0xFF
0xDD
0xDD
Register Name
TX Lookup
Table Drive 0
TX Lookup
Table Drive 1
Bit
7
Bit Name
DRV EN1
Description
0: Driver 1 disabled
1: Driver 1 enabled
6:4
DRV LV1[2:0]
Driver 1 current = decimal(DRV LV1[2:0]) + 1
3
DRV EN0
0: Driver 0 disabled
1: Driver 0 enabled
2:0
DRV LV0[2:0]
Driver 0 current = decimal(DRV LV0[2:0]) + 1
7
DRV END
0: Driver D disabled
1: Driver D enabled
6:4
DRV LVD[2:0]
Driver D Current = decimal(DRV LVD[2:0]) + 1
3
DRV EN2
0: Driver 2 disabled
1: Driver 2 enabled
2:0
DRV LV2[2:0]
Driver 2 current = decimal(DRV LV2[2:0]) + 1
Rev. 0 | Page 20 of 40
ADN4604
Advanced Settings
In addition to the basic settings provided in the TX basic
control registers, advanced settings are available in TX Drive 0
Control and TX Drive 1 Control registers (Address 0x30 to
Address 0x4F). The advanced settings are useful in applications
where each output requires an individually programmed
preemphasis or output level setting beyond what is available
in the lookup table in basic mode. To enable these advanced
settings, set the TX CTL SELECT bit in the TX basic control
register to a logic high. Next, program the TX Drive 0 control
and Drive 1 control registers (Address 0x30 to Address 0x4F) to
the desired output level and boost values. A subset of possible
settings is provided in Table 13. An expanded list of available
settings is shown in Table 19 in the Applications Information
section. These advanced settings can also be used to modify the
TX lookup table settings (Address 0x60 to Address 0x6F). The
advanced settings register map is shown in Table 15.
The preemphasis boost equation follows.
− V SW − DC
)
V SW − DC
Gain[dB] = 20 × log10 (1 + V SW − PE
(1)
VTTO
VH-PE
VH-DC
VOCM
VSW-DC
VSW-PE
Single-Ended Output Levels and
PE Boost
VSW-DC 1 VSW-PE1 PE Boost PE
(mV)
%
(dB)
(mV)
200
200
0.00
0.00
200
300
50.00
3.52
200
350
75.00
4.86
200
400
100.00
6.02
200
450
125.00
7.04
200
500
150.00
7.96
200
600
200.00
9.54
300
300
0.00
0.00
300
400
33.33
2.50
300
450
50.00
3.52
300
500
66.67
4.44
300
550
83.33
5.26
300
600
100.00
6.02
300
700
133.33
7.36
400
400
0.00
0.00
400
500
25.00
1.94
400
550
37.50
2.77
400
600
50.00
3.52
400
650
62.50
4.22
400
700
75.00
4.86
400
800
100.00
6.02
500
500
0.00
0.00
600
600
0.00
0.00
1
VL-PE
Register
Settings
TX
TX
Drive 0
Drive 1
0xBB
0x00
0xBB
0x99
0xBB
0xAA
0xBB
0xBB
0xBB
0xCC
0xBB
0xDD
0xBB
0xFF
0xDD
0x00
0xDD
0x99
0xDD
0xAA
0xDD
0xBB
0xDD
0xCC
0xDD
0xDD
0xDD
0xFF
0xFF
0x00
0xFF
0x99
0xFF
0xAA
0xFF
0xBB
0xFF
0xCC
0xFF
0xDD
0xFF
0xFF
0xFF
0x0B
0xFF
0x0F
Output
Current
ITTO1 (mA)
8
12
14
16
18
20
24
12
16
18
20
22
24
28
16
20
22
24
26
28
32
20
24
Symbol definitions are shown in Table 14.
07934-044
VL-DC
TPE
Table 13. TX Preemphasis and Output Swing Advanced
Settings
Figure 44. Signal Level Definitions
Table 14. Symbol Definitions
Symbol
IDC
IPE
ITTO
TPE
VDPP-DC
Formula
Programmable
Programmable
IDC + IPE
VDPP-PE
25 Ω × ITTO × 2
VSW-DC
VSW-PE
∆VOCM_DC-COUPLED
∆VOCM_AC-COUPLED
VOCM
VH-DC
VL-DC
VH-PE
VL-PE
VTTO
VDPP-DC/2 = VH-DC – VL-DC
VDPP-PE/2 = VH-PE – VL-PE
25 Ω × ITTO/2
50 Ω × ITTO/2
VTTO − ∆VOCM = ( VH-DC + VL-DC )/2
VTTO − ∆VOCM + VDPP-DC/2
VTTO − ∆VOCM − VDPP-DC/2
VTTO − ∆VOCM + VDPP-PE/2
VTTO − ∆VOCM − VDPP-PE/2
Definition
Output current that sets output level
Output current for PE delayed tap
Total transmitter output current
Preemphasis pulse width
Peak-to-peak differential voltage swing of nonpreemphasized waveform
Peak-to-peak differential voltage swing of preemphasized
waveform
DC single-ended voltage swing
Preemphasized single-ended voltage swing
Output common-mode shift, dc-coupled outputs
Output common-mode shift, ac-coupled outputs
Output common-mode voltage
DC single-ended output high voltage
DC single-ended output low voltage
Maximum single-ended output voltage
Minimum single-ended output voltage
Output termination voltage
25 Ω × IDC × 2
Rev. 0 | Page 21 of 40
ADN4604
Table 15 displays the TX advanced control registers. The TX advanced control registers consist of two bytes (16 bits) for each of the 16
output channels. The mapping of register address to output channel is shown in the first column. The TX advanced control registers
provides ultimate flexibility of per port output level and preemphasis boost. Table 13 lists a variety of possible output levels and
preemphasis boost settings and the corresponding TX Drive 0 and TX Drive 1 codes.
Table 15. TX Advanced Control Registers
Address: Channel
0x30: Output 0,
0x32: Output 1,
0x34: Output 2,
0x36: Output 3,
0x38: Output 4,
0x3A: Output 5,
0x3C: Output 6,
0x3E: Output 7,
0x40: Output 8,
0x42: Output 9,
0x44: Output 10,
0x46: Output 11,
0x48: Output 12,
0x4A: Output 13,
0x4C: Output 14,
0x4E: Output 15
0x31: Output 0,
0x33: Output 1,
0x35: Output 2,
0x37: Output 3,
0x39: Output 4,
0x3B: Output 5,
0x3D: Output 6,
0x3F: Output 7,
0x41: Output 8,
0x43: Output 9,
0x45: Output 10,
0x47: Output 11,
0x49: Output 12,
0x4B: Output 13,
0x4D: Output 14,
0x4F: Output 15
Default
0xFF
0x00
Register Name
TX Drive 0
control
TX Drive 1
control
Bit
7
Bit Name
DRV EN1
6:4
3
DRV LV1[2:0]
DRV EN0
2:0
DRV LV0[2:0]
7
DRV END
6:4
3
DRV LVD[2:0]
DRV EN2
2:0
DRV LV2[2:0]
Rev. 0 | Page 22 of 40
Description
0: Driver 1 disabled
1: Driver 1 enabled
Driver 1 current = decimal(DRV LV1[2:0]) + 1
0: Driver 0 disabled
1: Driver 0 enabled
Driver 0 current = decimal(DRV LV0[2:0]) + 1
0: Driver D disabled
1: Driver D enabled
Driver D current = decimal(DRV LVD[2:0]) + 1
0: Driver 2 disabled
1: Driver 2 enabled
Driver 2 current = decimal(DRV LV2[2:0]) + 1
ADN4604
TERMINATION
The termination control is separated by quadrants (North =
Outputs[15:8], South = Outputs[7:0], East = Inputs[15:8], and
West = Inputs[7:0]).
The inputs and outputs include integrated 50 Ω termination
resistors. For applications that require external termination
resistors, the internal resistors can be disabled. For example,
disabling the integrated 50 Ω termination resistors allows
alternative termination values such as 75 Ω as shown in
Figure 45.
Table 16 shows the termination control register. A Logic 0
enables the terminations for the respective quadrant. A Logic 1
disables the terminations for the respective quadrant. The
terminations are enabled by default.
Note that the integrated 50 Ω termination resistors are optimal
for high data rate digital signaling. Disabling the terminations
can reduce the overall performance.
VTTIx
VTTIx
VCC
VTTOx
VTTOx
75Ω
75Ω
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
75Ω
Rx
CML
50Ω
07934-045
ADN4604
75Ω
VEE
Figure 45. 75 Ω to 50 Ω Impedance Translator.
Table 16. Termination Control Register
Address
0xF0
Default
0x00
Register Name
Termination control
Bit
3
Bit Name
TXN_TERM
2
TXS_TERM
1
RXE_TERM
0
RXW_TERM
Rev. 0 | Page 23 of 40
Description
Output[15:8] (North) termination control
0: Terminations enabled
1: Terminations disabled
Output[7:0] (South) termination control
0: Terminations enabled
1: Terminations disabled
Input[15:8] (East) termination control
0: Terminations enabled
1: Terminations disabled
Input[7:0] (West) termination control
0: Terminations enabled
1: Terminations disabled
ADN4604
I2C SERIAL CONTROL INTERFACE
The ADN4604 register set is controlled through a 2-wire I2C
interface. The ADN4604 acts only as an I2C slave device. Therefore,
the I2C bus in the system needs to include an I2C master to
configure the ADN4604 and other I2C devices that may be on
the bus.
1.
2.
The ADN4604 I2C interface can be run in the standard
(100 kHz) and fast (400 kHz) modes. The SDA line only
changes value when the SCL pin is low with two exceptions. To
indicate the beginning or continuation of a transfer, the SDA
pin is driven low while the SCL pin is high; to indicate the end
of a transfer, the SDA line is driven high while the SCL line is
high. Therefore, it is important to control the SCL clock to
toggle only when the SDA line is stable unless indicating a start,
repeated start, or stop condition.
3.
4.
5.
6.
7.
8.
9.
Table 17. I2C Device Address Assignment
ADDR1 Pin
0
0
1
1
I2C Device Address
0x90
0x92
0x94
0x96
ADDR0 Pin
0
1
0
1
Send a start condition (while holding the SCL line high,
pull the SDA line low).
Send the ADN4604 part address (seven bits) whose upper
four bits are the static value b10010 and whose lower three
bits are controlled by the input pins I2C_A[1:0]. This
transfer should be MSB first.
Send the write indicator bit (0).
Wait for the ADN4604 to acknowledge the request.
Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
Wait for the ADN4604 to acknowledge the request.
Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
Wait for the ADN4604 to acknowledge the request.
Do one or more of the following:
a.
b.
c.
RESET
On initial power-up, or at any point in operation, the ADN4604
register set can be restored to the default values by pulling the
RESET pin to low according to the specification in Table 2.
During normal operation, however, the RESET pin must be
pulled up to DVCC. A software reset is available by writing the
value 0x01 to the Reset register at Address 0x00. This register is
write only.
d.
I2C DATA WRITE
Send a stop condition (while holding the SCL line high,
pull the SDA line high) and release control of the bus.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of the write procedure to perform a write.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of this procedure to perform a read from
another address.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 8 of the read procedure (in the I2C Data
Read section) to perform a read from the same
address set in Step 5.
The ADN4604 write process is shown in Figure 46. The SCL
signal is shown along with a general write operation and a
specific example. In the example, data 0x92 is written to
Address 0x6D of an ADN4604 part with a part address of 0x4B.
It is important to note that the SDA line only changes when the
SCL line is low, except for the case of sending a start, stop, or
repeated start condition, Step 1 and Step 9 in this case.
To write data to the ADN4604 register set, a microcontroller,
or any other I2C master, must send the appropriate control
signals to the ADN4604 slave device. The steps to be followed
are listed below; the signals are controlled by the I2C master,
unless otherwise specified. A diagram of the procedure is
shown in Figure 46.
SCL
START
b10010
ADDR
R/W ACK
[1:0]
REGISTER ADDR
ACK
DATA
ACK
STOP
SDA
EXAMPLE
1
2
2
3
4
5
2
Figure 46. I C Write Diagram
Rev. 0 | Page 24 of 40
6
7
8
9a
07934-046
SDA
ADN4604
13. Do one or more of the following:
I2C DATA READ
To read data from the ADN4604 register set, a microcontroller,
or any other I2C master must send the appropriate control
signals to the ADN4604 slave device. The steps are listed below;
the signals are controlled by the I2C master, unless otherwise
specified. A diagram of the procedure is shown in Figure 47.
Send a start condition (while holding the SCL line high,
pull the SDA line low).
2. Send the ADN4604 part address (seven bits) whose upper
five bits are the static value b10010 and whose lower two
bits are controlled by the input pins ADDR1 and ADDR0.
This transfer should be MSB first.
3. Send the write indicator bit (0).
4. Wait for the ADN4604 to acknowledge the request.
5. Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first. The register
address is kept in memory in the ADN4604 until the part
is reset or the register address is written over with the same
procedure (Step 1 to Step 6).
6. Wait for the ADN4604 to acknowledge the request.
7. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low).
8. Send the ADN4604 part address (seven bits) whose upper
five bits are the static value b10010 and whose lower two
bits are controlled by the input pins ADDR1 and ADDR0.
This transfer should be MSB first.
9. Send the read indicator bit (1).
10. Wait for the ADN4604 to acknowledge the request.
11. The ADN4604 then serially transfers the data (eight bits)
held in the register indicated by the address set in Step 5.
12. Acknowledge the data.
a.
Send a stop condition (while holding the SCL line high
pull the SDA line high) and release control of the bus.
b.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of the write procedure (see the I2C Data
Write section) to perform a write.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of this procedure to perform a read from
another address.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 8 of this procedure to perform a read from
the same address.
1.
c.
d.
The ADN4604 read process is shown in Figure 47. The SCL
signal is shown along with a general read operation and a
specific example. In the example, Data 0x49 is read from
Address 0x6D of an ADN4604 part with a part address of 0x4B.
The part address is seven bits wide and is composed of the
ADN4604 static upper five bits (b10010) and the pin programmable lower two bits (ADDR1 and ADDR0). In this example,
the ADDR1 and ADDR0 bits are set to b01. In Figure 47, the
corresponding step number is visible in the circle under the
waveform. The SCL line is driven by the I2C master and never
by the ADN4604 slave. As for the SDA line, the data in the
shaded polygons is driven by the ADN4604, whereas the data in
the nonshaded polygons is driven by the I2C master. The end
phase case shown is that of 13a.
Note that the SDA line only changes when the SCL line is low,
except for the case of sending a start, stop, or repeated start
condition, as in Step 1, Step 7, and Step 13. In Figure 47, A is
the same as ACK in Figure 46. Equally, Sr represents a repeated
start where the SDA line is brought high before SCL is raised.
SDA is then dropped while SCL is still high.
SCL
SDA START
b10010
ADDR R/
[1:0] W
A
REGISTER ADDR
A
Sr
6
7
b10010
ADDR
[1:0]
R/
A
W
DATA
A
STOP
11
12
13a
1
2
2
3
4
5
2
8
Figure 47. I C Read Diagram
Rev. 0 | Page 25 of 40
8
9
10
07934-047
SDA
EXAMPLE
ADN4604
SPI SERIAL CONTROL INTERFACE
The SPI serial interface of the ADN4604 consists of four wires:
CS , SCK, SDI, and SDO. CS is used to select the device when
more than one device is connected to the serial clock and data
lines. CS is also used to distinguish between read and write
commands (see Figure 48). SCK is used to clock data in and out
of the part. Data can either contain eight bits of register address
or data.
three-state mode. Only when the CS goes from high to low does
the part accept any data on the SDI line. To allow continuous
writes, the address pointer register auto-increments by one
without having to load the address pointer register each time.
Subsequent data bytes are written into sequential registers. Note
that not all registers in the 256-byte address space exist and not
all registers are writable. Zeroes should be entered for
nonexisting address fields when implementing a continuous
write operation. Address 0xD0 to Address 0xEF are reserved
and should not be overwritten. A continuous write sequence is
shown in Figure 49.
The SDI line is used to write to the registers, and the SDO line
is used to read data back from the registers. Data on SDI is
clocked on the rising edge of SCK. Data on SDO changes on the
falling edge of SCK. The recommended pull-up resistor value is
between 500 Ω and 1 kΩ. Strong pull-ups are needed when
serial clock speeds that are close to the maximum limit are used
or when the SPI interface lines are experiencing large capacitive
loading. Larger resistor values can be used for pull-up resistors
when the serial clock speed is reduced.
Read Operation
Figure 48 shows the diagram for a write operation to the
ADN4604. To read back from a register, first write to the
address pointer register with the desired starting address. A
read command is distinguished from a write command by the
occurrence of CS going high after the address pointer is written.
Subsequent clock cycles with CS asserted low stream data
starting from the desired register address onto SDO, MSB first.
SDO changes on the falling edge of SCK.
The part operates in slave mode and requires an externally
applied serial clock to the SCLK input. The serial interface is
designed to allow the part to be interfaced to systems that
provide a serial clock that is synchronized to the serial data.
Write Operation
Multiple data reads are possible in SPI interface mode as the
address pointer register is auto-incremented. A continuous read
sequence is shown in Figure 50.
Figure 48 shows the diagram for a write operation to the
ADN4604. Data is clocked into the registers on the rising edge
of SCK. When the CS line is high, the SDI and SDO lines are in
CS
SDI
ADDRESS
DATA
HI-Z
SDO
WRITE OPERATION
CS
SDO
ADDRESS
XXXXXXXX
HI-Z
DATA
READ OPERATION
Figure 48. SPI—Correct Use of CS During SPI Communications
Rev. 0 | Page 26 of 40
07934-048
SDI
ADN4604
CS
SCK
ADDRESS
DATA BYTE 0
DATA BYTE 1
DATA BYTE N
07934-049
SDI
HI-Z
SDO
Figure 49. SPI Continuous Write Sequence
CS
SDI
SDO
ADDRESS
XXXXXXXX
XXXXXXXX
XXXXXXXX
DATA BYTE 1
DATA BYTE N
HI-Z
DATA BYTE 0
Figure 50. SPI Continuous Read Sequence
Rev. 0 | Page 27 of 40
07934-050
SCK
ADN4604
REGISTER MAP
Registers repeated per port or per table entry are grouped together. Register address mapping is shown in the first column.
Table 18. Register Map
Address: Channel
0x00
0x10
0x11
0x12
0x13
Default
N/A
0xFF
0xFF
0x00
0x00
Register Name
RESET
RX EQ Control 0
Bit
0
7
Bit Name
Reset
EQ[7]
RX EQ Control 1
6
5
4
3
2
1
0
15
EQ[6]
EQ[5]
EQ[4]
EQ[3]
EQ[2]
EQ[1]
EQ[0]
EQ[15]
RX Control 0
14
13
12
11
10
9
8
7
EQ[14]
EQ[13]
EQ[12]
EQ[11]
EQ[10]
EQ[9]
EQ[8]
SIGN[7]
RX Control 1
6
5
4
3
2
1
0
15
SIGN[6]
SIGN[5]
SIGN[4]
SIGN[3]
SIGN[2]
SIGN[1]
SIGN[0]
SIGN[15]
14
13
12
11
10
9
8
SIGN[14]
SIGN[13]
SIGN[12]
SIGN[11]
SIGN[10]
SIGN[9]
SIGN[8]
Rev. 0 | Page 28 of 40
Description
Software reset. Write only.
Equalizer boost control for input 7
0: 0 dB
1: 12 dB
Equalizer boost control for Input 6
Equalizer boost control for Input 5
Equalizer boost control for Input 4
Equalizer boost control for Input 3
Equalizer boost control for Input 2
Equalizer boost control for Input 1
Equalizer boost control for Input 0
Equalizer boost control for Input 15
0: 0 dB
1: 12 dB
Equalizer boost control for Input 14
Equalizer boost control for Input 13
Equalizer boost control for Input 12
Equalizer boost control for Input 11
Equalizer boost control for Input 10
Equalizer boost control for Input 9
Equalizer boost control for Input 8
Signal path polarity inversion for Input 7
0: Noninverting
1: Inverting
Signal path polarity inversion for Input 6
Signal path polarity inversion for Input 5
Signal path polarity inversion for Input 4
Signal path polarity inversion for Input 3
Signal path polarity inversion for Input 2
Signal path polarity inversion for Input 1
Signal path polarity inversion for Input 0
Signal path polarity inversion for Input 15
0: Noninverting
1: Inverting
Signal path polarity inversion for Input 14
Signal path polarity inversion for Input 13
Signal path polarity inversion for Input 12
Signal path polarity inversion for Input 11
Signal path polarity inversion for Input 10
Signal path polarity inversion for Input 9
Signal path polarity inversion for Input 8
ADN4604
Address: Channel
0x18: Broadcast,
0x20: Output 0,
0x21: Output 1,
0x22: Output 2,
0x23: Output 3,
0x24: Output 4,
0x25: Output 5,
0x26: Output 6,
0x27: Output 7,
0x28: Output 8,
0x29: Output 9,
0x2A: Output 10,
0x2B: Output 11,
0x2C: Output 12,
0x2D: Output 13,
0x2E: Output 14,
0x2F: Output 15
0x30: Output 0,
0x32: Output 1,
0x34: Output 2,
0x36: Output 3,
0x38: Output 4,
0x3A: Output 5,
0x3C: Output 6,
0x3E: Output 7,
0x40: Output 8,
0x42: Output 9,
0x44: Output 10,
0x46: Output 11,
0x48: Output 12,
0x4A: Output 13,
0x4C: Output 14,
0x4E: Output 15
0x31: Output 0,
0x33: Output 1,
0x35: Output 2,
0x37: Output 3,
0x39: Output 4,
0x3B: Output 5,
0x3D: Output 6,
0x3F: Output 7,
0x41: Output 8,
0x43: Output 9,
0x45: Output 10,
0x47: Output 11,
0x49: Output 12,
0x4B: Output 13,
0x4D: Output 14,
0x4F: Output 15
0x60: Table Entry 0
0x62: Table Entry 1
0x64: Table Entry 2
0x66: Table Entry 3
0x68: Table Entry 4
0x6A: Table Entry 5
0x6C: Table Entry 6
0x6E: Table Entry 7
Default
0x00
0xFF
0x00
0xFF
0xFF
0xFF
0xFF
0xDC
0xBB
0x99
0x99
Register Name
TX basic control
TX Drive 0
control
TX Drive 1
control
TX Lookup
Table 0
Bit
6
Bit Name
TX CTL SELECT
5:4
TX EN[1:0]
3
2:0
Reserved
PE[2:0]
7
DRV EN1
6:4
3
DRV LV1[2:0]
DRV EN0
2:0
DRV LV0[2:0]
7
DRV END
6:4
3
DRV LVD[2:0]
DRV EN2
2:0
DRV LV2[2:0]
7
DRV EN1
0: Driver 1 disabled
1: Driver 1 enabled
6:4
DRV LV1[2:0]
Driver 1 current = decimal(DRV LV1[2:0]) + 1
3
DRV EN0
0: Driver 0 disabled
1: Driver 0 enabled
2:0
DRV LV0[2:0]
Driver 0 current = decimal(DRV LV0[2:0]) + 1
Rev. 0 | Page 29 of 40
Description
0: PE and output level control is derived from common
lookup table
1: PE and output level control is derived from per port
drive control registers
00: TX disabled, lowest power state
01: TX standby
10: TX squelched
11: TX enabled
Reserved. Set to 0.
If TX CTL SELECT = 0, see Table 10
Selected table entry = decimal(PE[2:0])
If TX CTL SELECT = 1, PE[2:0] are ignored
0: Driver 1 disabled
1: Driver 1 enabled
Driver 1 current = decimal(DRV LV1[2:0]) + 1
0: Driver 0 disabled
1: Driver 0 enabled
Driver 0 current = decimal(DRV LV0[2:0]) + 1
0: Driver D disabled
1: Driver D enabled
Driver D current = decimal(DRV LVD[2:0]) + 1
0: Driver 2 disabled
1: Driver 2 enabled
Driver 2 current = decimal(DRV LV2[2:0]) + 1
ADN4604
Address: Channel
0x61: Table Entry 0
0x63: Table Entry 1
0x65: Table Entry 2
0x67: Table Entry 3
0x69: Table Entry 4
0x6B: Table Entry 5
0x6D: Table Entry 6
0x6F: Table Entry 7
0x80
0x81
Default
0x00
0x99
0xCC
0xFF
0xFF
0xFF
0xDD
0xDD
Write only
0x00
0x82
0x90
Register Name
TX Lookup
Table 1
Bit
7
Bit Name
DRV END
Description
0: Driver D disabled
1: Driver D enabled
6:4
DRV LVD[2:0]
Driver D current = decimal(DRV LVD[2:0]) + 1
3
DRV EN2
0: Driver 2 disabled
1: Driver 2 enabled
2:0
DRV LV2[2:0]
Driver 2 current = decimal(DRV LV2[2:0]) + 1
Update
Map table select
0
0
Write only
0xEF
XPT broadcast
XPT Map 0
Control 0
0x91
0xCD
XPT Map 0
Control 1
0x92
0xAB
XPT Map 0
Control 2
0x93
0x89
XPT Map 0
Control 3
0x94
0x67
XPT Map 0
Control 4
0x95
0x45
XPT Map 0
Control 5
0x96
0x23
XPT Map 0
Control 6
0x97
0x01
XPT Map 0
Control 7
0x98
0x10
XPT Map 1
Control 0
0x99
0x32
XPT Map 1
Control 1
0x9A
0x54
XPT Map 1
Control 2
0x9B
0x76
XPT Map 1
Control 3
0x9C
0x98
XPT Map 1
Control 4
0x9D
0xBA
XPT Map 1
Control 5
0x9E
0xDC
XPT Map 1
Control 6
0x9F
0xFE
XPT Map 1
Control 7
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
UPDATE
MAP TABLE
SELECT
BROADCAST[3:0]
OUT1[3:0]
OUT0[3:0]
OUT3[3:0]
OUT2[3:0]
OUT5[3:0]
OUT4[3:0]
OUT7[3:0]
OUT6[3:0]
OUT9[3:0]
OUT8[3:0]
OUT11[3:0]
OUT10[3:0]
OUT13[3:0]
OUT12[3:0]
OUT15[3:0]
OUT14[3:0]
OUT1[3:0]
OUT0[3:0]
OUT3[3:0]
OUT2[3:0]
OUT5[3:0]
OUT4[3:0]
OUT7[3:0]
OUT6[3:0]
OUT9[3:0]
OUT8[3:0]
OUT11[3:0]
OUT10[3:0]
OUT13[3:0]
OUT12[3:0]
OUT15[3:0]
OUT14[3:0]
Updates XPT switch core (active high, write only)
0: Map 0 is selected
1: Map 1 is selected
All outputs connection assignment
Output 1 connection assignment
Output 0 connection assignment
Output 3 connection assignment
Output 2 connection assignment
Output 5 connection assignment
Output 4 connection assignment
Output 7 connection assignment
Output 6 connection assignment
Output 9 connection assignment
Output 8 connection assignment
Output 11 connection assignment
Output 10 connection assignment
Output 13 connection assignment
Output 12 connection assignment
Output 15 connection assignment
Output 14 connection assignment
Output 1 connection assignment
Output 0 connection assignment
Output 3 connection assignment
Output 2 connection assignment
Output 5 connection assignment
Output 4 connection assignment
Output 7 connection assignment
Output 6 connection assignment
Output 9 connection assignment
Output 8 connection assignment
Output 11 connection assignment
Output 10 connection assignment
Output 13 connection assignment
Output 12 connection assignment
Output 15 connection assignment
Output 14 connection assignment
Rev. 0 | Page 30 of 40
ADN4604
Address: Channel
0xB0
Default
0xEF
Register Name
XPT Status 0
0xB1
0xCD
XPT Status 1
0xB2
0xAB
XPT Status 2
0xB3
0x89
XPT Status 3
0xB4
0x67
XPT Status 4
0xB5
0x45
XPT Status 5
0xB6
0x23
XPT Status 6
0xB7
0x01
XPT Status 7
0xF0
0x00
Termination
control
0xFE
0xFF
0x04
Revision
Device ID
Bit
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
3
Bit Name
OUT1[3:0]
OUT0[3:0]
OUT3[3:0]
OUT2[3:0]
OUT5[3:0]
OUT4[3:0]
OUT7[3:0]
OUT6[3:0]
OUT9[3:0]
OUT8[3:0]
OUT11[3:0]
OUT10[3:0]
OUT13[3:0]
OUT12[3:0]
OUT15[3:0]
OUT14[3:0]
TXN_TERM
2
1
0
7:0
7:0
TXS_TERM
RXE_TERM
RXW_TERM
REV[7:0]
ID[7:0]
Rev. 0 | Page 31 of 40
Description
Output 1 connection status
Output 0 connection status
Output 3 connection status
Output 2 connection status
Output 5 connection status
Output 4 connection status
Output 7 connection status
Output 6 connection status
Output 9 connection status
Output 8 connection status
Output 11 connection status
Output 10 connection status
Output 13 connection status
Output 12 connection status
Output 15 connection status
Output 14 connection status
Output[15:8] (North) termination control
0: Terminations enabled
1: Terminations disabled
Output[7:0] (South) termination control
Input[15:8] (East) termination control
Input[7:0] (West) termination control
Read-only
Read-only
ADN4604
APPLICATIONS INFORMATION
Figure 51. Since HDMI, DVI, and DisplayPort are quad lane
protocols, four ADN4604s are used to create a full 16 × 16
matrix switch. Smaller arrays, such as 4 × 4 and 8 × 8, require
one and two ADN4604 devices, respectively. Proper high speed
PCB design techniques should be used to maintain the signal
integrity of the high data rate signals. It is important to minimize
the lane-to-lane skew and crosstalk in these applications.
The ADN4604 is an asynchronous and protocol agnostic digital
switch and, therefore, is applicable to a wide range of applications including network routing and digital video switching.
The ADN4604 supports the data rates and signaling levels of
HDMI®, DVI®, DisplayPort and SD-, HD-, and 3G-SDI digital
video. The ADN4604 can be used to create matrix switches. An
example block diagram of a 16 × 16 matrix switch is shown in
IN 0
OUT 0
IN 1
OUT 1
SOURCE 1
DISPLAY 1
ADN4604
DISPLAY 2
SOURCE 2
IN 15
OUT 15
DISPLAY 3
SOURCE 3
DISPLAY 4
SOURCE 4
IN 0
OUT 0
IN 1
OUT 1
DISPLAY 5
SOURCE 5
ADN4604
SOURCE 6
DISPLAY 6
DISPLAY 7
SOURCE 7
IN 15
OUT 15
DISPLAY 8
SOURCE 8
DISPLAY 9
SOURCE 9
SOURCE 10
IN 0
OUT 0
IN 1
OUT 1
ADN4604
SOURCE 11
DISPLAY 11
DISPLAY 12
SOURCE 12
IN 15
OUT 15
DISPLAY 13
SOURCE 13
SOURCE 14
SOURCE 15
DISPLAY 10
IN 0
OUT 0
IN 1
OUT 1
DISPLAY 14
DISPLAY 15
SOURCE 16
DISPLAY 16
IN 15
OUT 15
Figure 51. ADN4604 Digital Video (DVI, HDMI, DisplayPort) Matrix Switch Block Diagram
Rev. 0 | Page 32 of 40
07934-051
ADN4604
ADN4604
O/E
IN 1
O/E
IN 2
OUT 1
CDR
E/O
OUT 2
CDR
E/O
CDR
E/O
ADN4604
O/E
IN 15
OUT 15
07934-052
16 × 16
CROSSPOINT
SWITCH
Figure 52. ADN4604 Networking Switch Application Block Diagram
8 LANE UPLINK PATH
Z0
Z0
EQ
PE
Z0
Z0
8 LANE DOWNLINK PATH
Z0
ASIC 2
Z0
PE
EQ
Z0
Z0
LOSSY CHANNEL
LOSSY CHANNEL
Figure 53. Multi-Lane Signal Conditioning Application Diagram
Rev. 0 | Page 33 of 40
07934-053
ASIC 1
ADN4604
•
•
SUPPLY SEQUENCING
Ideally, all power supplies should be brought up to the appropriate levels simultaneously (power supply requirements are set by
the supply limits in Table 1 and the absolute maximum ratings
listed in Table 4). If the power supplies to the ADN4604 are
brought up separately, the supply power-up sequence is as follows:
DVCC powered first, followed by VCC, and, last the termination
supplies (VTTIE, VTTIW, VTTON, and VTTOS). The power-down
sequence is reversed with termination supplies being powered
off first. The termination supplies contain ESD protection
diodes to the VCC power domain. To avoid a sustained high
current condition in these devices (ISUSTAINED < 100 mA), the
VTTI and VTTO supplies should be powered on after VCC and
should be powered off before VCC.
•
Alternatively, the thermal resistance can be reduced by
•
•
OUTPUT COMPLIANCE
In low voltage applications, users must pay careful attention
to both the differential and common-mode signal level. The
choice of output voltage swing, preemphasis setting, supply
voltages (VCC and VTTO), and output coupling (ac or dc) affect
peak and settled single-ended voltage swings and the commonmode shift measured across the output termination resistors.
These choices also affect output current and, consequently,
power consumption. Table 19 shows the change in output
common mode (ΔVOCM = VCC − VOCM) with output level and
preemphasis setting. Single-ended output levels are calculated
for VTTO supplies of 3.3 V and 2.5 V to illustrate practical
challenges of reducing the supply voltage. The minimum VL (min
VL) cannot be below the absolute minimum level specified in
Table 1. The combinations of output level, preemphasis, supply
voltage, and output coupling for which the minimum VL
specification is violated are listed as N/A in Table 1.
Peak current from VTTIx or VTTOx to VCC < 200 mA
Sustained current from VTTIx or VTTOx to VCC < 100 mA
POWER DISSIPATION
The power dissipation of the ADN4604 depends on the supply
voltages, I/O coupling type, and device configuration. The
input termination resistors dissipate power depending on the
differential input swing and common-mode voltage. When accoupled, the common-mode voltage is equal to the termination
supply voltage (VTTIE or VTTIW). While the current drawn from
the input termination supply is effectively zero, there is still
power and heat dissipated in the termination resistors as a result
of the differential signal swing. The core supply current and
output termination current are strongly dependent on device
configuration, such as the number of channels enabled, output
level setting, and output preemphasis setting.
Since the absolute minimum output voltage specified in Table 1
is relative to VCC, decreasing VCC is required to maintain the
output levels within the specified limits when lower output
termination voltages are required. VTTO voltages as low as 1.8 V
are allowable for output swings less than or equal to 400 mV
(single-ended). Figure 54 illustrates an application where the
ADN4604 is used as a dc-coupled level translator to interface a
3.3 V CML driver to an ASIC with 1.8 V I/Os. The diode in
series with VCC reduces the voltage at VCC for improved output
compliance.
In high ambient temperature operating conditions, it is important to avoid exceeding the maximum junction temperature of
the device. Limiting the total power dissipation can be achieved
by the following:
Reducing the output swing
3.3V
3.3V
VTTIx
1.8V
VCC
VTTOx
1.8V
ASIC
3.3V
Z0
CML
Z0
Rx
CML
Z0
ADN4604
Z0
VEE
Figure 54. DC-Coupled Level Translator Application Circuit
Rev. 0 | Page 34 of 40
07934-054
•
Adding an external heat-sink
Increasing the airflow
Refer to the Printed Circuit Board (PCB) Layout Guidelines
section for recommendations for proper thermal stencil layout
and fabrication.
If the system power supplies have a high impedance in the
powered off state, then supply sequencing is not required
provided the following limits are observed:
•
•
Reducing the preemphasis level
Decreasing the supply voltages within the allowable ranges
defined in Table 1
Disabling unused channels
ADN4604
Table 19. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting
Single-Ended Output Levels and
PE Boost
VSW-DC 1
(mV)
100
100
100
100
100
100
100
100
100
200
200
200
200
200
200
200
200
200
300
300
300
300
300
300
300
300
300
400
400
400
400
400
400
400
400
400
450
450
500
500
550
550
600
1
2
VSW-PE1
(mV)
100
150
200
250
300
350
400
450
500
200
250
300
350
400
450
500
550
600
300
350
400
450
500
550
600
650
700
400
450
500
550
600
650
700
750
800
450
650
500
700
550
650
600
PE Boost
%
0.00
50.00
100.00
150.00
200.00
250.00
300.00
350.00
400.00
0.00
25.00
50.00
75.00
100.00
125.00
150.00
175.00
200.00
0.00
16.67
33.33
50.00
66.67
83.33
100.00
116.67
133.33
0.00
12.50
25.00
37.50
50.00
62.50
75.00
87.50
100.00
0.00
44.44
0.00
40.00
0.00
18.18
0.00
PE
(dB)
0.00
3.52
6.02
7.96
9.54
10.88
12.04
13.06
13.98
0.00
1.94
3.52
4.86
6.02
7.04
7.96
8.79
9.54
0.00
1.34
2.50
3.52
4.44
5.26
6.02
6.72
7.36
0.00
1.02
1.94
2.77
3.52
4.22
4.86
5.46
6.02
0.00
3.19
0.00
2.92
0.00
1.45
0.00
Register
Settings
TX
Drive 0
0x99
0x99
0x99
0x99
0x99
0x99
0x99
0x99
0x99
0xBB
0xBB
0xBB
0xBB
0xBB
0xBB
0xBB
0xBB
0xBB
0xDD
0xDD
0xDD
0xDD
0xDD
0xDD
0xDD
0xDD
0xDD
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
TX
Drive 1
0x00
0x88
0x99
0xAA
0xBB
0xCC
0xDD
0xEE
0xFF
0x00
0x88
0x99
0xAA
0xBB
0xCC
0xDD
0xEE
0xFF
0x00
0x88
0x99
0xAA
0xBB
0xCC
0xDD
0xEE
0xFF
0x00
0x88
0x99
0xAA
0xBB
0xCC
0xDD
0xEE
0xFF
0x09
0xBD
0x0B
0xBF
0x0D
0x9F
0x0F
AC-Coupled Outputs
VCC = 2.7 V
VCC = VTTO = 3.3 V VTTO = 2.5 V
Output
Current
ITTO1
(mA)
4
6
8
10
12
14
16
18
20
8
10
12
14
16
18
20
22
24
12
14
16
18
20
22
24
26
28
16
18
20
22
24
26
28
30
32
18
26
20
28
22
26
24
∆VOCM1
(mV)
100
150
200
250
300
350
400
450
500
200
250
300
350
400
450
500
550
600
300
350
400
450
500
550
600
650
700
400
450
500
550
600
650
700
750
800
450
650
500
700
550
650
600
VH-PE1
(V)
3.25
3.225
3.2
3.175
3.15
3.125
3.1
3.075
3.05
3.2
3.175
3.15
3.125
3.1
3.075
3.05
3.025
3
3.15
3.125
3.1
3.075
3.05
3.025
3
2.975
2.95
3.1
3.075
3.05
3.025
3
2.975
2.95
2.925
2.9
3.075
2.975
3.05
2.95
3.025
2.975
3
Symbol definitions are shown in Table 14.
This setting is not allowed when ac-coupled with VCC = 2.7 V and VTTON = 2.5 V or VTTOS = 2.5 V.
Rev. 0 | Page 35 of 40
VL-PE 1
(V)
3.15
3.075
3
2.925
2.85
2.775
2.7
2.625
2.55
3
2.925
2.85
2.775
2.7
2.625
2.55
2.475
2.4
2.85
2.775
2.7
2.625
2.55
2.475
2.4
2.325
2.25
2.7
2.625
2.55
2.475
2.4
2.325
2.25
2.175
2.1
2.625
2.325
2.55
2.25
2.475
2.325
2.4
VH-PE1
(V)
2.45
2.425
2.4
2.375
2.35
2.325
2.3
2.275
2.25
2.4
2.375
2.35
2.325
2.3
2.275
2.25
2.225
2.2
2.35
2.325
2.3
2.275
2.25
2.225
2.2
2.175
2.15
2.3
2.275
2.25
2.225
2.2
2.175
2.15
N/A 2
N/A2
2.275
2.175
N/A2
2.15
2.225
2.175
N/A2
VL-PE1
(V)
2.35
2.275
2.2
2.125
2.05
1.975
1.9
1.825
1.75
2.2
2.125
2.05
1.975
1.9
1.825
1.75
1.675
1.6
2.05
1.975
1.9
1.825
1.75
1.675
1.6
1.525
1.45
1.9
1.825
1.75
1.675
1.6
1.525
1.45
N/A2
N/A2
1.825
1.525
N/A2
1.45
1.675
1.525
N/A2
DC-Coupled Outputs
VCC = 2.7 V
VCC = VTTO = 3.3 V
VTTO = 2.5 V
∆VOCM1
(mV)
50
75
100
125
150
175
200
225
250
100
125
150
175
200
225
250
275
300
150
175
200
225
250
275
300
325
350
200
225
250
275
300
325
350
375
400
225
325
250
350
275
325
300
VH-DC1
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
VL-DC1
(V)
3.2
3.15
3.1
3.05
3
2.95
2.9
2.85
2.8
3.1
3.05
3
2.95
2.9
2.85
2.8
2.75
2.7
3
2.95
2.9
2.85
2.8
2.75
2.7
2.65
2.6
2.9
2.85
2.8
2.75
2.7
2.65
2.6
2.55
2.5
2.85
2.65
2.8
2.6
2.75
2.65
2.7
VH-PE1
(V)
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
VL-PE1
(V)
2.4
2.35
2.3
2.25
2.2
2.15
2.1
2.05
2
2.3
2.25
2.2
2.15
2.1
2.05
2
1.95
1.9
2.2
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
2.1
2.05
2
1.95
1.9
1.85
1.8
1.75
1.7
2.05
1.85
2
1.8
1.95
1.85
1.9
ADN4604
Stencil Design for the Thermal Paddle
PRINTED CIRCUIT BOARD (PCB) LAYOUT
GUIDELINES
The high speed differential inputs and outputs should be routed
with 100 Ω controlled impedance differential transmission
lines. The transmission lines, either microstrip or stripline,
should be referenced to a solid low impedance reference plane.
An example of a PCB cross-section is shown in Figure 55. The
trace width (W), differential spacing (S), height above reference
plane (H), and dielectric constant of the PCB material determine
the characteristic impedance. Adjacent channels should be kept
apart by a distance greater than 3 W to minimize crosstalk.
W
S
W
SOLDERMASK
SIGNAL (MICROSTRIP)
H
PCB DIELECTRIC
REFERENCE PLANE
PCB DIELECTRIC
SIGNAL (STRIPLINE)
PCB DIELECTRIC
REFERENCE PLANE
W
S
07934-055
PCB DIELECTRIC
W
To effectively remove heat from the package and to enhance
electrical performance, the thermal paddle must be soldered
(bonded) to the PCB thermal paddle, preferably with minimum
voids. However, eliminating voids may not be possible because
of the presence of thermal vias and the large size of the thermal
paddle for larger size packages. Also, outgassing during the
reflow process may cause defects (splatter, solder balling) if the
solder paste coverage is too big.
It is recommended that smaller multiple openings in the stencil
be used instead of one big opening for printing solder paste on
the thermal paddle region. This typically results in 50% to 80%
solder paste coverage. Figure 57 shows how to achieve these
levels of coverage.
Voids within solder joints under the exposed paddle can have
an adverse affect on high speed and RF applications, as well as
on thermal performance. Because the package incorporates a
large center paddle, controlling solder voiding within this
region can be difficult. Voids within this ground plane can
increase the current path of the circuit. The maximum size for
a void should be less than via pitch within the plane. This
assures that any one via is not rendered ineffectual when any
void increases the current path beyond the distance to the next
available via.
Figure 55. Example of a PCB Cross-Section
Thermal Paddle Design
The TQFP is designed with an exposed thermal paddle to
conduct heat away from the package and into the PCB. By
incorporating thermal vias into the PCB thermal paddle,
heat is dissipated more effectively into the inner metal layers
of the PCB. To ensure device performance at elevated
temperatures, it is important to have a sufficient number of
thermal vias incorporated into the design. An insufficient
number of thermal vias results in a θJA value larger than
specified in Table 1.
1.35mm × 1.35mm SQUARES
AT 1.65mm PITCH
07934-057
COVERAGE: 68%
Figure 57. Typical Thermal Paddle Stencil Design
It is recommended that a via array of 4 × 4 or 5 × 5 with a
diameter of 0.3 mm to 0.33 mm be used to set a pitch between
1.0 mm and 1.2 mm. A representative of these arrays is shown in
Figure 56.
THERMAL
PADDLE
07934-056
THERMAL
VIA
Figure 56. PCB Thermal Paddle and Via
Rev. 0 | Page 36 of 40
ADN4604
SOLDER
MASK
(A)
COPPER
PLATING
VIA
(B)
(C)
(D)
07934-058
Large voids in the thermal paddle area should be avoided. To
control voids in the thermal paddle area, solder masking may be
required for thermal vias to prevent solder wicking inside the
via during reflow, thus displacing the solder away from the
interface between the package thermal paddle and thermal
paddle land on the PCB. There are several methods employed
for this purpose, such as via tenting (top or bottom side), using
dry film solder mask; via plugging with liquid photo-imagible
(LPI) solder mask from the bottom side; or via encroaching.
These options are depicted in Figure 58. In case of via tenting,
the solder mask diameter should be 100 microns larger than the
via diameter.
Figure 58. Solder Mask Options for Thermal Vias: (A) Via Tenting from the
Top; (B) Via Tenting from the Bottom; (C) Via Plugging, Bottom; and (D) Via
Encroaching, Bottom
Rev. 0 | Page 37 of 40
ADN4604
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 BSC SQ
1.20
MAX
14.00 BSC SQ
100
1
SEATING
PLANE
76
76
75
100
1
75
PIN 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
51
50
25
50
1.05
1.00
0.95
7°
3.5°
0°
0.50 BSC
0.27
0.22
0.17
0.15
0.05
26
6.50
NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
021809-A
25
26
0.20
0.09
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
Figure 59. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN4604ASVZ1
ADN4604ASVZ-RL1
Temperature Range
−40°C to +85°C
−40°C to +85°C
ADN4604-EVALZ1
1
Package Description
100-Lead Thin Quad Flat Package [TQFP_EP]
100-Lead Thin Quad Flat Package [TQFP_EP],
13” Tape & Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 38 of 40
Package Option
SV-100-1
SV-100-1
Ordering Quantity
1000
ADN4604
NOTES
Rev. 0 | Page 39 of 40
ADN4604
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07934-0-10/09(0)
Rev. 0 | Page 40 of 40

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