Power Management Unit for Imaging Modules ADP5020 FEATURES Input voltage range: 2.4 V to 5.5 V Low standby current: 1 μA Switching frequency: 3 MHz I2C interface Synchronous Buck 1 regulator: 600 mA Synchronous Buck 2 regulator: 250 mA Low dropout regulator (LDO): 150 mA Internal compensation Internal soft start Thermal shutdown 20-lead 4 mm × 4 mm LFCSP TYPICAL APPLICATIONS CIRCUIT VIN 2.4V TO 5.5V Digital cameras, handsets Mobile TVs 2.2µH VDD2 VOUT1 2.5V TO 3.7V VOUT1 VOUT1 10µF VDD3 PGND1 ADP5020 2.2µH VDDA VDD_IO SW2 1µF VOUT2 1.1V TO 1.8V 4.7µF VOUT2 1.7V TO 3.6V VDD_IO 10kΩ APPLICATIONS SW1 VDD1 10µF 10kΩ PGND2 0.1µF VOUT3 1.8V TO 3.3V VOUT3 1µF SDA SCL SYNC XSHTDN EN/GPIO AGND 07774-001 DGND EXT. FREQ 9.6/19.2MHz Figure 1. GENERAL DESCRIPTION The ADP5020 provides a highly integrated power solution that includes all of the power circuits necessary for a digital imaging module. It comprises two step-down dc-to-dc converters, one LDO, and a power sequence controller. All dc-to-dc converters integrate power pMOSFETs and nMOSFETs, making the system simpler and more compact and reducing the cost. The ADP5020 has digitally programmed output voltages and buck converters that can source up to 600 mA. A fixed frequency operation of 3 MHz enables the use of tiny inductors and capacitors. The buck converters use a voltage mode, constant-frequency PWM control scheme, and the synchronous rectification is implemented to reduce the power loss. The Buck 1 regulator operates at up to 93% efficiency. The ADP5020 provides high performance, reduces component count and size, and is lower in cost when compared to conventional designs. The ADP5020 runs on input voltage from 2.4 V to 5.5 V and supports one-cell lithium-ion (Li+) batteries. The high performance LDO maximizes noise suppression. The ADP5020 can be activated via an I2C® interface or through a dedicated enable input. During logic-controlled shutdown, the input is disconnected from the output source, and the part draws 1 μA typical from the input source. Other key features include undervoltage lockout to prevent deep-battery discharge and soft start to prevent input current overshoot at startup. The ADP5020 is available in a 20-lead LFCSP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADP5020 TABLE OF CONTENTS Features .............................................................................................. 1 Undervoltage Lockout ............................................................... 13 Applications ....................................................................................... 1 Thermal Shutdown .................................................................... 13 Typical Applications Circuit............................................................ 1 Control Registers ............................................................................ 14 General Description ......................................................................... 1 Device Address ........................................................................... 14 Revision History ............................................................................... 2 Register Map ............................................................................... 14 Functional Block Diagram .............................................................. 3 Register Descriptions ................................................................. 14 Specifications..................................................................................... 4 Power-Up/Power-Down Sequence............................................... 17 Switching Specifications .............................................................. 5 Sequencer .................................................................................... 17 DC-to-DC Conversion Specifications, Buck 1 Regulator ....... 5 Default Power-On Sequence with EN Pin .............................. 17 DC-to-DC Conversion Specifications, Buck 2 Regulator ....... 6 Power-On Sequence Using the I2C Interface.............................. 19 VOUT3 Specifications, Low Dropout (LDO) Regulator ........ 6 Power-Up/Power-Down State Flow ......................................... 20 I C Timing Specifications ............................................................ 7 Applications Information .............................................................. 21 Absolute Maximum Ratings............................................................ 8 Power Good Status ..................................................................... 21 Thermal Resistance ...................................................................... 8 XSHTDN Logic .......................................................................... 21 ESD Caution .................................................................................. 8 Components Selection ............................................................... 21 Pin Configuration and Function Descriptions ............................. 9 LDO Input Filter......................................................................... 22 Typical Performance Characteristics ........................................... 10 Layout Recommendations............................................................. 23 Theory of Operation ...................................................................... 13 Applications Schematic ............................................................. 23 Circuit Operation ....................................................................... 13 PCB Board Layout Recommendations .................................... 24 Internal Compensation .............................................................. 13 External Component List .......................................................... 24 Current Limiting and Short-Circuit Protection ..................... 13 Outline Dimensions ....................................................................... 25 Synchronization .......................................................................... 13 Ordering Guide .......................................................................... 25 2 I C Interface ................................................................................ 13 2 REVISION HISTORY 4/09—Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADP5020 FUNCTIONAL BLOCK DIAGRAM VDD3 VDD2 VDD1 VDDA SW1 XSHTDN RESET UVLO BUCK 1 VOUT1 VOUT1 PGND1 SCL I2C SDA SW2 BUCK 2 VDD_IO CONTROL LOGIC VOUT2 EN/GPIO PGND2 SYNC THERMAL SHUTDOWN LDO VOUT3 BUCK1_EN SEQUENCER HOUSEKEEPING BUCK2_EN LDO_EN DGND AGND Figure 2. Rev. 0 | Page 3 of 28 07774-002 VDDA ADP5020 SPECIFICATIONS TJ = −40°C to +125°C, VDDx = 3.6 V, VDD_IO = 1.8 V, unless otherwise noted. Table 1. Parameter OPERATING RANGE VDDx Operating Voltage Range Logic I/O Operating Voltage Range 1 EN, SDA, SCL CHARACTERISTICS Low Level Input Voltage High Level Input Voltage INPUT LOGIC CURRENT XSHTDN, EN/GPIO Low Level Output Voltage High Level Output Voltage OUTPUT LOGIC LEAKAGE CURRENT UNDERVOLTAGE LOCKOUT THRESHOLD Falling Rising POWER-ON RESET THRESHOLD Falling Rising UVLO GLITCH DEBOUNCE TIME SHUTDOWN OUTPUT DURATION 2 POWER GOOD (POK) ACTIVATION DELAY TIME 3 EN to First Regulator First to Second Regulator Second to Third Regulator NO LOAD CURRENT CHARACTERISTICS Standby Current Lockout Current Operating Quiescent Current, Switching 4 THERMAL CHARACTERISTICS Thermal Shutdown, TJ Rising Thermal Shutdown Hysteresis HOUSEKEEPING BLOCK Power Good Threshold Symbol Conditions Min VDD VDD_IO 2.4 1.7 VIL VIH ILK Internal pull-down, 1 MΩ 0.7 × VDD_IO −1 VOL VOH ILK IRST = +3 mA IRST = −3 mA 0.8 × VDD_IO VUVLOF VUVLOR Referenced to VDDA Referenced to VDDA 1.8 VPORF VPORR Referenced to VDDA Referenced to VDDA VDD > POR levels XSHTDN line driven low 1.0 tXSHTDN Max Unit 5.5 3.6 V V 0.3 × VDD_IO V V μA +6 0.2 × VDD_IO tREG1 tREG2 tREG3 IQ(STNBY) ILOCK IQ Typ 2.0 2.2 1.4 1.6 50 1 1 V V μA 2.4 V V 1.7 5 5 5 EN = 0 EN = 0, VDDA < VUVLOF ILOAD = 0 mA 1 1 10 TSD ms ms ms 5 1 15 150 30 VPG 70 1 80 3 Rev. 0 | Page 4 of 28 μA μA mA °C °C 90 The VDD_IO voltage must be less than or equal to the level on the VDDx supply lines. Shutdown output duration is automatic when using the EN pin. To get this delay when using I2C, FORCE_XS must be set to 1. Activation delays apply only when the device is activated through the EN pin or the EN_ALL bit (Address 0x03[4]); the sequencer controls the turning on of the regulators. 4 The quiescent current is calculated as though all regulators are powered up. 2 V V μs ms % ADP5020 SWITCHING SPECIFICATIONS Table 2. Parameter SWITCHING FREQUENCY CH1 CH2 SYNC CLOCK DIVIDER RATIO Symbol Conditions Min Typ Max Unit fSW1 fSW2 Sync disabled Sync disabled 2.5 2.5 3 3 3.6 3.6 MHz MHz RATIODIV RATIODIV SYNC_9P6 = 1 SYNC_19P2 = 1 60 MHz MHz % 3 6 SYNC CHARACTERISTICS Frequency Range Frequency Duty Cycle Signal DC Coupling Level Low Level Input Voltage High Level Input Voltage DC Coupling AC Coupling Level AC Coupling Capacitor Input Current fSYNC1 fSYNC2 fSYNCDUTY 40 VIL VIH VSYNC VCAC-PP Sine wave, peak-to-peak 0.7 × VDD_IO 0 0.5 ISYNC SYNC_9P6 = 1, or SYNC_19P2 = 1 9.6 19.2 50 0.3 × VDD_IO 1.0 10 50 VDD_IO VDD_IO V V V V nF μA Max Unit 3.7 +1 +4 V % % DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR Table 3. Parameter OUTPUT VOLTAGE Range 1 Initial Accuracy Total Accuracy VOUT1 REGULATION Load Regulation Line Regulation CURRENT Maximum Output Current Quiescent Current POWER Low-Side Power nMOSFET High-Side Power pMOSFET SWITCH CURRENT LIMIT MINIMUM ON TIME MAXIMUM DUTY CYCLE SOFT START TIME COUT DISCHARGE SWITCH ON RESISTANCE Symbol Conditions Min VOUT1 3-bit range TA = 25°C, VDD1 2 , VOUT1 = 3.3 V, ILOAD = 20 mA VDD1 3 , ILOAD = 50 mA to 600 mA 2.5 −1 −5 ILOAD = 20 mA to 600 mA VDDA = 1.8 V, VDD12, 3 IBK1MAX IQBK1 VDD13, VOUT1 = 2.5 V to 3.7 V ILOAD = 0 mA RDSON1 RDSON1 ICL1 tMIN1 DMAX1 tSS1 RDIS1 ID = 400 mA ID = 400 mA 0.2 0.15 4 0.8 0.7 1 See Table 13 (the BUCK1_VSEL register, Address 0x01) for details. VDD1 = 3.1 V to 5.5 V, ILOAD is less than 200 mA. For tight regulation, the supply voltage must be 0.6 V higher than the output voltage. 3 VDD1 = 3.7 V to 5.5 V, ILOAD is more than 200 mA. For tight regulation, the supply voltage must be 1.2 V higher than the output voltage. 2 Rev. 0 | Page 5 of 28 Typ 175 250 1.2 55 88 1.4 1 % % 600 6 mA mA 250 400 1.6 mΩ mΩ A ns % ms kΩ 95 1.3 ADP5020 DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR Table 4. Parameter OUTPUT VOLTAGE Adjustable Range 1 Initial Accuracy Total Accuracy Load Regulation Line Regulation CURRENT Maximum Output Current Quiescent Current POWER Low-Side Power nMOSFET High-Side Power pMOSFET SWITCH CURRENT LIMIT MINIMUM ON TIME MAXIMUM DUTY CYCLE SOFT START TIME COUT DISCHARGE SWITCH ON RESISTANCE 1 Symbol Conditions Min VOUT2 4-bit range TA = 25°C, VDD2 = 3.6 V, VOUT2 = 1.2 V, ILOAD = 20 mA VDD2 = 2.5 V to 5 V, ILOAD = 10 mA to 250 mA ILOAD = 10 mA to 250 mA VDDA = 1.8 V, VDD2 = 2.5 V to 5 V 1.1 −1 −5 IBK2MAX IQBK2 RDSON2 RDSON2 ICL2 tMIN2 DMAX2 tSS2 RDIS2 Typ Max Unit 1.8 +1 +4 V % % % % 250 6.5 mA mA mΩ mΩ mA ns % μs kΩ 0.2 0.15 ILOAD = 0 mA 4 ID = 200 mA ID = 200 mA 330 450 850 0.7 240 300 630 55 87.5 900 1 Typ Max Unit 0.45 0.15 3.3 +1.5 +4 0.75 0.30 V % % % % 200 70 45 400 150 100 85 600 mA mV μA mA 0.7 47 44 70 1 1.3 dB dB μs kΩ 360 90 1.3 See Table 14 (the BUCK2_LDO_VSEL register, Address 0x02) for details. VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR Table 5. Parameter OUTPUT VOLTAGE Adjustable Range 1 Initial Accuracy Total Accuracy Load Regulation Line Regulation CURRENT Maximum Output Current Dropout Voltage Quiescent Current Short-Circuit Current Limit Power Supply Rejection Ratio Symbol Conditions Min VOUT3 100 mV step, 4-bit range TA = 25°C, VDD3 = 3.6 V, VOUT3 = 1.8 V, ILOAD = 10 mA VDD3 = 2.5 V to 5 V, ILOAD = 0 mA to 150 mA ILOAD = 10 mA to 100 mA ILOAD = 100 mA 2 1.8 −1.5 −5 ILDOMAX VLDODROP IQ At 100 mA, VOUT3 = 3.3 V ILOAD = 0 mA PSRR f = 1 kHz, VDD3 = 5 V, VOUT3 = 3.3 V, ILOAD = 50 mA f = 10 kHz, VDD3 = 5 V, VOUT3 = 3.3 V, ILOAD = 50 mA SOFT START TIME COUT DISCHARGE SWITCH ON RESISTANCE 1 2 tSS2 RDIS8 See Table 14 (the BUCK_LDO_VSEL register, Address 0x02) for details. VDD3 > VOUT3 + LDODROP. Rev. 0 | Page 6 of 28 ADP5020 I2C TIMING SPECIFICATIONS Table 6. Parameter fSCL tHIGH tLOW tSU,DAT tHD,DAT 1 tSU,STA tHD,STA tBUF tSU,STO tRISE tFALL tSP CB 2 1 2 Min Max 400 0.6 1.3 100 0 0.6 0.6 1.3 0.6 20 + 0.1CB 20 + 0.1CB 0 0.9 300 300 50 400 Unit kHz μs μs ns μs μs μs μs μs ns ns ns pF Description SCL clock frequency SCL high time SCL low time Data setup time Data hold time Setup time for repeated start Hold time for start/repeated start Bus free time between a stop condition and a start condition Setup time for stop condition Rise time of SCL/SDA Fall time of SCL/SDA Pulse width of suppressed spike Capacitive load for each bus line A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the SCL falling edge. CB is the total capacitance of one bus line in picofarads (pF). Timing Diagram SDA tBUF tLOW tRISE tFALL tHD,STA tFALL tSU,DAT tSP tRISE SCL S tHD,DAT tHIGH tSU,STA Sr P S 07774-003 S = START CONDITION Sr = START REPEATED CONDITION P = STOP CONDITION tSU,STO Figure 3. I2C Interface Timing Diagram Rev. 0 | Page 7 of 28 ADP5020 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter VDD1, VDD2, VDD3 SW1, SW2 VOUT1, VOUT2, VOUT3 VDD_IO EN, SCL, SDA, SYNC, XSHTDN Operating Temperature Range Ambient Junction Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) VESD Machine Model Range Human Body Model Range Charged Device Model θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V −0.3V to +3.6 V −0.3 V to VDD_IO + 0.3 V Table 8. Thermal Resistance Package Type 20-Lead LFCSP (CP-20-4) θJA 47.4 θJC 4.3 Unit °C/W Thermal Data −40°C to +85°C −40°C to +125°C −65°C to +150°C 260°C 260°C 215°C 220°C Junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and environmental conditions. The specified value of θJA is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board, as per JEDEC standards. For more information, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). −200 V to +200 V −2000 V to +2000 V ±750 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION The ADP5020 can be damaged when the junction temperature (TJ) limits are exceeded. Monitoring the ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications having moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The TJ of the device is dependent on the ambient temperature (TA), the power dissipation (PD) of the device, and the junction-to-ambient thermal resistance of the package (θJA). Maximum TJ is calculated from TA and PD using the following formula: TJ = TA + (PD × θJA) Rev. 0 | Page 8 of 28 ADP5020 VOUT1 14 VDD3 13 VOUT3 12 EN/GPIO 11 1 PGND2 ADP5020 2 VOUT2 BOTTOM VIEW (Not to Scale) 3 VDDA EXPOSED PAD VOUT2 2 4 AGND VDDA 3 5 SYNC AGND 4 17 SW1 16 PGND1 18 VDD1 19 VDD2 PIN 1 INDICATOR PGND2 1 ADP5020 TOP VIEW (Not to Scale) 13 VDD3 12 VOUT3 9 VDD_IO XSHTDN 10 8 SCL 6 6 DGND SDA 7 7 SDA Figure 4. Pin Configuration (Bottom View) 14 VOUT1 11 EN/GPIO DGND 8 SCL NOTES 1. EXPOSED PAD SHOULD BE CONNECTED TO PGND1 AND PGND2. 07774-004 9 VDD_IO XSHTDN 10 SYNC 5 15 VOUT1 07774-005 VOUT1 15 20 SW2 19 VDD2 20 SW2 18 VDD1 17 SW1 16 PGND1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration (Top View) Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic PGND2 VOUT2 VDDA AGND SYNC 6 7 8 9 10 11 DGND SDA SCL VDD_IO XSHTDN EN/GPIO 12 13 14, 15 16 17 18 19 20 EPAD VOUT3 VDD3 VOUT1 PGND1 SW1 VDD1 VDD2 SW2 Exposed paddle Description Power Ground Buck 2. Feedback Buck 2. Supply Voltage Internal Analog Circuit. Analog Ground. Frequency Synchronization. Connect to an external 19.2 MHz or 9.6 MHz clock signal to synchronize the internal oscillator. Digital Ground. I2C Data. I2C Clock. Supply Voltage for Internal Logic Inputs/Outputs. Shutdown Output, Active Low. After power-on reset, this pin is defined as enable (EN). To enable active high, the I2C command can program this pin to be an output (GPIO). A weak pull-down resistor is enabled when the pin operates as EN. Regulated Output Voltage from LDO. Supply Voltage LDO. Feedback/Driver Buck 1 Output. Power Ground Buck 1. Switch Pin Buck 1. Supply Voltage Buck 1. Supply Voltage Buck 2. Switch Pin Buck 2. Exposed pad should be connected to PGND1 and PGND2. Rev. 0 | Page 9 of 28 ADP5020 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 = 4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted. 3.5 95 3.3V 3.0V 3.0 90 2.0V 2.0 1.8V 1.5 VOUT1 (2.5V) VOUT2 (2.8V) VOUT3 (2.9V) VOUT4 (3.0V) VOUT5 (3.2V) VOUT6 (3.3V) VOUT7 (3.7V) 80 75 0 30 60 90 LOAD CURRENT (mA) 120 150 70 07774-006 0 Figure 6. LDO Load Regulation 100 200 300 400 LOAD CURRENT (mA) 500 Figure 9. Buck 1, Efficiency vs. Load Current LDO OUTPUT = 20mV/DIV ILOAD = 100mA/DIV TIME = 100µs/DIV BUCK 1 OUTPUT = 100mV/DIV ILOAD = 100mA/DIV TIME = 100µs/DIV BUCK 1 ILOAD ILOAD 07774-010 07774-007 LDO Figure 7. LDO Load Transient Figure 10. Buck 1 Load Transient Response 1.9 VOUT7 (3.7V) 3.4 VOUT6 (3.3V) VOUT5 (3.2V) VOUT4 (3.0V) 2.8 VOUT3 (2.9V) VOUT2 (2.8V) 2.6 VOUT1 (2.5V) 2.4 VOUT7 (1.7V) 1.7 3.2 3.0 VOUT8 (1.8V) 1.8 OUTPUT VOLTAGE (V) 3.6 VOUT6 (1.6V) 1.6 VOUT5 (1.5V) 1.5 VOUT4 (1.4V) 1.4 VOUT3 (1.3V) 1.3 VOUT2 (1.2V) 1.2 2.2 VOUT1 (1.1V) 1.1 0 100 200 300 400 LOAD CURRENT (mA) 500 600 0 07774-008 OUTPUT VOLTAGE (V) 3.8 0 600 Figure 8. Buck 1 Load Regulation 0 50 100 150 200 LOAD CURRENT (mA) Figure 11. Buck 2 Load Regulation Rev. 0 | Page 10 of 28 250 300 07774-011 1.0 85 07774-009 2.5V 2.5 EFFICIENCY (%) LDO VOLTAGE (V) 2.8V ADP5020 VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 = 4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted. 0.90 BUCK 1 OUTPUT = 2V/DIV BUCK 2 OUTPUT = 1V/DIV 0.85 TIME = 5ms/DIV 0.75 0.70 EFF1 (1.1V) EFF2 (1.2V) EFF3 (1.3V) EFF4 (1.4V) EFF5 (1.5V) EFF6 (1.6V) EFF7 (1.7V) EFF8 (1.8V) 0.60 0.55 0.50 0 50 100 150 200 LOAD CURRENT (mA) 250 BUCK 2 ENABLE 300 07774-015 0.65 07774-012 EFFICIENCY (%) 0.80 Figure 15. Startup Sequence of the Three Regulators, Set by Default Figure 12. Buck 2 Efficiency vs. Load Current BUCK 2 OUTPUT = 1V/DIV SW2 OUTPUT = 2V/DIV TIME = 500µs/DIV BUCK 2 OUTPUT = 50mV/DIV ILOAD = 100mA/DIV TIME = 100µs/DIV BUCK 2 ILOAD SW2 07774-016 07774-013 BUCK 2 Figure 13. Buck 2 Load Transient Response Figure 16. Buck 2 Enable Startup 1.2 BUCK 1 OUTPUT = 1V/DIV SW1 OUTPUT = 2V/DIV TIME = 500µs/DIV 0.8 BUCK 1 0.6 ISHTDN (µA) @ –40°C ISHTDN (µA) @ +25°C ISHTDN (µA) @ +125°C 0.4 0.2 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 5.0 07774-017 0 2.0 SW1 07774-014 SHUTDOWN CURRENT (µA) 1.0 Figure 14. Shutdown Current vs. Input Voltage Figure 17. Buck 1 Enable Startup Rev. 0 | Page 11 of 28 ADP5020 VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 =4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted. LDO OUTPUT = 1V/DIV TIME = 50µs/DIV SW2 LDO BUCK 2 OUTPUT = 20mV/DIV SW2 = 5V/DIV TIME = 100ns/DIV 07774-030 07774-028 BUCK 2 Figure 18. LDO Startup Figure 20. Buck 2 Switching Node Voltage and Output Ripple Voltage SW1 BUCK 1 BUCK 1 OUTPUT = 2V/DIV BUCK 2 OUTPUT = 1V/DIV LDO OUTPUT = 1V/DIV ENABLE OUTPUT = 2V/DIV TIME = 5ms/DIV LDO BUCK 1 OUTPUT = 20mV/DIV SW1 = 5V/DIV TIME = 100ns/DIV BUCK 2 07774-029 ENABLE Figure 19. Buck 1 Switching Node Voltage and Output Ripple Voltage Figure 21. Three Regulators Turned Off by Sequencer Rev. 0 | Page 12 of 28 07774-031 BUCK 1 ADP5020 THEORY OF OPERATION CIRCUIT OPERATION The buck converters use pMOSFET as the upper switch and nMOSFET as a synchronous rectifier. This synchronous rectification maintains high efficiency for a wide input and output voltage range. The voltage mode control architecture, which features a high frequency bandwidth, provides a fast load and line transient response. The Buck 1 regulator can deliver up to 600 mA with very tight regulation. To minimize cross conduction and maximize efficiency, an antishoot-through circuit is implemented in the gate driver. The two switching regulators operate out of phase, reducing input ripple voltage and current. INTERNAL COMPENSATION The ADP5020 contains an internal compensation network. The compensation circuit is designed to make the synchronous buck converter stable over the input line, output load, and temperature with specified output capacitors and inductors. In addition, the high bandwidth control loop design allows for fast load and line transient response. CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION Both buck converters and the LDO have a current limit feature that allows the ADP5020 to protect itself and any external components during overload and short-circuit conditions. The upper switch pMOSFET turns off if peak current exceeds the limit. The nMOSFET is turned on for a longer period until inductor current drops to 0 A to prevent thermal runaway. The I2C timing specifications are shown in Table 6, and the I2C interface timing diagram is shown in Figure 3. The 7-bit slave address of the ADP5020 is shown in Table 10. UNDERVOLTAGE LOCKOUT The undervoltage lockout block contains the UVLO detector circuits for the battery voltage level. It also contains the status registers that are required to allow the external application processor to determine the status of the power supplies. The most important function of the UVLO circuit is to prevent converter operation if the supply voltage is too low. The UVLO falling condition (when the battery voltage decreases from the operating range level) is set to a typical value of 2.0 V, whereas the UVLO rising condition (when the supply voltage increases from zero) is typically 2.2 V. THERMAL SHUTDOWN The thermal shutdown block (TSD) prevents device damage if the die temperature reaches a level greater than 150°C. When the thermal shutdown limit is reached, the regulator disables the outputs, while waiting for the die to cool down (typically, to 30°C below the thermal shutdown threshold). There are two distinct conditions to be considered when recovering from a thermal shutdown condition: • SYNCHRONIZATION The device has several methods of synchronizing an external clock with the switching regulators. If the external clock is 9.6 MHz, Bit 6 (SYNC_9P6) in the OPERATIONAL_CONTROL register (Address 0x04) must be set to 1, and Bit 5 (SYNC_19P2) must be set to 0. This operation divides the external clock by 3 before it is applied to the switching regulator clock. If the external clock is 19.2 MHz, Bit 5 (SYNC_19P2) in Address 0x04 must be set to 1, and Bit 6 (SYNC_9P6) must be set to 0. This opera-tion divides the external clock by 6 before it is applied to the switching regulator clock. The synchronous clock can be dc- or ac-coupled onto the SYNC pin. For ac coupling, Bit 4 (SYNC_AC) in Address 0x04 is set to 1; for dc coupling, Bit 4 is set to 0. Operational control is performed by I2C writing to Register 0x04. • 2 I C INTERFACE An internal register can be accessed using a synchronous serial interface that implements the standard I2C interface. The ADP5020 behaves as a slave device, communicating at normal speed (100 kHz) or fast speed (400 kHz). Rev. 0 | Page 13 of 28 The EN pin is low. If the EN pin is low and the device is operating in I2C command mode, the outputs remain disabled until the application processor initializes the parameters and performs the sequencing of the regulators. The application processor can sense a generic failure condition by detecting a missing acknowledge bit following an I2C command. When a thermal shutdown condition occurs, Bit 0 (TSD) in the OPERATIONAL_CONTROL register (Address 0x04) is latched to 1 so that the processor can recognize the origin of the failure when resuming from a fault condition. When the TSD bit is set, the application processor must clear this bit to activate the regulators. If the TSD bit is not cleared, writing to the regulator enable bits, Bits[7:4] (BK1_EN, BK2_EN, LDO_EN, and EN_ALL), in the REG_CONTROL_STATUS register (Address 0x03) has no effect. The application processor can also force Bit 0 (TSD) to 1. In this case, the operation proceeds as though a thermal shutdown condition has occurred. The EN pin is high. If the EN pin is high, the device resumes operation automatically from a thermal shutdown condition. The device resumes performing the predefined regulator sequence without processor intervention. Bit 0 (TSD) in the OPERATIONAL_CONTROL register (Address 0x04) is set to indicate that a thermal shutdown has occurred, and it is not possible to activate the regulators using an I2C command unless the host sets the TSD bit to 0. ADP5020 CONTROL REGISTERS DEVICE ADDRESS Following a start condition, the bus master must send the address of the slave it is accessing. The slave address for the ADP5020 is shown in Table 10. The Bit 0 defines the operation to be per- formed. When this bit is set to Logic 1, a read operation is selected. When this bit is set to Logic 0, a write operation is selected. Table 10. Slave Address Bit 7 ADR6 0 Bit 6 ADR5 0 Bit 5 ADR4 1 Bit 4 ADR3 0 Bit 3 ADR2 1 Bit 2 ADR1 0 Bit 1 ADR0 0 Bit 0 R/W 1 or 0 REGISTER MAP Table 11. Address 0x00 0x01 0x02 0x03 Register Name Revision BUCK1_VSEL BUCK2_LDO_VSEL REG_CONTROL_STATUS D7 BK1_EN D6 D5 MAJ[2:0] Reserved[7:3] BK2_VSEL[3:0] BK2_EN LDO_EN 0x04 OPERATIONAL_CONTROL Reserved SYNC_9P6 0x05 EN_CONTROL 0x06 to 0x0F Reserved SYNC_19P2 D4 D3 MIN[2:0] EN_ALL BK1_ PGOOD BK1_ XSHTDN SYNC_ AC Reserved[7:2] D2 D1 D0 OPT[1:0] BK1_VSEL[2:0] LDO_VSEL[3:0] FORCE_XS BK2_ LDO_ PGOOD PGOOD TSD BK2_ LDO_ XSHTDN XSHTDN ENO_DRV ENO_HIZ_ BAR REGISTER DESCRIPTIONS User Accessible Registers Table 12. Revision Register, Address 0x00 Bit [7:5] [4:2] [1:0] Bit Name MAJ[2:0] MIN[2:0] OPT[1:0] Access R R R Default N/A N/A N/A Description Major revision bits. Used to electronically ID the device version. Minor revision bits. Used to electronically ID the device version. Option bits. Used to electronically ID the option (multiple options on same device family). Table 13. BUCK1_VSEL Register, Address 0x01 Bit [7:3] [2:0] Bit Name Reserved BK1_VSEL[2:0] Access N/A R/W Default N/A Fuse Description Reserved. Sets the voltage output level of the Buck 1 regulator. Preloads on power-up with values stored in fuses. Note that this value can be edited by the user in an application. 000 = 2.5 V. 001 = 2.8 V. 010 = 2.9 V. 011 = 3.0 V. 100 = 3.2 V. 101 = 3.3 V (default). 110 = 3.7 V. 111 = reserved. Rev. 0 | Page 14 of 28 ADP5020 Table 14. BUCK2_LDO_VSEL Register, Address 0x02 Bit [7:4] Bit Name BK2_VSEL[3:0] Access R/W Default Fuse [3:0] LDO_VSEL[3:0] R/W Fuse Description Sets the voltage output level of the Buck 2 regulator. Preloads on power-up with values stored in fuses. Note that this value can be edited by a user in an application. 0000 = 1.1 V. 0001 = 1.1 V. 0010 = 1.1 V. 0011 = 1.1 V. 0100 = 1.1 V. 0101 = 1.1 V. 0110 = 1.1 V. 0111 = 1.1 V. 1000 = 1.1 V. 1001 = 1.2 V (default). 1010 = 1.3 V. 1011 = 1.4 V. 1100 = 1.5 V. 1101 = 1.6 V. 1110 = 1.7 V. 1111 = 1.8 V. Sets the voltage output level of the LDO regulator. Preloads on power-up with values stored in fuses. Note that this value can be edited by the user in an application. 0000 = 1.8 V (default). 0001 = 1.9 V. 0010 = 2.0 V. 0011 = 2.1 V. 0100 = 2.2 V. 0101 = 2.3 V. 0110 = 2.4 V. 0111 = 2.5 V. 1000 = 2.6 V. 1001 = 2.7 V. 1010 = 2.8 V. 1011 = 2.9 V. 1100 = 3.0 V. 1101 = 3.1 V. 1110 = 3.2 V. 1111 = 3.3 V. Rev. 0 | Page 15 of 28 ADP5020 Table 15. REG_CONTROL_STATUS Register, Address 0x03 Bit 7 6 5 4 Bit Name BK1_EN BK2_EN LDO_EN EN_ALL Access R/W R/W R/W R/W Default 0 0 0 0 3 BK1_PGOOD R 0 2 BK2_PGOOD R 0 1 LDO_PGOOD R 0 0 FORCE_XS R/W 0 Description 1 = turns on the Buck 1 regulator. If the EN pin is high, the sequencer is ignored. 1 = turns on the Buck 2 regulator. If the EN pin is high, the sequencer is ignored. 1 = turns on the LDO regulator. If the EN pin is high, the sequencer is ignored. 1 = turns on all regulators, following sequencer programming. BK1_EN, BK2_EN, and LDO_EN must all be set to 0 for this bit to function. Power good status for Buck 1. 1 = power good (POK). 0 = fail. Power good status for Buck 2. 1 = power good (POK). 0 = fail. Power good status for LDO. 1 = power good (POK). 0 = fail. 1 = the XSHTDN pin is controlled by the power good signals. 0 = the XSHTDN pin is held low unless the EN pin is high, regardless of regulator status. If EN is high, this bit is ignored in controlling the XSHTDN pin (acts as if FORCE_XS = 1). Table 16. OPERATIONAL_CONTROL Register, Address 0x04 Bit 7 6 Bit Name Reserved SYNC_9P61 Access N/A R/W Default N/A 0 5 SYNC_19P21 R/W 0 4 SYNC_AC 1 R/W 0 3 BK1_XSHTDN R/W Fuse 2 BK2_XSHTDN R/W Fuse 1 LDO_XSHTDN R/W Fuse 0 TSD R/W 0 1 Description Reserved. 1 = a 9.6 MHz clock is on the SYNC pin. The SYNC frequency is divided by 3 and used as clock frequency for switching regulators. 1 = a 19.2 MHz clock is on the SYNC pin. The SYNC frequency is divided by 6 and used as clock frequency for switching regulators. 1 for both SYNC_9P6 and SYNC_19P2 = invalid setting. 0 for both SYNC_9P6 and SYNC_19P2 = clock synchronization is disabled, and the device operates with the 3 MHz internal clock. 1 = the ac path is used for the SYNC input. 0 = the dc path is used (default). 0 = power good for Buck 1 must be high for XSHTDN to go high (default). 1 = Buck 1 power good is ignored. 0 = power good for Buck 2 must be high for XSHTDN to go high (default). 1 = Buck 2 power good is ignored. 0 = LDO power good must be high for XSHTDN to go high (default). 1 = LDO power good is ignored. Shows a latched status of a thermal shutdown (TSD) event. 1 = TSD is active. Must be cleared to 0 by user program to enable the regulators. If this bit remains set to 1, regulator activation is inhibited, as in a thermal shutdown event. The SYNC selection bits (SYNC_AC, SYNC_9P6, and SYNC_19P2) cannot be changed while a switching regulator is running. Table 17. EN_CONTROL Register, Address 0x05 Bit [7:2] 1 Bit Name Reserved ENO_HIZ_BAR Access N/A R/W Default N/A 0 0 ENO_DRV R/W 0 Description Reserved. 0 = the EN/GPIO pin is in high impedance, and the EN function is selected. 1 = GPIO output is selected, and the EN function is ignored. Active only when ENO_HIZ_BAR = 1 (GPIO). 0 = GPIO output is set to low. 1 = GPIO output is set to high. Rev. 0 | Page 16 of 28 ADP5020 POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN The sequencer is enabled after a low-to-high transition of the enable pin (EN). When EN is low or programmed as an output, the sequencing is controlled and timed by the application processor via the I2C commands. Figure 22 shows the default regulator sequencing after a low-tohigh transition of the EN pin. The regulator order is factory programmed and can be changed for specific applications. The power good signal (POK) turns to high if the regulator voltage is ≥80% of the target voltage. The second regulator checks the POK signal of the first regulator and waits the preset delay time (tREG2) before turning on. In addition to changing the regulator order, it is also possible to disable the unused regulator. Additional fuses allow disabling of the association between XSHTDN generation and the POK signal for a specific regulator. The power good signal of an unused regulator must be masked, via dedicated fuse and user registers, to prevent the XSHTDN output from being forced low. A host processor controller, connected to the I2C bus, can override the masking fuses by accessing the following bits in the OPERATIONAL_CONTROL register (Address 0x04): Bit 3 (BK1_XSHTDN, for Buck 1), Bit 2 (BK2_XSHTDN, for Buck 2), and Bit 3 (LDO_XSHTDN, for LDO). Writing 0 to these register bits requires that power good be true to release the XSHTDN pin to high. Writing 1 to these bits causes the regu-lator state to be ignored, and XSHTDN must depend on the active and unmasked regulators. Each regulator inside the ADP5020 is controlled by the sequencer block. The sequencer is factory programmed with a default turn-on sequence that determines the activation order of the regulators. The default activation order is listed as follows: 1. 2. 3. Buck 1 LDO Buck 2 A low-to-high transition of the EN pin, when programmed as an input, or an I2C command setting Bit 4 (EN_ALL) in the REG_CONTROL_STATUS register (Address 0x03), starts the sequencer. The activation delay for the first regulator is determined by the turn-on delay of the band gap, oscillator, and other internal circuits. Therefore, the first regulator cannot be activated before a typical 5 ms delay time has elapsed. Delays between the first and second regulator and from the second to third regulator are hard coded to a specific time (tREG1, tREG2, and tREG3). The delay time starts from the moment a regulator has reached the power good threshold (see Figure 22). The regulators can also be activated individually via the I2C commands. The host specifies which regulator is to be turned on or off by setting or clearing the following selection bits in the REG_CONTROL_STATUS register (Address 0x03): Bit 7 (BK1_EN), Bit 6 (BK2_EN), or Bit 5 (LDO_EN). When the regulators are individually activated by I2C commands, the auto sequencing is disabled and the host controls the turn-on and turn-off timing (see Figure 26). EN tREG1 BUCK 1 POK tREG2 LDO POK tREG3 BUCK 2 POK tXSHTDN 07774-018 XSHTDN Figure 22. Automatic Sequencing with EN Low-to-High Transition Rev. 0 | Page 17 of 28 ADP5020 Activation Waveforms VDDx VUVLOR POR INTERNAL POR EN I2C BUS I2C SEQUENCER REGISTERS PROGRAMMING EN_ ALL = 1 EN_ ALL = 0 tREG1 POK tREG2 BUCK 1 POK tREG3 LDO POK tXSHTDN 07774-019 BUCK 2 XSHTDN Figure 23. Regulators Are Activated by I2C Command VDDx POR INTERNAL POR EN I2C BUS I2C SEQUENCER REGISTERS PROGRAMMING tREG1 POK BUCK 1 tREG2 POK tREG3 LDO POK tXSHTDN 07774-020 BUCK 2 XSHTDN Figure 24. Activation Command Using the EN Pin When activated through the EN pin, the sequencer is affected only by the I2C commands that set or clear the regulator power good masking bits: Bit 3 (BK1_XSHTDN), Bit 2 (BK2_XSHTDN), and Bit 1 (LDO_XSHTDN) in the OPERATIONAL_CONTROL register (Address 0x04). See the Default Power-On Sequence with EN Pin section for more information. The sequence order of the regulators is factory programmed through fuses, but the delays between the regulators (tREG1, tREG2, and tREG3) are fixed and cannot be changed. The EN_ALL bit (Bit 4) in the REG_CONTROL_STATUS regi-ster (Address 0x03) has the same functionality as the EN pin. The sequencer has an antiglitch function that allows it to ignore supply voltage dip if glitch time is less than 50 μs (see Figure 25). Rev. 0 | Page 18 of 28 ADP5020 POWER-ON SEQUENCE USING THE I2C INTERFACE 1. 2. 3. When the EN pin is low, the regulator sequence is controlled by the application processor sending I2C commands to control the activation. When Bit 4 (EN_ALL) in the REG_CONTROL_ STATUS register (Address 0x03) is set to 1, the regulator sequence is as follows: Buck 1 LDO Buck 2 This sequence can be factory programmed through fuses. Unused regulators can also be fuse programmed to be turned off during sequencing. VDDx POR VUVLOR VUVLOF <50µs INTERNAL POR EN I2C BUS I2C SET/CLEAR xxx_XSHTDN BITS tREG1 tREG2 BUCK 1 tREG3 LDO tXSHTDN 07774-021 BUCK 2 XSHTDN Figure 25. Activation and Power Failure Conditions EN I2C BUS BK1_EN =1 LD0_EN =1 BK2_EN =1 FORCE_XS =1 FORCE_XS =0 BK1_EN, LDO_EN, BK2_EN = 0 BUCK 1 LDO 07774-022 BUCK 2 XSHTDN Figure 26. Individual Activation Through I2C Commands Rev. 0 | Page 19 of 28 ADP5020 The application processor, together with the regulator power good signal, controls the XSHTDN pin, as shown in Table 18. After a regulator is enabled and no failure condition is detected (power good = 1 in Bits[3:1] of the REG_CONTROL_STATUS register, Address 0x03), the level of the XSHTDN pin is controlled by Bit 0 (FORCE_XS) in the REG_CONTROL_STATUS register. Therefore, the application processor can write to this register to gain control over the XSHTDN pin. However, if the EN signal is high, the level on the XSHTDN pin depends on the power good condition of the regulator. POWER-UP/POWER-DOWN STATE FLOW Table 18. Truth Table If the supply voltage goes below the VUVLOR threshold, but not below the POR threshold, the registers are preserved. If the supply voltage returns to the normal operating level (above VUVLOR), a new activation does not require initialization of the registers. However, if the supply voltage goes below the POR level, the device is held in reset state. When the input voltage resumes the proper operating level, the host controller must reload the registers. EN Pin 0 0 0 0 1 1 I2C Regulator Enable 0 1 1 1 X1 X1 FORCE_XS X1 0 1 1 X1 X1 XSHTDN Pin 0 0 0 1 1 0 The additional current required to keep the POR monitoring circuits alive during UVLO is estimated to be approximately 1 μA. X = don’t care. NO POWER VDDx > VPOR LEVEL INTERNAL RESET VDDx < VPOR VDDx < VPOR EN = LOW EN = LOW AND 12C OFF COMMAND OR VDDx < VUVLOF EN = HIGH STAND BY NORMAL OPERATION I2 C COMMANDS DEVICE ENABLED (EN_ALL OR EN = HIGH) EN = LOW OR I2C OFF COMMAND OR VDDx < VUVLOF TSD STARTUP SEQUENCER 07774-023 1 Power Good 0 X1 0 1 1 0 When the device is enabled, the UVLO circuit constantly monitors the supply voltage. If the supply voltage falls below the VUVLOF threshold, typically 2.0 V, the regulators are immediately turned off. All the internal analog circuits are then disabled to save power, except the power-on reset (POR) circuit, which detects if the supply voltage is dropping. If the supply voltage is higher than the POR threshold, the POR circuit keeps the logic circuits operating properly and retains the internal values of the registers. This POR threshold is set to approximately 1.4 V. SEQUENCE END, AND ALL REGULATIONS ARE POWER GOOD Figure 27. State Flow Rev. 0 | Page 20 of 28 ADP5020 APPLICATIONS INFORMATION Peak inductor current is calculated in the following equation: POWER GOOD STATUS The ADP5020 constantly monitors the operating conditions. When a regulator is activated, it checks if the output voltage level is above 80% (the power good threshold) of the nominal level for that output. If the output voltage does not reach the power good threshold, one of the three power good status bits in the REG_CONTROL_STATUS register (Address 0x03) is cleared. If the output voltage reaches the power good threshold, one of the power good status bits in the REG_CONTROL_STATUS register is set to 1. The REG_CONTROL_STATUS register contains the following three power good bits: BK1_PGOOD for the Buck 1 output (Bit 3), BK2_PGOOD for the Buck 2 output (Bit 2), and LDO_PGOOD for the LDO output (Bit 1). XSHTDN LOGIC In addition to the power good information for each enabled regulator, an XSHTDN signal is generated, as shown in Table 18. If one or more regulators are unused in a specific application, the masking bits for the disabled regulator, which are fuse programmable and I2C programmable after device startup, must be set to 1 to mask the status of the power good signal. Besides having the masking bits predefined through factory-programmed fuses (necessary only for operation with the EN signal), the ADP5020 provides three masking bits that are accessible through the I2C interface. These bits are located in the OPERATIONAL_ CONTROL register (Address 0x04), where the BK1_XSHTDN bit (Bit 3) is the mask (if set to 1) for Buck 1, the BK2_XSHTDN bit (Bit 2) is the mask (if set to 1) for Buck 2, and the LDO_ XSHTDN bit (Bit 3) is the mask (if set to 1) for the LDO. Additional failures that are verified are the input (VDDA) undervoltage condition, as described in the Undervoltage Lockout section; and an overtemperature condition of the die, as described in the Thermal Shutdown section. As soon as one of these conditions occurs, the active regulators are immediately turned off, and the XSHTDN pin is set to 0. COMPONENTS SELECTION Buck Inductor The buck inductor is chosen to meet output ripple current and ripple voltage requirements with minimum size. The fast load transient response and wide frequency bandwidth are also important factors for inductor selection. The minimum inductance of the buck converter is derived from the following equation: LMINBUCK (V − VOUT ) × VOUT = INMAX VINMAX × f SW × r × IOUT where: VINMAX is the maximum input supply voltage. VOUT is the regulator output voltage in the buck converter. fSW is the converter switching frequency. r is the inductor ripple factor, which is selected as 30%. (1) ILMAX = IOUT + 0.5 × r × IOUT (2) The calculated minimum Buck 2 inductor value is 2.2 μH. The maximum peak inductor current is 325 mA. A ceramic inductor such as the Taiyo Yuden BRL2012T2R2M, with a 600 mA saturation current in a 2 mm × 1.2 mm × 1 mm package, can be used. For the Buck 1 converter, the calculated minimum inductance is 2.2 μH, with maximum peak current of 690 mA. A ceramic inductor such as the Taiyo Yuden BRL2518T2R2M, with a 1 A saturation current in a 2.5 mm × 1.8 mm × 1.2 mm package, is recommended. Input Capacitor Selection The input capacitors are used to decouple the parasitic inductance of input wires to the converters and to reduce the input ripple voltage and the switching ac current flow to the battery rail. The capacitors are selected to support the maximum input operating voltage and the maximum rms current. The capacitance must also be large enough to ensure input stability and suppress input ripple. ESR should as small as possible to decouple the noise. MLCC ceramic capacitors are a good choice for battery-powered applications because of their high capacitance, small size, and low ESR. A 10 μF ceramic capacitor (for example, the JMK107BJ106MA-T from Taiyo Yuden) is recommended. Output Capacitor Selection Output capacitor selection should be based on the following three factors: • • • Maximizing the control loop bandwidth of the converter with the LC filter Minimizing the output voltage ripple Minimizing the size of the capacitor Note that the output ripple is the combination of several factors, including the inductor ripple current (ΔIL), the ESR and ESL output capacitors, and the capacitor impedance at the switching frequency. In buck converters, the output ripple can be calculated as follows: ΔVOUTRIPPLE = ΔIL ⎛⎜ ESR + ⎜ ⎝ ⎞ 1 + 4 × ESL × f SW ⎟⎟ 8 × f SW × COUT ⎠ ΔIL = r × IOUT Capacitor manufacturer data sheets show the ESR and ESL value. In real-life applications, the ripple voltage may be higher because the equations provided in this data sheet do not consider parameters such as board/package parasitic inductance and capacitance. The minimum recommended capacitance is no less than 4.0 μF for Buck 1, 2.0 μF for Buck 2, and 0.4 μF for the LDO. Rev. 0 | Page 21 of 28 ADP5020 ADP5020 LDO INPUT FILTER SW1 VBATT C1 10µF VOUT1 VOUT1 1 2 × π × L3 × C8 (3) where L3 = 250 nH, assuming that fLC = 1 MHz and C8 = 100 nF. The inductor must be able to withstand the LDO load current, including the overload condition, which is limited to 400 mA. Rev. 0 | Page 22 of 28 3.3V C6 10µF The filter resonance frequency is determined by the following equation: f LC = L1 2.2µH BUCK 1 LDO INPUT FILTER L3 VDD3 C8 0.1µF LDO VOUT3 2.8V C3 1µF Figure 28. Optional LDO Input Filter 07774-026 To improve the LDO input-to-output ripple suppression in the critical switching frequency range of the buck converters, it may be necessary to add an LC filter tuned to 1 MHz, as shown in Figure 28. Additional tests and simulation must be performed to assess if this filter is necessary. ADP5020 LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC ADP5020 VDD1 VBATT C4 10µF SW1 GND BUCK 1 INPUT POWER SUPPLIES VDD2 VOUT1 VOUT1 +VIS C1 10µF PGND1 L2 2.2µH BUCK 2 VOUT2 VDD_IO VDDIO C5 0.1µF SDA SCL SCL VOUT3 +VIO C3 1.0µF –VIO SYNC EN/GPIO XSHTDN DGND XSHTDN AGND 07774-027 GPIO/EN –VCORE R2 10kΩ SDA SYNC C2 4.7µF PGND2 LDO R1 10kΩ +VCORE SW2 OUTPUT POWER RAILS C6 1.0µF –VIS VDD3 VDDA PROCESSOR INTERFACE L1 2.2µH Figure 29. Schematic for Camera Module Applications Rev. 0 | Page 23 of 28 ADP5020 • PCB BOARD LAYOUT RECOMMENDATIONS • • • Place the input and output capacitors, C1, C2, C3, C4, and C5, as close as possible to the respective ADP5020 pin, and make the grounding connection to the ADP5020 ground pins as short as possible. Connect C3, C5, and C6 to the analog ground, and connect C1, C2, and C4 to the power ground. Place the L1 and L2 inductors as close as possible to the respective output pins. • • The power and analog ground planes are recommended to keep the noise low. Use one layer for power ground and one layer for analog ground. Tie the power and analog grounds at a single point. Use wide traces to connect the inductor and the input and output capacitors. Add the L3 inductor and the C8 capacitor, if needed, to improve the LDO noise rejection at the switching frequency of the Buck 1 regulator (3 MHz) because the LDO PSRR typically degrades at higher frequencies. If switching noise is not an issue, remove the L3 inductor. EXTERNAL COMPONENT LIST Table 19. Recommended External Components List Reference Designator C1, C4 C1, C4 C2 C3 C5 C6 L1 L2 R1, R2 Description 10 μF, X5R, 6.3 V, ±20% 10 μF, X5R, 6.3 V, ±20% 4.7 μF, X5R, 6.3 V, ±10% 1.0 μF, X5R, 6.3 V, ±10% 0.1 μF, X5R, 10 V, ±10% 1.0 μF, X5R, 6.3 V, ±10% 2.2 μH, DCR = 0.13 Ω, IDC = 1 A 2.2 μH, DCR = 0.23 Ω, IDC = 0.53 A 10 kΩ, 1%, thick film resistor Size 0603 0603 0603 0603 0402 0603 2.5 mm × 1.8 mm × 1.2 mm 2.0 mm × 1.2 mm × 1.0 mm 0402 Rev. 0 | Page 24 of 28 Proposed Vendor Murata Taiyo Yuden Murata Murata Murata Murata Taiyo Yuden Taiyo Yuden KOA Speer Electronics Vendor Part No. GRM188R60J106M JMK107BJ106MA GRM188R60J475K GRM155R60J105K GRM155R61A104K GRM155R60J105K BRL2518T2R2M BRL2012T2R2M RK73H1ETTP1002F ADP5020 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 10 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 090408-B TOP VIEW 6 11 Figure 30. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Model ADP5020ACPZ-R71 ADP5020CP-EVALZ1 1 Temperature Range −40°C to +85°C Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 25 of 28 Package Option CP-20-4 ADP5020 NOTES Rev. 0 | Page 26 of 28 ADP5020 NOTES Rev. 0 | Page 27 of 28 ADP5020 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07774-0-5/09(0) Rev. 0 | Page 28 of 28