TI ADS5433IPJY

3
AD
43
S5
ADS5433
www.ti.com
SLAS503 – APRIL 2006
14 BIT, 80 MSPS ANALOG-TO-DIGITAL CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
14 Bit Resolution
80 MSPS Maximum Sample Rate
Typical SNR = 74.4 dBc at 80 MSPS and
30 MHz IF
Typical SFDR = 96.5 dBc at 80 MSPS and
30 MHz IF
Assured SFDR = 91 dBc at 80 MSPS and
30 MHz IF
2.2 Vpp Differential Input Range
5 V Supply Operation
3.3 V CMOS Compatible Outputs
1.85 W Total Power Dissipation
2s Complement Output Format
On-Chip Input Analog Buffer, Track and Hold,
and Reference Circuit
•
52 Pin HTQFP Package With Exposed
Heatsink
Pin Compatible to the ADS5423, ADS5424,
and AD6644/45
Industrial Temperature Range = –40°C to
85°C
APPLICATIONS
•
•
•
•
Single and Multichannel Digital Receivers
Base Station Infrastructure
Instrumentation
Video and Imaging
RELATED DEVICES
•
•
Clocking: CDC7005
Amplifiers: OPA695, THS4509
DESCRIPTION
The ADS5433 is a 14 bit 80 MSPS analog-to-digital converter (ADC) that operates from 5 V and 3.3 V supplies
while providing 3.3 V CMOS compatible digital outputs. The ADS5433 is optimized for spurious-free dynamic
range (SFDR). Pin-compatible to the ADS5423, ADS5424, and AD6644/45, the ADS5433 provides enhanced
SFDR for input frequencies up to 100 MHz. At 80 MSPS, SFDR is typically 96.5 dBc and is guaranteed to 91
dBc over the industrial temperature range (-40°C to 85°C) with a -1 dBFS 30 MHz input signal.
The ADS5433 input buffer isolates the internal switching of the on-chip Track and Hold (T&H) from disturbing the
signal source. A 2.2 VPP input range and internal reference generator simplify system design. The ADS5433 is
available in a 52 pin HTQFP package and is built on Texas Instrument’s complementary bipolar process
(BiCom3).
FUNCTIONAL BLOCK DIAGRAM
AVDD
AIN
AIN
TH1
A1
+
TH2
Σ
A2
+
TH3
Reference
ADC1
DAC1
ADC2
5
C1
C2
CLK
CLK
A3
ADC3
−
−
VREF
Σ
DRVDD
DAC2
6
5
Digital Error Correction
Timing
DMID OVR
DRY
D[13:0]
GND
B0061-02
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
ADS5433
www.ti.com
SLAS503 – APRIL 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
(1)
PRODUCT
PACKAGE
LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5433
HTQFP52 (1)PowerPAD™
PJY
-40°C to 85°C
ADS5433I
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
ADS5433IPJY
Tray, 160
ADS5433IPJYR
Tape and Reel, 1000
Thermal pad size: Octagonal 2,5 mm side
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage
(1)
ADS5433
UNIT
AVDD to GND
6
V
DRVDD to GND
5
Analog input to GND
–0.3 to AVDD + 0.3
V
Clock input to GND
–0.3 to AVDD + 0.3
V
±2.5
V
CLK to CLK
Digital data output to GND
Operating temperature range
Maximum junction temperature
Storage temperature range
(1)
–0.3 to DRVDD + 0.3
V
–40 to 85
°C
150
°C
–65 to 150
°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL CHARACTERISTICS (1)
PARAMETER
(1)
2
TEST CONDITIONS
TYP
UNIT
θJA
Soldered slug, no airflow
22.5
°C/W
θJA
Soldered slug, 200-LPFM airflow
15.8
°C/W
θJA
Unsoldered slug, no airflow
33.3
°C/W
θJA
Unsoldered slug, 200-LPFM airflow
25.9
°C/W
θJC
Bottom of package (heatslug)
2
°C/W
Using 25 thermal vias (5 × 5 array). See the Application Section.
Submit Documentation Feedback
ADS5433
www.ti.com
SLAS503 – APRIL 2006
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
3
3.3
3.6
V
SUPPLIES
AVDD
Analog supply voltage
DRVDD
Output driver supply voltage
ANALOG INPUT
VCM
Differential input range
2.2
VPP
Input common-mode voltage
2.4
V
10
pF
DIGITAL OUTPUT
Maximum output load
CLOCK INPUT
ADCLK input sample rate (sine wave) 1/tC
Clock amplitude, sine wave,
30
differential (1)
3
Clock duty cycle (2)
MSPS
VPP
50%
Open free-air temperature range
(1)
(2)
80
–40
85
°C
See Figure 12 and Figure 13 for more information.
See Figure 11 for more information.
Submit Documentation Feedback
3
ADS5433
www.ti.com
SLAS503 – APRIL 2006
ELECTRICAL CHARACTERISTICS
Over full temperature range (TMIN = –40°C to TMAX = 85°C), sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 5 V,
DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
UNIT
14
Bits
2.2
VPP
kΩ
ANALOG INPUTS
Differential input range
Differential input resistance
See Figure 27
1
Differential input capacitance
See Figure 27
1.5
pF
570
MHz
2.4
V
Analog input bandwidth
INTERNAL REFERENCE VOLTAGES
VREF
Reference voltage
DYNAMIC ACCURACY
No missing codes
Tested
DNL
Differential linearity error
fIN = 10 MHz
INL
Integral linearity error
fIN = 10 MHz
Offset error
–0.95
±0.5
1.5
±1.5
–5
Offset temperature coefficient
0
LSB
5
1.7
Gain error
–5
PSRR
Gain temperature coefficient
0.9
LSB
mV
ppm/°C
5
%FS
1
mV/V
77
ppm/°C
POWER SUPPLY
IAVDD
Analog supply current
VIN = full scale, fIN = 30 MHz
355
410
mA
IDRVDD
Output buffer supply current
VIN = full scale, fIN = 30 MHz
35
47
mA
Power dissipation
Total power with 10-pF load on each digital
output to ground, fIN = 70 MHz
1.85
2.2
W
20
100
ms
Power-up time
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
fIN = 30 MHz
74.6
73
fIN = 50 MHz
SNR
Signal-to-noise ratio
fIN = 70 MHz
74.3
73
73.4
fIN = 170 MHz
71.9
fIN = 230 MHz
70.5
fIN = 30 MHz
Spurious-free dynamic range
96.5
95.7
fIN = 70 MHz
90.8
84
fIN = 170 MHz
70
fIN = 230 MHz
61.3
Submit Documentation Feedback
dBc
95.3
91
fIN = 50 MHz
fIN = 100 MHz
4
74
fIN = 100 MHz
fIN = 10 MHz
SFDR
74.4
dBc
ADS5433
www.ti.com
SLAS503 – APRIL 2006
ELECTRICAL CHARACTERISTICS (Continued)
Over full temperature range (TMIN = –40°C to TMAX = 85°C), sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 5 V,
DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
72.8
74.5
MAX
UNIT
DYNAMIC AC CHARACTERISTICS (Continued)
fIN = 10 MHz
SINAD
HD2
HD3
Signal-to-noise + distortion
Second harmonic
Third harmonic
Worst-harmonic/spur (other than
HD2 and HD3)
RMS idle channel noise
fIN = 30 MHz
74.4
fIN = 50 MHz
74.2
fIN = 70 MHz
73.8
fIN = 100 MHz
73
fIN = 170 MHz
67.4
fIN = 230 MHz
59.9
fIN = 10 MHz
105
fIN = 30 MHz
103
fIN = 50 MHz
103
fIN = 70 MHz
94
fIN = 100 MHz
96
fIN = 170 MHz
77
fIN = 230 MHz
67
fIN = 10 MHz
97
fIN = 30 MHz
101
fIN = 50 MHz
97
fIN = 70 MHz
91
fIN = 100 MHz
84
fIN = 170 MHz
70
fIN = 230 MHz
61
fIN = 10 MHz
99
fIN = 30 MHz
98
fIN = 50 MHz
99
fIN = 70 MHz
98
fIN = 100 MHz
98
fIN = 170 MHz
94
fIN = 230 MHz
92
Input pins tied together
0.9
dBc
dBc
dBc
dBc
LSB
DIGITAL CHARACTERISTICS
Over full temperature range (TMIN = –40°C to TMAX = 85°C), AVDD = 5 V, DRVDD = 3.3 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.1
0.6
UNIT
DIGITAL OUTPUTS
Low-level output voltage
CLOAD = 10 pF (1)
High-level output voltage
CLOAD = 10 pF (1)
Output capacitance
DMID
(1)
2.6
V
3.2
V
3
pF
DRVDD/2
V
Equivalent capacitance to ground of (load + parasitics of transmission lines).
Submit Documentation Feedback
5
ADS5433
www.ti.com
SLAS503 – APRIL 2006
TIMING REQUIREMENTS (1)
Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 80 MSPS
PARAMETER
MIN
TYP
MAX
UNIT
APERTURE TIME
tA
Aperture delay
500
ps
tJ
Clock slope independent aperture uncertainity (jitter)
150
fs
kJ
Clock slope dependent jitter factor
50
µV
CLOCK INPUT
tCLK
Clock period
12.5
ns
tCLKH (2)
Clock pulsewidth high
6.25
ns
tCLKL (2)
Clock pulsewidth low
6.25
ns
CLOCK TO DATAREADY (DRY)
tDR
Clock rising 50% to DRY falling 50%
tC_DR
Clock rising 50% to DRY rising 50%
tC_DR_50%
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
CLOCK TO DATA,
2.8
3.9
4.7
tDR + tCLKH
9
ns
ns
10.1
11
ns
OVR(4)
tr
Data VOL to data VOH (rise time)
2
ns
tf
Data VOH to data VOL (fall time)
2
ns
L
Latency
3
Cycles
tsu(C)
Valid DATA (3) to clock 50% with 50% duty cycle clock (setup time)
tH(C)
Clock 50% to invalid DATA(3) (hold time)
DATAREADY (DRY) to DATA,
th(DR)_50%
(1)
(2)
(3)
(4)
(5)
(6)
6.3
ns
2.6
3.6
ns
3.3 (6)
4
ns
5.4
5.9
ns
OVR (5)
Valid DATA(3) to DRY 50% with 50% duty cycle clock (setup time)
tsu(DR)_50%
4.8 (4)
DRY 50% to invalid
DATA(3)
with 50% duty cycle clock (hold time)
All values obtained from design and characterization.
See Figure 1 for more information.
See VOH and VOL levels.
tSU(C) = tCLK– tCLK(min) + tSU(C)(min), where tCLK(min) = 12.5 ns and tSU(C)(min) = 4.8 ns for all sample rates equal to or below 80MSPS.
Data is updated with clock rising edge or DRY falling edge.
tSU(DR)50% = (tCLK / 2) – (tCLK(min) / 2) + tSU(DR)(min), where tCLK(min) = 12.5 ns and tSU(DR)(min) = 3.3 ns for all sample rates equal to or
below 80MSPS.
tA
N+3
N
AIN
N+1
N+2
tCLKH
tCLK
CLK, CLK
N+1
N
N+4
tCLKL
N+2
N+3
tC_DR
D[13:0], OVR
DRY
N−3
tr
N−2
tf
tsu(C)
N−1
tsu(DR)
N+4
th(C)
N
th(DR)
tDR
T0073-02
Figure 1. Timing Diagram
6
Submit Documentation Feedback
ADS5433
www.ti.com
SLAS503 – APRIL 2006
PIN CONFIGURATION
DRY
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
DRVDD
GND
D5
D4
PJY PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
DRVDD
GND
VREF
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
1
39
2
3
38
37
4
36
5
6
35
34
7
33
GND
8
9
32
10
30
11
12
29
28
13
27
31
D3
D2
D1
D0 (LSB)
DMID
GND
DRVDD
OVR
DNC
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
C1
GND
AVDD
GND
C2
GND
AVDD
14 15 16 17 18 19 20 21 22 23 24 25 26
P0041-01
PIN ASSIGNMENTS
TERMINAL
NAME
DRVDD
DESCRIPTION
NO.
1, 33, 43
3.3 V power supply, digital output stage only
GND
2, 4, 7, 10, 13, 15,
17, 19, 21, 23, 25,
27, 29, 34, 42
VREF
3
2.4 V reference. Bypass to ground with a 0.1-µF microwave chip capacitor.
CLK
5
Clock input. Conversion initiated on rising edge.
6
Complement of CLK, differential input
CLK
AVDD
Ground
8, 9, 14, 16, 18, 22, 5 V analog power supply
26, 28, 30
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
C1
20
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
C2
24
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
DNC
31
Do not connect
OVR
32
Overrange bit. A logic level high indicates the analog input exceeds full scale.
DMID
35
Output data voltage midpoint. Approximately equal to (DVCC)/2
36
Digital output bit (least significant bit); two's complement
D0 (LSB)
D1–D5, D6–D12
37–41, 44–50
Digital output bits in two's complement
D13 (MSB)
51
Digital output bit (most significant bit); 2s complement
DRY
52
Data ready output
Submit Documentation Feedback
7
ADS5433
www.ti.com
SLAS503 – APRIL 2006
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
Offset Error
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low frequency value.
The offset error is the difference, given in number of
LSBs, between the ADC's actual value average idle
channel output code and the ideal average idle
channel output code. This quantity is often mapped
into mV.
Aperture Delay
The delay in time between the rising edge of the
input sampling clock and the actual time at which the
sampling occurs.
PSRR
The maximum change in offset voltage divided by
the total change in supply voltage, in units of mV/V.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the
time the clock signal remains at a logic high (clock
pulse width) to the period of the clock signal. Duty
cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50%
duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Temperature Drift
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree celcius of the paramter from TMIN or TMAX. It
is computed as the maximum variation of that
parameter over the whole temperature range divided
by TMAX – TMIN.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first five harmonics.
P
SNR 10Log 10 S
PN
(1)
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog
input values spaced exactly 1 LSB apart. The DNL is
the deviation of any single step from this ideal value,
measured in units of LSB.
Integral Nonlinearity (INL)
The INL is the deviation of the ADC's transfer
function from a best fit line determined by a least
squares curve fit of that transfer function, measured
in units of LSB.
Gain Error
The gain error is the deviation of the ADC's actual
input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input
full-scale range.
8
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral
components including noise (PN) and distortion (PD),
but excluding dc.
PS
SINAD 10Log 10
PN PD
(2)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
Total Harmonic Distortion (THD)
THD is the ratio of the fundamental power (PS) to the
power of the first five harmonics (PD).
Submit Documentation Feedback
ADS5433
www.ti.com
SLAS503 – APRIL 2006
THD 10Log 10
Two-Tone Intermodulation Distortion
PS
PD
(3)
THD is typically given in units of dBc (dB to carrier).
Power Up Time
The difference in time from the point where the
supplies are stable at ±5% of the final value, to the
time the ac test is past.
IMD3 is the ratio of the power of the fundamental (at
frequiencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to full scale) when it is
referred to the full-scale range.
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc
(dB to carrier).
Submit Documentation Feedback
9
ADS5433
www.ti.com
SLAS503 – APRIL 2006
TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fS = 80 MSPS
fIN = 2 MHz
SNR = 74.5 dBc
SINAD = 74.4 dBc
SFDR = 95.7 dBc
THD = 89.9 dBc
−40
fS = 80 MSPS
fIN = 30 MHz
SNR = 74.4 dBc
SINAD = 74.3 dBc
SFDR = 97.2 dBc
THD = 95.5 dBc
−20
Amplitude − dBFS
Amplitude − dBFS
−20
−60
−80
−40
−60
−80
−100
−100
−120
−120
0
5
10
15
20
25
30
35
0
40
f − Frequency − MHz
5
10
15
SPECTRAL PERFORMANCE
35
40
G002
TWO-TONE INTERMODULATION DISTORTION
0
fS = 80 MSPS
fIN = 70 MHz
SNR = 74 dBc
SINAD = 73.9 dBc
SFDR = 93.7 dBc
THD = 90.6 dBc
−40
fIN1 = 19.8 MHz, −7 dBFS
fIN2 = 20.2 MHz, −7 dBFS
IMD3 = −100.1 dBFS
−20
Amplitude − dB
−20
Amplitude − dBFS
30
Figure 3.
0
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
5
10
15
20
25
30
35
40
f − Frequency − MHz
0
5
10
15
20
25
30
35
40
f − Frequency − MHz
G003
Figure 4.
G004
Figure 5.
TWO-TONE INTERMODULATION DISTORTION
TWO-TONE INTERMODULATION DISTORTION
0
0
fIN1 = 19.8 MHz, −15 dBFS
fIN2 = 20.2 MHz, −15 dBFS
IMD3 = −105.9 dBFS
fIN1 = 59.8 MHz, −7 dBFS
fIN2 = 60.2 MHz, −7 dBFS
IMD3 = −103.6 dBFS
−20
Amplitude − dB
−20
Amplitude − dB
25
f − Frequency − MHz
G001
Figure 2.
−40
−60
−80
−40
−60
−80
−100
−100
−120
−120
0
5
10
15
20
25
f − Frequency − MHz
30
35
0
40
G005
Figure 6.
10
20
5
10
15
20
25
f − Frequency − MHz
Figure 7.
Submit Documentation Feedback
30
35
40
G006
ADS5433
www.ti.com
SLAS503 – APRIL 2006
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
TWO-TONE INTERMODULATION DISTORTION
AC PERFORMANCE vs INPUT AMPLITUDE
0
120
100
AC Performance − dB
Amplitude − dB
SFDR (dBFS)
fIN1 = 59.8 MHz, −15 dBFS
fIN2 = 60.2 MHz, −15 dBFS
IMD3 = −110.3 dBFS
−20
−40
−60
−80
−100
SNR (dBFS)
80
60
SFDR (dBc)
40
20
SNR (dBc)
0
−120
0
5
10
15
20
25
30
35
−20
−90
40
f − Frequency − MHz
fS = 80 MSPS
fIN = 30 MHz
−80
−70
−60
−50
−40
−30
−20
−10
0
AIN − Input Amplitude − dBFS
G007
G008
Figure 8.
Figure 9.
AC PERFORMANCE vs INPUT AMPLITUDE
TWO-TONE SPURIOUS-FREE DYNAMIC RANGE vs INPUT
AMPLITUDE
120
120
SFDR (dBFS)
100
SNR (dBFS)
Two-Tone SFDR − dB
AC Performance − dB
100
80
60
SFDR (dBc)
40
20
SNR (dBc)
0
−80
−70
−60
−50
−40
−30
−20
−10
80
60
40
SFDR (dBc)
20
90 dBFS Line
fS = 80 MSPS
fIN1 = 69 MHz
fIN2 = 71 MHz
0
fS = 80 MSPS
fIN = 70 MHz
−20
−90
SFDR (dBFS)
−20
−110−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
AIN − Input Amplitude − dBFS
G009
Figure 10.
G010
Figure 11.
NOISE HISTOGRAM WITH INPUTS SHORTED
SPURIOUS-FREE DYNAMIC RANGE vs DUTY CYCLE
45
100
fIN = 2 MHz
40
95
35
30
SFDR − dBc
Percentage − %
0
AIN − Input Amplitude − dBFS
25
20
15
10
90
fIN = 30 MHz
85
80
5
0
75
8169 8170 8171 8172 8173 8174 8175 8176 8177
Code Number
30
G011
Figure 12.
40
50
Duty Cycle − %
60
70
G012
Figure 13.
Submit Documentation Feedback
11
ADS5433
www.ti.com
SLAS503 – APRIL 2006
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
AC PERFORMANCE vs CLOCK LEVEL
AC PERFORMANCE vs CLOCK LEVEL
100
100
95
95
SFDR (dBc)
85
80
SNR (dBc)
75
70
65
60
fS = 80 MSPS
fIN = 30 MHz
55
50
0
80
1
2
3
4
SNR (dBc)
75
70
65
60
50
0.0
fS = 80 MSPS
fIN = 70 MHz
0.5
1.5
2.0
2.5
3.0
3.5
4.0
Clock Level − VPP
G014
Figure 14.
Figure 15.
AC PERFORMANCE vs CLOCK COMMON MODE
SPURIOUS-FREE DYNAMIC RANGE vs ANALOG SUPPLY
VOLTAGE
110
99
40°C
fS = 80 MSPS
fIN = 30 MHz
100
SFDR − dBc
90
80
−20°C
SNR (dBc)
70
60
97
96
95
60°C
50
30
0.0
0°C
98
SFDR (dBc)
85°C
94
40
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Clock Common Mode − V
93
4.65
5.0
−40°C
fS = 80 MSPS
fIN = 30 MHz
4.75
4.85
4.95
5.05
5.15
5.25
5.35
AVDD − Analog Supply Voltage − V
G015
G016
Figure 16.
Figure 17.
SIGNAL-TO-NOISE RATIO vs ANALOG SUPPLY VOLTAGE
SPURIOUS-FREE DYNAMIC RANGE vs DIGITAL SUPPLY
VOLTAGE
75.2
75.0
99
−20°C
−40°C
SFDR − dBc
74.6
0°C
74.4
74.2
40°C
74.0
97
96
40°C
85°C
95
−40°C
60°C
73.8
73.6
0°C
−20°C
98
74.8
73.4
4.65
fS = 80 MSPS
fIN = 30 MHz
4.75
4.85
94
60°C
85°C
4.95
5.05
5.15
AVDD − Analog Supply Voltage − V
5.25
5.35
93
2.7
fS = 80 MSPS
fIN = 30 MHz
2.8
G017
Figure 18.
12
1.0
G013
120
AC Performance − dB
85
55
Clock Level − VPP
SNR − Signal-to-Noise Ratio − dBc
SFDR (dBc)
90
AC Performance − dB
AC Performance − dB
90
2.9
3.0
3.1
3.2
3.3
3.5
DRVDD − Digital Supply Voltage − V
Figure 19.
Submit Documentation Feedback
3.4
3.6
3.7
G018
ADS5433
www.ti.com
SLAS503 – APRIL 2006
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SNR − Signal-to-Noise Ratio − dBc
−40°C
−20°C
75.0
74.8
74.6
0°C
74.4
74.2
74.0
73.8
40°C
73.6
73.4
2.7
2.8
2.9
60°C
85°C
fS = 80 MSPS
fIN = 30 MHz
3.0
3.1
3.2
3.3
3.4
3.5
DIFFERENTIAL NONLINEARITY
DNL − Differential Nonlinearity − LSB
SIGNAL-TO-NOISE RATIO vs DIGITAL SUPPLY VOLTAGE
75.2
3.6
1.0
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
3.7
DRVDD − Digital Supply Voltage − V
fIN = 10 MHz
0.8
5000
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
DNL − Differential Nonlinearity − LSB
fIN = 10 MHz
1.0
0.5
0.0
−0.5
−1.0
−1.5
10000
1.0
fIN = 30 MHz
0.8
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
15000
Code
0
5000
10000
Code
G021
Figure 22.
15000
G022
Figure 23.
INTEGRAL NONLINEARITY
2.0
INL − Integral Nonlinearity − LSB
INL − Integral Nonlinearity − LSB
G020
Figure 21.
1.5
5000
15000
Code
G019
Figure 20.
0
10000
fIN = 30 MHz
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
5000
10000
Code
15000
G023
Figure 24.
Submit Documentation Feedback
13
ADS5433
www.ti.com
SLAS503 – APRIL 2006
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY AND SAMPLING FREQUENCY
120
72
74
73
fS - Sampling Frequency - MHz
110
74
100
90
73
80
72
70
74
60
73
72
50
74
70
40
73
70
72
30
20
20
60
40
68
68
70
100
80
66
120
64
140
160
fIN - Input Frequency - MHz
64
62
70
68
66
72
74
SNR - dBc
M0048-07
Figure 25.
SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY AND SAMPLING FREQUENCY
120
92
90
100
84
88
110
fS - Sampling Frequency - MHz
90
84
94
76
80
72
88
94
90
92
92
88
90
84
94
96
80
96
70
92 90
96
60
96
76
80
72
88
94
50
96
40
92
94
30
20
96
20
84
88
90
60
40
100
80
72
76
80
120
140
160
fIN - Input Frequency - MHz
70
75
80
85
SFDR - dBc
Figure 26.
14
Submit Documentation Feedback
90
95
100
M0048-08
ADS5433
www.ti.com
SLAS503 – APRIL 2006
EQUIVALENT CIRCUITS
DRVDD
AVDD
AIN
BUF
T/H
500 Ω
VREF
BUF
AVDD
500 Ω
AIN
BUF
S0187-01
T/H
S0186-01
Figure 27. Analog Input
Figure 28. Digital Output
AVDD
AVDD
+
CLK
Bandgap
1 kΩ
25 Ω
VREF
−
Clock Buffer
1.2 kΩ
Bandgap
1.2 kΩ
AVDD
1 kΩ
S0189-01
CLK
S0188-01
Figure 29. Clock Input
Figure 30. Reference
DRVDD
AVDD
10 kΩ
DMID
−
DAC
Bandgap
+
C1, C2
IOUTP
IOUTM
10 kΩ
S0190-01
S0191-01
Figure 31. Decoupling Pin
Figure 32. DMID Generation
Submit Documentation Feedback
15
ADS5433
www.ti.com
SLAS503 – APRIL 2006
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5433 is a 14 bit, 80 MSPS, monolithic
pipeline analog to digital converter. Its bipolar analog
core operates from a 5 V supply, while the output
uses 3.3 V supply for compatibility with the CMOS
family. The conversion process is initiated by the
rising edge of the external input clock. At that instant,
the differential input signal is captured by the input
track and hold (T&H) and the input sample is
sequentially converted by a series of small resolution
stages, with the outputs combined in a digital
correction logic block. Both the rising and the falling
clock edges are used to propagate the sample
through the pipeline every half clock cycle. This
process results in a data latency of three clock
cycles, after which the output data is available as a
14 bit parallel word, coded in binary two's
complement format.
INPUT CONFIGURATION
The analog input for the ADS5433 (see Figure 27)
consists of an analog differential buffer followed by a
bipolar track-and-hold. The analog buffer isolates the
source driving the input of the ADC from any internal
switching. The input common mode is set internally
through a 500 Ω resistor connected from 2.4 V to
each of the inputs. This results in a differential input
impedance of 1 kΩ.
maximum signal swing of 1.1 VPP for a total
differential input signal swing of 2.2 VPP. The
maximum swing is determined by the internal
reference voltage generator eliminating any external
circuitry for this purpose.
The ADS5433 obtains optimum performance when
the analog inputs are driven differentially. The circuit
in Figure 33 shows one possible configuration using
an RF transformer with termination either on the
primary or on the secondary of the transformer. If
voltage gain is required a step up transformer can be
used. For higher gains that would require impractical
higher turn ratios on the transformer, a single-ended
amplifier driving the transformer can be used (see
Figure 34). Another circuit optimized for performance
would be the one on Figure 35, using the THS4304
or the OPA695. Texas Instruments has shown
excellent performance on this configuration up to 10
dB gain with the THS4304 and at 14 dB gain with the
OPA695. For the best performance, they need to be
configured differentially after the transformer (as
shown) or in inverting mode for the OPA695 (see
SBAA113); otherwise, HD2 from the op amps limits
the useful frequency.
R0
50
VIN
R
50
AC Signal
Source
ADS5433
AIN
ADT1−1WT
S0176-02
Figure 33. Converting a Single-Ended Input to
a Differential Signal Using RF Transformers
−5 V
RS
100 Ω
+
OPA695
−
0.1 µF
1000 µF
RIN
1:1
RT
100 Ω
RIN
R1
400 Ω
R2
57.5 Ω
AIN
1:1
For a full-scale differential input, each of the
differential lines of the input signal (pins 11 and 12)
swings symmetrically between 2.4 +0.55 V and 2.4
–0.55 V. This means that each input is driven with a
signal of up to 2.4 ±0.55 V, so that each input has a
5V
Z0
50
AIN
CIN
ADS5433
AIN
AV = 8V/V
(18 dB)
S0177-02
Figure 34. Using the OPA695 With the ADS5433
16
Submit Documentation Feedback
ADS5433
www.ti.com
SLAS503 – APRIL 2006
RG
RF
CM
5V
−
THS4304
+
1:1
VIN
49.9 Ω
CM
From
50 Ω
Source
AIN
ADS5433
VREF
AIN
5V
+
THS4304
−
RG
CM
RF
CM
S0192-01
Figure 35. Using the THS4304 With the ADS5433
Besides these, Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202, and OPA847)
that can be selected depending on the application.
An RF gain block amplifier, such as Texas
Instrument's THS9001, can also be used with an RF
transformer for high input frequency applications. For
applications requiring dc-coupling with the signal
source, instead of using a topology with three single
ended amplifiers, a differential input/differential
output amplifier like the THS4509 (see Figure 36)
can be used, which minimizes board space and
reduce number of components.
Figure 38 shows their combined SNR and SFDR
performance versus frequency with –1 dBFS input
signal level and sampling at 80 MSPS.
On this configuration, the THS4509 amplifier circuit
provides 10 dB of gain, converts the single-ended
input to differential, and sets the proper input
common-mode voltage to the ADS5433.
The 225 Ω resistors and 2.7 pF capacitor between
the THS4509 outputs and ADS5433 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100 MHz (–3 dB).
For this test, an Agilent signal generator is used for
the signal source. The generator is an ac-coupled 50
Ω source. A band-pass filter is inserted in series with
the input to reduce harmonics and noise from the
signal source.
Input termination is accomplished via the 69.8 Ω
resistor and 0.22 mF capacitor to ground in
conjunction with the input impedance of the amplifier
circuit. A 0.22 µF capacitor and 49.9 Ω resistor is
inserted to ground across the 69.8 W resistor and
0.22 µF capacitor on the alternate input to balance
the circuit.
Gain is a function of the source impedance,
termination, and 348 Ω feedback resistor. See the
THS4509 data sheet for further component values to
set proper 50 Ω termination for other common gains.
Since
the
ADS5433
recommended
input
common-mode voltage is +2.4 V, the THS4509 is
operated from a single power supply input with VS+ =
+5 V and VS– = 0 V (ground). This maintains
maximum headroom on the internal transistors of the
THS4509.
From VIN
50 Ω
Source
100 Ω
69.8 Ω
348 Ω
+5V
225 Ω
0.22 µF
100 Ω
49.9 Ω
0.22 µF
69.8 Ω
THS 4509
2.7 pF
225 Ω
CM
0.22 µF
348 Ω
14-Bit
80 MSPS
AIN
ADS5433
AIN VREF
49.9 Ω
0.1 µF
0.1 µF
S0193-01
Figure 36. Using the THS4509 With the ADS5433
Submit Documentation Feedback
17
ADS5433
www.ti.com
SLAS503 – APRIL 2006
with any other ADCs) at the system level. The first
advantage is that it allows for common-mode noise
rejection at the PCB level. A further analysis (see
Clocking High Speed Data Converters, SLYT075)
reveals one more advantage. The following formula
describes the different contributions to clock jitter:
(Jittertotal)2 = (EXT_jitter)2+ (ADC_jitter)2=
(EXT_jitter)2 + (ADC_int)2 + (K/clock_slope)2
95
Performance − dB
90
SFDR (dBc)
85
80
SNR (dBFS)
75
70
10
20
30
40
50
60
70
fIN − Input Frequency − MHz
G024
Figure 37. Performance vs Input Frequency for
the THS4509 + ADS5433 Configuration
Square Wave or
Sine Wave
CLK
0.01 µF
ADS5433
CLK
The use of differential clock allows for the use of
bigger clock amplitudes without exceeding the
absolute maximum ratings. This, on the case of
sinusoidal clock, results on higher slew rates which
minimizes the impact of the jitter factor inversely
proportional to the clock slope.
0.01 µF
S0168-03
Figure 38. Single-Ended Clock
CLOCK INPUTS
The ADS5433 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between
both configurations. In low input frequency
applications, where jitter may not be a big concern,
the use of single ended clock (see Figure 38) could
save some cost and board space without any
trade-off in performance. When driven on this
configuration, it is best to connect CLKM (pin 11) to
ground with a 0.01 µF capacitor, while CLKP is
ac-coupled with a 0.01 µF capacitor to the clock
source, as shown in Figure 35.
0.1 µF
Clock
Source
The first term would represent the external jitter,
coming from the clock source, plus noise added by
the system on the clock distribution, up to the ADC.
The second term is the ADC contribution, which can
be divided in two portions. The first does not depend
directly on any external factor. That is the best we
can get out of our ADC. The second contribution is a
term inversely proportional to the clock slope. The
faster the slope, the smaller this term will be. As an
example, we could compute the ADC jitter
contribution from a sinusoidal input clock of 3 VPP
amplitude and Fs = 80 MSPS:
ADC_jitter = sqrt ((150fs)2+ (5 × 10-5/(1.5 × 2 ×
PI × 80 × 106))2) = 164fs
Figure 39 shows this approach. The back-to-back
Schottky can be added to limit the clock amplitude in
cases where this would exceed the absolute
maximum ratings, even when using a differential
clock. Figure 12 and Figure 13 show the
performance versus input clock amplitude for a
sinusoidal clock.
100 nF
MC100EP16DT
100 nF
D
D
ADS5433
100 nF
ADS5433
CLK
499 CLK
MA3X71600LCT−ND
CLK
Q
VBB Q
499 1:4
100 nF
50 Ω
50 Ω
100 nF
113 Ω
CLK
S0195-01
S0194-01
Figure 40. Differential Clock Using PECL Logic
Figure 39. Differential Clock
Nevertheless, for jitter sensitive applications, the use
of a differential clock will have some advantages (as
18
Another possibility is the use of a logic based clock,
as PECL. In this case, the slew rate of the edges will
most likely be much higher than the one obtained for
Submit Documentation Feedback
ADS5433
www.ti.com
SLAS503 – APRIL 2006
the same clock amplitude based on a sinusoidal
clock. This solution would minimize the effect of the
slope dependent ADC jitter. Nevertheless, observe
that for the ADS5433, this term is small and has
been optimized. Using logic gates to square a
sinusoidal clock may not produce the best results as
logic gates may not have been optimized to act as
comparators, adding too much jitter while squaring
the inputs.
The common-mode voltage of the clock inputs is set
internally to 2.4 V using internal 1 kΩ resistors. It is
recommended using an ac coupling, but if for any
reason, this scheme is not possible, due to, for
instance, asynchronous clocking, the ADS5433
presents a good tolerance to clock common-mode
variation (see Figure 14).
Additionally, the internal ADC core uses both edges
of the clock for the conversion process. This means
that, ideally, a 50% duty cycle should be provided.
Figure 11 shows the performance variation of the
ADC versus clock duty cycle.
DIGITAL OUTPUTS
The ADC provides 14 data outputs (D13 to D0, with
D13 being the MSB and D0 the LSB), a data-ready
signal (DRY, pin 52), and an out-of-range indicator
(OVR, pin 32) that equals 1 when the output reaches
the full-scale limits.
The output format is two's complement. When the
input voltage is at negative full scale (around –1.1 V
differential), the output will be, from MSB to LSB, 10
0000 0000 0000. Then, as the input voltage is
increased, the output switches to 10 0000 0000
0001, 10 0000 0000 0010 and so on until 11 1111
1111 1111 right before mid-scale (when both inputs
are tied together if we neglect offset errors). Further
increase on input voltages, outputs the word 00 0000
0000 0000, to be followed by 00 0000 0000 0001, 00
0000 0000 0010 and so on until reaching 01 1111
1111 1111 at full-scale input (1.1 V differential).
Although the output circuitry of the ADS5433 has
been designed to minimize the noise produced by
the transients of the data switching, care must be
taken when designing the circuitry reading the
ADS5433 outputs. Output load capacitance should
be minimized by minimizing the load on the output
traces, reducing their length and the number of gates
connected to them, and by the use of a series
resistor with each pin. Typical numbers on the data
sheet tables and graphs are obtained with 100 Ω
series resistor on each digital output pin, followed by
a 74AVC16244 digital buffer as the one used in the
evaluation board.
POWER SUPPLIES
The use of low noise power supplies with adequate
decoupling is recommended, being the linear
supplies the first choice vs switched ones, which
tend to generate more noise components that can be
coupled to the ADS5433.
The ADS5433 uses two power supplies. For the
analog portion of the design, a 5 V AVDD is used,
while for the digital outputs supply (DRVDD), we
recommend the use of 3.3 V. All the ground pins are
marked as GND, although AGND pins and DRGND
pins are not tied together inside the package.
Customers willing to experiment with different
grounding schemes should know that AGND pins are
4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, and 29, while
DRGND pins are 2, 34, and 42. Nevertheless, we
recommend that both grounds are tied together
externally, using a common ground plane. That is the
case on the production test boards and modules
provided to customer for evaluation. In order to
obtain the best performance, the user should layout
the board to assure that the digital return currents do
not flow under the analog portion of the board. This
can be achieved without the need to split the board
and just with careful component placing and
increasing the number of vias and ground planes.
Finally, notice that the metallic heat sink under the
package is also connected to analog ground.
LAYOUT INFORMATION
The evaluation board represents a good guideline of
how to layout the board to obtain the maximum
performance out of the ADS5433. General design
rules as the use of multilayer boards, single ground
plane for both, analog and digital ADC ground
connections and local decoupling ceramic chip
capacitors should be applied. The input traces
should be isolated from any external source of
interference or noise, including the digital outputs as
well as the clock traces. The clock should also be
isolated from other signals, especially on applications
where low jitter is required, as high IF sampling.
Besides performance oriented rules, special care has
to be taken when considering the heat dissipation
out of the device. The thermal heat sink (octagonal,
with 2,5 mm on each side) should be soldered to the
board, and provision for more than 16 ground vias
should be made. The thermal package information
describes the TJA values obtained on the different
configurations.
Submit Documentation Feedback
19
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Mailing Address:
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2006, Texas Instruments Incorporated