AD S5 463 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 12-Bit, 500-MSPS Analog-to-Digital Converter • FEATURES • • • • • • • • • • 500-MSPS Sample Rate 12-Bit Resolution, 10.5 Bits ENOB 2-GHz Input Bandwidth SFDR = 75 dBc at 450 MHz and 500 MSPS SNR = 64.6 dBFS at 450 MHz and 500 MSPS 2.2-Vpp Differential Input Voltage LVDS-Compatible Outputs Total Power Dissipation: 2.2 W Offset Binary Output Format Output Data Transitions on the Rising and Falling Edges of a Half-Rate Output Clock • • • On-Chip Analog Buffer, Track and Hold, and Reference Circuit 80-Pin TQFP PowerPAD™ Package (14-mm × 14-mm) Industrial Temperature Range = –40°C to 85°C Pin-Similar to ADS5440/ADS5444 APPLICATIONS • • • • • • Test and Measurement Instrumentation Software-Defined Radio Data Acquisition Power Amplifier Linearization Communication Instrumentation Radar DESCRIPTION The ADS5463 is a 12-bit, 500-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. The ADS5463 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design. Designed to optimize conversion of wide-bandwidth signals up to 500 MHz of input frequency at 500 MSPS, the ADS5463 has outstanding low noise and linearity over a large input frequency range. Input signals above 500 MHz can also be converted due to the large input bandwidth of the device. The ADS5463 is available in an 80-pin TQFP PowerPAD™ package. The ADS5463 is built on state-of-the-art Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full industrial temperature range (–40°C to 85°C). VIN VIN A1 TH1 + TH2 S + TH3 A2 VREF A3 ADC3 – – ADC1 S DAC1 ADC2 DAC2 Reference 5 5 5 Digital Error Correction CLK CLK Timing OVR OVR DRY DRY D[11:0] B0061-03 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS5463 HTQFP-80 (2) PowerPAD PFP –40°C to 85°C ADS5463I (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5463IPFP Tray, 96 ADS5463IPFPR Tape and reel, 1000 For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet. Thermal pad size: 9.5 mm × 9.5 mm (minimum), 10 mm × 10 mm (maximum). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) ADS5463 UNIT AVDD5 to GND 6 V AVDD3 to GND 5 V DVDD3 to GND 5 V Analog input to GND –0.3 to (AVDD5 + 0.3) V Clock input to GND –0.3 to (AVDD5 + 0.3) V ±2.5 V Supply voltage CLK to CLK Digital data output to GND –0.3 to (DVDD3 + 0.3) V –40 to 85 °C Operating temperature range Maximum junction temperature Storage temperature range ESD, human-body model (HBM) (1) 150 °C –65 to 150 °C 2 kV Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime is available upon request. THERMAL CHARACTERISTICS (1) PARAMETER (2)R θJA (3)R θJP (1) (2) (3) 2 TEST CONDITIONS TYP Soldered thermal pad, no airflow 23.7 Soldered thermal pad, 150-LFM airflow 17.8 Soldered thermal pad, 250-LFM airflow 16.4 Bottom of package (thermal pad) 2.99 Using 36 thermal vias (6 × 6 array). See PowerPAD Package in the Application Information section. RθJA is the thermal resistance from the junction to ambient. RθJP is the thermal resistance from the junction to the thermal pad. Submit Documentation Feedback UNIT °C/W °C/W ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT SUPPLIES AVDD5 Analog supply voltage 4.75 5 5.25 V AVDD3 Analog supply voltage 3 3.3 3.6 V DVDD3 Output driver supply voltage 3 3.3 3.6 V ANALOG INPUT VCM Differential input range 2.2 Vpp Input common mode 2.4 V 10 pF DIGITAL OUTPUT (DRY, DATA, OVR) Maximum differential output load CLOCK INPUT (CLK) CLK input sample rate (sine wave) 20 500 Clock amplitude, differential sine wave 3 Clock duty cycle TA MSPS Vpp 50% Open free-air temperature –40 85 °C ELECTRICAL CHARACTERISTICS Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Resolution TYP MAX UNIT 12 Bits Differential input range 2.2 Vpp Input common mode 2.4 V ANALOG INPUTS VCM CMRR Input resistance (dc) Each input to ground 500 Ω Input capacitance Each input to ground 2.5 pF Analog input bandwidth (–3 dB) Dependent on source impedance 2 GHz Common-mode rejection ratio Common mode signal = 10 MHz 80 dB 2.4 V INTERNAL REFERENCE VOLTAGE VREF Reference voltage DYNAMIC ACCURACY No missing codes Assured DNL Differential linearity error fIN = 10 MHz INL Integral linearity error fIN = 10 MHz Offset error ±0.25 0.95 LSB –2.5 +0.8/–0.3 2.5 LSB –11 11 –0.95 Offset temperature coefficient 0.0005 Gain error –5 Gain temperature coefficient PSRR 5 %FS ∆%/°C –0.02 100-kHz supply noise (see Figure 32) mV mV/°C 85 dB POWER SUPPLY IAVDD5 5-V analog supply current 300 330 mA IAVDD3 3.3-V analog supply current IDVDD3 3.3-V digital supply current (includes LVDS) 125 138 mA 82 88 mA Total power dissipation 2.18 2.4 Power-up time 200 VIN = full scale, fIN = 10 MHz, fS = 500 MSPS Submit Documentation Feedback W µs 3 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 65.3 fIN = 70 MHz 65.4 fIN = 100 MHz 63.5 fIN = 230 MHz SNR Signal-to-noise ratio fIN = 300 MHz 65.1 63 64.6 fIN = 650 MHz 63.9 fIN = 900 MHz 62.6 fIN = 1.3 GHz 59.3 fIN = 10 MHz 85 fIN = 100 MHz fIN = 300 MHz 78 64 fIN = 650 MHz 65 fIN = 900 MHz 56 fIN = 1.3 GHz 45 fIN = 10 MHz 87 fIN = 300 MHz 81 64 4 Third harmonic 77 80 fIN = 650 MHz 77 fIN = 900 MHz 66 fIN = 1.3 GHz 50 fIN = 10 MHz 85 fIN = 70 MHz 90 70 fIN = 230 MHz HD3 80 fIN = 450 MHz fIN = 100 MHz fIN = 300 MHz dBc 87 90 64 80 fIN = 450 MHz 75 fIN = 650 MHz 65 fIN = 900 MHz 56 fIN = 1.3 GHz 45 Submit Documentation Feedback dBc 82 70 fIN = 230 MHz Second harmonic 77 75 fIN = 70 MHz HD2 82 fIN = 450 MHz fIN = 100 MHz dBFS 82 70 fIN = 230 MHz Spurious-free dynamic range 65 fIN = 450 MHz fIN = 70 MHz SFDR 65.3 dBc ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS (continued) Worst harmonic/spur (other than HD2 and HD3) THD Total Harmonic Distortion fIN = 10 MHz 86 fIN = 70 MHz 86 fIN = 100 MHz 86 fIN = 230 MHz 77 fIN = 300 MHz 81 fIN = 450 MHz 86 fIN = 650 MHz 85 fIN = 900 MHz 78 fIN = 1.3 GHz 67 fIN = 10 MHz 80 fIN = 70 MHz 79 fIN = 100 MHz 77 fIN = 230 MHz 75 fIN = 300 MHz 73 fIN = 450 MHz 73 fIN = 650 MHz 64 fIN = 900 MHz 55 fIN = 1.3 GHz 65.2 fIN = 70MHz SINAD Signal-to-noise and distortion Two-tone SFDR ENOB Effective number of bits RMS idle-channel noise 65.2 62 65.1 fIN = 230MHz 64.7 fIN = 300MHz 64.5 fIN = 450MHz 64.1 fIN = 650MHz 61.5 fIN = 900MHz 55.4 fIN = 1.3GHz 45.1 fIN1 = 65 MHz, fIN2 = 70 MHz, each tone at –7 dBFS 90 fIN1 = 65 MHz, fIN2 = 70 MHz, each tone at –16 dBFS 89 fIN1 = 350 MHz, fIN2 = 355 MHz, each tone at –7 dBFS 82 fIN1 = 350 MHz, fIN2 = 355 MHz, each tone at –16 dBFS 89 fIN = 100 MHz dBc 44 fIN = 10MHz fIN = 100MHz dBc 10 fIN = 300 MHz dBc dBFS 10.5 Bits 10.4 Inputs tied to common-mode 0.7 LSB LVDS DIGITAL OUTPUTS VOD Differential output voltage (±) VOC Common mode output voltage TA = 25°C 247 1.125 Submit Documentation Feedback 400 454 1.375 mV V 5 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 Sample N–1 N+4 N+2 ta N N+1 N+3 tCLKH N+5 tCLKL CLK CLK Latency = 3.5 Clock Cycles tDRY DRY DRY tDATA D[11:0], OVR N N–1 N+1 D[11:0], OVR T0158-01 Figure 1. Timing Diagram TIMING CHARACTERISTICS (1) Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock (unless otherwise noted) PARAMETER ta TEST CONDITIONS MIN MAX UNIT 200 ps Aperture jitter, rms 160 fs Latency 3.5 cycles tCLK Clock period 2 tCLKH Clock pulse duration, high 1 tCLKL Clock pulse duration, low tDRY CLK to DRY delay (2) Zero crossing, 7-pF differential loading 800 1100 1400 ps tDATA CLK to DATA/OVR delay (2) Zero crossing, 7-pF differential loading 600 1100 1600 ps tSKEW DATA to DRY skew tDATA – tDRY, 7-pF differential loading 0 350 ps tRISE DRY/DATA/OVR rise time 7-pF differential loading 500 ps tFALL DRY/DATA/OVR fall time 7-pF differential loading 500 ps (1) (2) 6 TYP Aperture delay 50 ns 1 –350 ns ns Timing parameters are assured by design or characterization, but not production tested. DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation delay. Submit Documentation Feedback ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 PIN CONFIGURATION D4 D5 D4 D5 GND D6 DVDD3 D7 D6 D8 D7 D9 D8 D10 D9 D11 (MSB) D10 DRY D11 (MSB) DRY PFP PACKAGE (TOP VIEW) DVDD3 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 GND 2 59 D3 AVDD5 58 57 D2 NC 3 4 NC 5 56 D1 VREF 6 55 D1 D0 AVDD5 7 8 54 53 D0 GND 9 52 GND CLK 10 CLK 11 GND ADS5463 D3 D2 51 DVDD3 50 NC GND 12 49 NC AVDD5 13 48 NC AVDD5 14 47 NC GND 15 46 NC AIN 16 45 NC AIN 17 44 NC GND 18 43 NC AVDD5 19 42 OVR GND 20 41 OVR GND AVDD3 GND GND AVDD3 GND AVDD3 RESERVED GND GND AVDD5 GND RESERVED GND AVDD5 GND AVDD5 AVDD5 GND AVDD5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0027-02 Submit Documentation Feedback 7 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 PIN CONFIGURATION (continued) Table 1. TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION AIN 16 Differential input signal (positive) AIN 17 Differential input signal (negative) AVDD5 AVDD3 DVDD3 3, 8, 13, 14, 19, 21, Analog power supply (5 V) 23, 25, 27, 31 35, 37, 39 Analog power supply (3.3 V) (Suggestion for ≤250 MSPS: leave option to connect to 5 V for ADS5440/4 compatibility) 1, 51, 66 Output driver power supply (3.3 V) GND 2, 7, 9, 12, 15, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 52, 65 CLK 10 Differential input clock (positive). Conversion is initiated on rising edge. CLK 11 Differential input clock (negative) Ground D0, D0 54, 53 LVDS digital output pair, least-significant bit (LSB) D1–D10, D1–D10 55–64, 67–76 LVDS digital output pairs D11, D11 78, 77 LVDS digital output pair, most-significant bit (MSB) DRY, DRY 80, 79 Data ready LVDS output pair 4, 5, 43–50 No connect (4 and 5 should be left floating, 43–50 are possible future bit additions for this pinout and therefore can be connected to a digital bus or left floating) OVR, OVR 42, 41 Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. RESERVED 29, 33 Pin 29 is reserved for possible future Vcm output for this pinout; pin 33 is reserved for possible future power-down control pin for this pinout. NC VREF 8 NO. 6 Reference voltage Submit Documentation Feedback ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) SPECTRAL PERFORMANCE FFT FOR 30-MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 100-MHz INPUT SIGNAL 0 0 SFDR = 82.4 dBc SINAD = 65.3 dBFS SNR = 65.4 dBFS THD = 79 dBc −20 −40 Amplitude − dB Amplitude − dB −20 SFDR = 80.6 dBc SINAD = 65.1 dBFS SNR = 65.3 dBFS THD = 77.1 dBc −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 125 150 175 200 225 250 0 25 50 Frequency − MHz 75 100 125 150 175 200 225 250 Frequency − MHz G001 G002 Figure 2. Figure 3. SPECTRAL PERFORMANCE FFT FOR 230-MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 300-MHz INPUT SIGNAL 0 0 SFDR = 77.5 dBc SINAD = 64.7 dBFS SNR = 65.2 dBFS THD = 73.7 dBc −20 −40 Amplitude − dB Amplitude − dB −20 SFDR = 77.1 dBc SINAD = 64.5 dBFS SNR = 65 dBFS THD = 73.1 dBc −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 125 150 175 200 225 250 0 25 Frequency − MHz 50 75 100 125 150 175 200 225 250 Frequency − MHz G003 Figure 4. G004 Figure 5. Submit Documentation Feedback 9 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) SPECTRAL PERFORMANCE FFT FOR 450-MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 650-MHz INPUT SIGNAL 0 0 SFDR = 74.3 dBc SINAD = 64.3 dBFS SNR = 64.8 dBFS THD = 73 dBc −20 −40 Amplitude − dB Amplitude − dB −20 SFDR = 65.5 dBc SINAD = 61.8 dBFS SNR = 64 dBFS THD = 64.9 dBc −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 125 150 175 200 225 250 0 25 50 Frequency − MHz 75 100 125 150 175 200 225 250 Frequency − MHz G005 G006 Figure 6. Figure 7. SPECTRAL PERFORMANCE FFT FOR 900-MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 1,300-MHz INPUT SIGNAL 0 0 SFDR = 55.5 dBc SINAD = 55.3 dBFS SNR = 62.8 dBFS THD = 55.1 dBc −20 −40 Amplitude − dB Amplitude − dB −20 SFDR = 45.6 dBc SINAD = 45.1 dBFS SNR = 59.3 dBFS THD = 44.3 dBc −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 125 150 175 200 225 250 0 25 Frequency − MHz 50 75 100 125 150 175 200 225 250 Frequency − MHz G007 Figure 8. 10 G008 Figure 9. Submit Documentation Feedback ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) TWO-TONE INTERMODULATION DISTORTION (FFT FOR 65.1 MHz AND 70.1 MHz AT –7 dBFS) TWO-TONE INTERMODULATION DISTORTION (FFT FOR 65.1 MHz AND 70.1 MHz AT –16 dBFS) 0 0 fIN1 = 65.1 MHz, −7 dBFS fIN2 = 70.1 MHz, −7 dBFS IMD3 = 90.5 dBFS SFDR = 90.3 dBFS −20 −40 Amplitude − dB Amplitude − dB −20 fIN1 = 65.1 MHz, −16 dBFS fIN2 = 70.1 MHz, −16 dBFS IMD3 = 96.1 dBFS SFDR = 88.8 dBFS −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 125 150 175 200 225 250 0 25 50 Frequency − MHz 75 100 125 150 175 200 225 250 Frequency − MHz G009 G010 Figure 10. Figure 11. TWO-TONE INTERMODULATION DISTORTION (FFT FOR 350 MHz AND 355 MHz AT –7 dBFS) TWO-TONE INTERMODULATION DISTORTION (FFT FOR 350 MHz AND 355 MHz AT –16 dBFS) 0 0 fIN1 = 350 MHz, −7 dBFS fIN2 = 355 MHz, −7 dBFS IMD3 = 81.6 dBFS SFDR = 81.6 dBFS −20 −40 Amplitude − dB Amplitude − dB −20 fIN1 = 350 MHz, −16 dBFS fIN2 = 355 MHz, −16 dBFS IMD3 = 101.1 dBFS SFDR = 88.9 dBFS −60 −80 −100 −40 −60 −80 −100 −120 −120 0 25 50 75 100 125 150 175 200 225 250 0 25 Frequency − MHz 50 75 100 125 150 175 200 225 250 Frequency − MHz G011 Figure 12. G012 Figure 13. Submit Documentation Feedback 11 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) FULLSCALE GAIN RESPONSE vs INPUT FREQUENCY DIFFERENTIAL NONLINEARITY 4 0.3 fS = 500 MSPS fIN = 10 MHz 3 0.2 Differential Nonlinearity − LSB Input Amplitude − dB 2 1 0 −1 −2 −3 −4 0.1 0.0 −0.1 −0.2 −5 fS = 500 MSPS AIN= –1 dBFS −6 0 −0.3 200 400 600 800 1000 1200 1400 1600 1800 2000 fIN − Input Frequency − MHz 50 550 1050 1550 2050 2550 3050 3550 4050 Code G013 G014 Figure 14. Figure 15. INTEGRAL NONLINEARITY NOISE HISTOGRAM WITH INPUTS SHORTED 1.0 60 fS = 500 MSPS fIN = 10 MHz 55 fS = 500 MSPS 50 0.6 45 0.4 Percentage − % INL − Integral Nonlinearity − LSB 0.8 0.2 0.0 −0.2 −0.4 40 35 30 25 20 15 −0.6 10 −0.8 5 −1.0 0 50 550 1050 1550 2050 2550 3050 3550 4050 2050 Code G015 Figure 16. 12 2049 2048 2046 G016 Figure 17. Submit Documentation Feedback 2047 Code Number ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) AC PERFORMANCE vs INPUT AMPLITUDE (100-MHz INPUT SIGNAL) AC PERFORMANCE vs INPUT AMPLITUDE (300-MHz INPUT SIGNAL) 120 SFDR (dBFS) AC Performance − dB 80 80 SNR (dBFS) 60 40 SFDR (dBc) 20 0 SNR (dBc) −20 SNR (dBFS) 60 40 SFDR (dBc) 20 0 SNR (dBc) −20 −40 −60 −120 SFDR (dBFS) 100 AC Performance − dB 100 120 −40 fS = 500 MSPS fIN = 100.3 MHz −100 −80 −60 −40 −20 fS = 500 MSPS fIN = 301.1 MHz −60 −120 0 −100 Input Amplitude − dBFS −80 −60 −40 −20 G017 G018 Figure 18. Figure 19. AC PERFORMANCE vs INPUT AMPLITUDE (350-MHz AND 355-MHz TWO-TONE INPUT SIGNAL) SFDR vs CLOCK DUTY CYCLE 85 SFDR − Spurious-Free Dynamic Range − dBc 100 80 Worst Spur (dBFS) AC Performance − dB SNR (dBFS) 60 Worst Spur (dBc) 40 20 SNR (dBc) 0 −20 −80 0 Input Amplitude − dBFS fS = 500 MSPS fIN1 = 350 MHz fIN2 = 355 MHz fIN = 100 MHz 80 75 fIN = 300 MHz 70 65 60 55 fS = 500 MSPS 50 −70 −60 −50 −40 −30 −20 −10 20 0 30 40 50 60 70 80 Duty Cycle − % Input Amplitude − dBFS G021 G020 Figure 20. Figure 21. Submit Documentation Feedback 13 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) SFDR vs CLOCK LEVEL SNR vs CLOCK LEVEL 66.0 79 fIN = 100 MHz SNR − Signal-to-Noise Ratio − dBFS SFDR − Spurious-Free Dynamic Range − dBc 80 78 77 fIN = 300 MHz 76 75 74 73 72 65.0 fIN = 300 MHz 64.5 64.0 63.5 63.0 fS = 500 MSPS fS = 500 MSPS 62.5 71 0 1 2 3 4 0 5 Clock Amplitude − VP−P 1 2 3 G022 Figure 22. Figure 23. SFDR vs CLOCK COMMON MODE SNR vs CLOCK COMMON MODE 5 G023 66 SNR − Signal-to-Noise Ratio − dBFS fIN = 100 MHz fIN = 100 MHz 80 fIN = 300 MHz 75 70 65 65 fIN = 300 MHz 64 63 62 61 fS = 500 MSPS fS = 500 MSPS 60 60 0 1 2 3 4 5 0 Clock Common Mode − V 1 2 3 4 5 Clock Common Mode − V G025 G024 Figure 24. 14 4 Clock Amplitude − VP−P 85 SFDR − Spurious-Free Dynamic Range − dBc fIN = 100 MHz 65.5 Figure 25. Submit Documentation Feedback ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) SFDR vs AVDD5 ACROSS TEMPERATURE SNR vs AVDD5 ACROSS TEMPERATURE 67.0 SNR − Signal-to-Noise Ratio − dBFS SFDR − Spurious-Free Dynamic Range − dBc 80 75 70 TA = 05C TA = 405C 65 TA = 655C TA = 255C TA = −405C 60 TA = 855C 55 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 AVDD − Supply Voltage − V TA = 255C TA = 405C 65.0 64.5 TA = 655C 64.0 TA = 855C TA = 1005C AVDD − Supply Voltage − V G026 G027 Figure 27. SFDR vs AVDD3 ACROSS TEMPERATURE SNR vs AVDD3 ACROSS TEMPERATURE 66.5 TA = 255C SNR − Signal-to-Noise Ratio − dBFS SFDR − Spurious-Free Dynamic Range − dBc 65.5 Figure 26. TA = 405C 78 TA = 05C 76 TA = 655C 74 TA = 855C TA = 1005C 70 TA = −405C 68 2.7 TA = 05C 63.0 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 80 72 TA = −405C 66.0 63.5 fS = 500 MSPS fIN= 100 MHz TA = 1005C 66.5 fS = 500 MSPS fIN= 100 MHz 2.9 fS = 500 MSPS fIN= 100 MHz 3.1 3.3 AVDD − Supply Voltage − V 3.5 66.0 TA = −405C TA = 05C 65.5 TA = 255C TA = 405C 65.0 TA = 655C 64.5 TA = 855C 64.0 fS = 500 MSPS fIN= 100 MHz 3.7 63.5 2.7 G028 Figure 28. 2.9 TA = 1005C 3.1 3.3 AVDD − Supply Voltage − V 3.5 3.7 G029 Figure 29. Submit Documentation Feedback 15 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) SFDR vs DVDD3 ACROSS TEMPERATURE SNR vs DVDD3 ACROSS TEMPERATURE 66.5 TA = 255C SNR − Signal-to-Noise Ratio − dBFS SFDR − Spurious-Free Dynamic Range − dBc 80 78 TA = 405C TA = 05C 76 TA = 655C 74 TA = 855C 72 TA = −405C 70 TA = 1005C 66.0 TA = −405C TA = 05C 65.5 TA = 255C TA = 405C 65.0 TA = 655C 64.5 TA = 855C 64.0 fS = 500 MSPS fIN= 100 MHz 68 2.7 2.9 3.1 3.3 3.5 DVDD − Supply Voltage − V TA = 1005C 63.5 2.7 3.7 2.9 3.1 3.3 3.7 G030 Figure 30. Figure 31. PSRR vs SUPPLY INJECTED FREQUENCY CMRR vs COMMON-MODE INPUT FREQUENCY G031 CMRR − Common-Mode Rejection Ratio − dB 100 AVDD3 90 80 AVDD5 70 60 50 fS = 500 MSPS fIN= None 40 0.01 0.1 1 10 100 90 fS = 500 MSPS 80 70 60 50 40 30 20 10 0 0.1 Frequency − MHz 1 10 100 1000 Common-Mode Input Frequency − MHz G032 Figure 32. 16 3.5 DVDD − Supply Voltage − V 100 PSRR − Power Supply Rejection Ratio − dB fS = 500 MSPS fIN= 100 MHz G033 Figure 33. Submit Documentation Feedback ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, (unless otherwise noted) SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY 550 63 64 64 65 61 62 63 fS - Sampling Frequency - MHz 500 65 450 64 400 63 62 350 300 65 64 63 62 250 61 200 58 59 65 170 10 100 300 200 400 500 600 700 800 900 1000 64 65 66 67 fIN - Input Frequency - MHz 58 57 61 60 59 62 63 SNR - dBFS M0048-09 Figure 34. SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY 550 70 75 80 500 fS - Sampling Frequency - MHz 60 75 55 65 80 80 450 400 70 75 65 80 350 55 60 80 300 85 250 60 200 170 10 70 75 85 80 100 300 200 55 65 400 500 600 700 800 900 1000 fIN - Input Frequency - MHz 45 50 55 60 65 70 SFDR - dBc 75 80 85 90 M0048-10 Figure 35. Submit Documentation Feedback 17 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 APPLICATION INFORMATION Theory of Operation The ADS5463 is a 12-bit, 500-MSPS, monolithic-pipeline, analog-to-digital converter. Its bipolar analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel word, coded in offset binary format. Input Configuration The analog input for the ADS5463 consists of an analog pseudodifferential buffer followed by a bipolar transistor track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching. The input common mode is set internally through a 500-Ω resistor connected from 2.4 V to each of the inputs. This results in a differential input impedance of 1 kΩ. For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings symmetrically between 2.4 V + 0.55 V and 2.4 V – 0.55 V. This means that each input has a maximum signal swing of 1.1 Vpp for a total differential input signal swing of 2.2 Vpp. The maximum swing is determined by the internal reference voltage generator, eliminating the need for any external circuitry for this purpose. The ADS5463 obtains optimum performance when the analog inputs are driven differentially. The circuit in Figure 36 shows one possible configuration using an RF transformer with termination either on the primary or on the secondary of the transformer. In addition, the evaluation module is configured with two back-to-back transformers, which also demonstrates good performance. If voltage gain is required, a step-up transformer can be used. Besides the transformer configurations, Texas Instruments offers a wide selection of single-ended operational amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as Texas Instruments' THS9001, can also be used for high-input-frequency applications. For large voltage gains at intermediate-frequencies in the 50-MHz–500-MHz range, the configuration shown in Figure 37 can be used. The component values can be tuned for different intermediate frequencies. The example shown is located on the evaluation module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found in the ADS5463 EVM User Guide (SLAU194) and the THS9001 50 MHz to 350 MHz Cascadeable Amplifier data sheet (SLOS426). R0 50 W Z0 50 W AIN R 200 W AC Signal Source Mini-Circuits JTX-4-10T ADS5463 AIN S0176-03 Figure 36. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer 18 Submit Documentation Feedback ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 Application Information (continued) 1000 pF VIN 1000 pF AIN THS9001 50 W 18 mH 39 pF ADS5463 50 W VIN 0.1 mF AIN THS9001 1000 pF 1000 pF S0177-03 Figure 37. Using the THS9001 IF Amplifier With the ADS5463 From 50 W Source VIN 100 W 78.9 W 348 W +5V 49.9 W 0.22 mF 100 W AIN THS4509 ADS5463 49.9 W 18 pF AIN VREF CM 49.9 W 0.22 mF 78.9 W 49.9 W 0.22 mF 0.1 mF 0.1 mF 348 W S0193-02 Figure 38. Using the THS4509 With the ADS5463 For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like the THS4509 (see Figure 38) is a good solution, as it minimizes board space and reduces the number of components. In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5463. The 50-Ω resistors and 18-pF capacitor between the THS4509 outputs and ADS5463 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB). Input termination is accomplished via the 78.9-Ω resistor and 0.22-µF capacitor to ground, in conjunction with the input impedance of the amplifier circuit. A 0.22-µF capacitor and 49.9-Ω resistor are inserted to ground across the 78.9-Ω resistor and 0.22-µF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. See the THS4509 data sheet for further component values to set proper 50-Ω termination for other common gains. Because the ADS5463 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single power supply input with V S+ = 5 V and V S– = 0 V (ground). This maintains maximum headroom on the internal transistors of the THS4509. Clock Inputs The ADS5463 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. In low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock (see Figure 39) could save some cost and board space without any trade-off in performance. When clocked with this configuration, it is best to connect CLK to ground with a 0.01-µF capacitor, while CLK is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in Figure 39. Submit Documentation Feedback 19 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 Application Information (continued) Square Wave or Sine Wave CLK 0.01 mF ADS5463 CLK 0.01 mF S0168-05 Figure 39. Single-Ended Clock 0.1 mF Clock Source CLK ADS5463 CLK S0194-02 Figure 40. Differential Clock For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) at the system level. The differential clock allows for common-mode noise rejection at the PCB level. With a differential clock, the signal-to-noise ratio of the ADC is better for high intermediate frequency applications because the board clock jitter is superior. A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise on jitter. Figure 40 shows this approach. See Clocking High Speed Data Converters (SLYT075) for more details. The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking, the ADS5463 features good tolerance to clock common-mode variation (see Figure 24 and Figure 25). Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. Digital Outputs The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal (DRY), and an overrange indicator (OVR) that equals a logic high when the output reaches the full-scale limits. The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the ADS5463. DRY is source-synchronous to the DATA/OVR bits and operates at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges of DRY. The ADS5463 digital outputs are LVDS-compatible. Due to the high data rates, care should be taken not to overload the digital outputs with too much capacitance, which shortens the data-valid timing window. The values given for timing were obtained with a measured 14-pF parasitic board capacitance to ground on each LVDS line (or 7-pF differential parasitic capacitance). 20 Submit Documentation Feedback ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 Application Information (continued) Power Supplies The use of low-noise power supplies with adequate decoupling is recommended. Linear supplies are the preferred choice versus switched ones, which tend to generate more noise components that can be coupled to the ADS5463. The ADS5463 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V AVDD is used, while the digital portion uses a 3.3-V supply (DVDD). All the ground pins are marked as GND, although analog and digital grounds are not tied together inside the package. The PSRR value and plot given were obtained by calibrating out the effect of the supply decoupling capacitors. With the decoupling capacitors in place, the board-level PSRR is actually much higher than the stated value for the ADC. Layout Information The evaluation board represents a good guideline of how to lay out the board to obtain the maximum performance from the ADS5463. General design rules, such as the use of multilayer boards, single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications where low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when considering the heat dissipation of the device. The thermal heat sink should be soldered to the board as described in the PowerPad Package section. See ADS5463 EVM User Guide (SLAU194) on the TI Web site for the evaluation board schematic. PowerPAD Package The PowerPAD package is a thermally enhanced standard-size IC package designed to eliminate the use of bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard repair procedures. The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a heatsink. Assembly Process 1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in the Mechanical Data section. 2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The small size prevents wicking of the solder through the holes. 3. It is recommended to place a small number of 25-mil-diameter holes under the package, but outside the thermal pad area, to provide an additional heat path. 4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a ground plane). 5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground plane. The spoke pattern increases the thermal resistance to the ground plane. 6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area. 7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking. 8. Apply solder paste to the exposed thermal pad area and all of the package terminals. For more detailed information regarding the PowerPAD package and its thermal properties, see either the PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application report (SLMA002). Submit Documentation Feedback 21 ADS5463 www.ti.com SLAS515 – NOVEMBER 2006 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay Clock Pulse Duration/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse duration) to the period of the clock signal, expressed as a percentage. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSB. Common-Mode Rejection Ratio (CMRR) CMRR measures the ability to reject signals that are presented to both analog inputs simultaneously. The injected common-mode frequency level is translated into dBFS, the spur in the output FFT is measured in dBFS, and the difference is the CMRR in dB. Effective Number of Bits (ENOB) ENOB is a measure in units of bits of a converter's performance as compared to the theoretical limit based on quantization noise ENOB = (SINAD – 1.76)/6.02 Gain Error Gain error is the deviation of the ADC actual input full-scale range from its ideal value, given as a percentage of the ideal input full-scale range. Integral Nonlinearity (INL) INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares curve fit of that transfer function. The INL at each analog input value is the difference between the actual transfer function and this best-fit line, measured in units of LSB. Offset Error Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode. Power-Supply Rejection Ratio (PSRR) 22 PSRR is a measure of the ability to reject frequencies present on the power supply. The injected frequency level is translated into dBFS, the spur in the output FFT is measured in dBFS, and the difference is the PSRR in dB. The measurement calibrates out the benefit of the board supply decoupling capacitors. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and in the first five harmonics. P SNR + 10log 10 S PN (2) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10log 10 PN ) PD (3) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at the nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters over the whole temperature range divided by TMIN – TMAX. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD). P THD + 10log 10 S PD (4) THD is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion (IMD3) IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2– f1). IMD3 is given in units of either dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 18-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS5463IPFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5463IPFPG4 ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5463IPFPR ACTIVE HTQFP PFP 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5463IPFPRG4 ACTIVE HTQFP PFP 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device ADS5463IPFPR 17-May-2007 Package Pins PFP 80 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) TAI 330 24 15.0 15.0 1.5 20 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) ADS5463IPFPR PFP 80 TAI 341.0 159.0 123.5 Pack Materials-Page 2 W Pin1 (mm) Quadrant 24 PKGORN T2TR-MS P IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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