AKM AK2573AVB

ASAHI KASEI
[AK2573A]
AK2573A
125M / 156M Laser Diode Driver + APC
Features
- 1 chip 125M / 156M Laser Diode Driver (LDD) +
Digital APC (APC_FF and APC_FB)
- Programmable laser BIAS and modulation current
controlled by an on-chip temperature sensor
(APC_FF)
- Digital feedback circuit for APC (APC FB)
- Two current output 8 bit DACs,
I-DAC1: 85mA sink for modulation current
I-DAC2: 54mA sink for BIAS current
- TXFAULT detection and 1kbit ID Field (EEPROM)
for SFP (Small Form-factor Pluggable) support
- I2CTM compatible digital I/F
- Duty adjustment
- Power failure alarm (OPTALM), Over current alarm
(CURRALM), Temperature alarm (TEMPALM),
Data alarm (DATAALM) and TXFAULT for failure
alarm
- BIAS and modulation current monitors (* 0.0095)
- Single 3.3V +/- 0.2V operation
Description
The AK2573A is a 1chip LDD (Laser Diode Driver) and
an APC (Auto Power Control) for laser direct
modulation application. It contains up to 156M LDD,
programmable duty adjustment, BIAS and modulation
currents, a digital feedback circuit, BIAS and
modulation current monitors, failure alarms, I2CTM
interface, an EEPROM for storing LD characteristics
and user information, and TXFAULT detection for SFP
application. The AK2573A has two APC functions;
APC FF (Feed-forward) and APC FB (Feedback). APC
FF supplies a programmed current in response to the
temperature. APC FB provides a stable auto power
control function with an internal digital feedback
algorithm.
All program and operational functions can be set
through the I2CTM compatible interface and stored in the
on-chip EEPROM.
Ordering Information
Product Number
AK2573AVB
Applications
STM-1 / OC-3 (156Mbps) Optical Interface Module
TS–1000 (125Mbps) Optical Interface Module
PKG
BCC++ 48 (7mm * 7mm)
I2CTM is a trademark o f Philips Corporation.
Block Diagram
SEL
DATAP
DATA
(LVPECL)
CLKP
CLK
(LVPECL)
CLKN
IMODN
Selecter
DATAN
FF
DUTY_
ADJ
DRIVER
LD
IMOD
Imod
OSC
I-DAC1
TEMPSENS
ADC
EEPROM
MODMON
* 0.0095
APC
Ibias
I-DAC2
TEMPMON
IBIAS
* 0.0095
BIASMON
DATAALM
PDMON
Monitor
PD
OPTALM
ALM
PDGAIN
RPD
TXFAULT*
CPD
Digital I/F
BIAS
SHUTDOWN
CONTROL
BIAS_GEN
RB (12k)
SCL SDA*
<MS0189-E-01>
CURRALM
TEMPALM
PDIN
TXDIS1
TXDIS2
*: Open Drain
WP**
**: Pull-up
-1-
2004/5
ASAHI KASEI
[AK2573A]
- Contents -
Ⅰ. Pin Description ･･･････････････････････････････････････････････････････････････････････････････････ 4
Ⅱ. Absolute Maximum Rating･････････････････････････････････････････････････････････････････････････ 6
Ⅲ. Recommend Operation Conditions ･･････････････････････････････････････････････････････････････････ 6
Ⅳ. Electrical Cghracteristics ･･･････････････････････････････････････････････････････････････････････････ 6
1. Power Consumption ･････････････････････････････････････････････････････････････････････････ 6
2. EEPROM･･･････････････････････････････････････････････････････････････････････････････････････ 6
3. Digital Input / Output DC Characteristics ････････････････････････････････････････････ 7
4. I2CTM I/F AC Character･････････････････････････････････････････････････････････････････････ 7
5. LVPECL I/F･･････････････････････････････････････････････････････････････････････････････････ 7
6. I-DAC1･･･････････････････････････････････････････････････････････････････････････････････････ 8
7. I-DAC2･･･････････････････････････････････････････････････････････････････････････････････････ 8
8. Duty Cycle Adjustment ････････････････････････････････････････････････････････････････････ 8
9. Current Monitor････････････････････････････････････････････････････････････････････････････ 8
10. PDGAIN･･･････････････････････････････････････････････････････････････････････････････････････ 9
11. DACAPC･･･････････････････････････････････････････････････････････････････････････････････････ 9
12. BIASGEN ･････････････････････････････････････････････････････････････････････････････････････ 9
13. Temperature Sensor ････････････････････････････････････････････････････････････････････････ 9
14. ADC ･･････････････････････････････････････････････････････････････････････････････････････････ 9
15. Power On Reset･････････････････････････････････････････････････････････････････････････････ 9
16. On-chip Oscillator ････････････････････････････････････････････････････････････････････････ 9
17. OPTALM Detect Level･･･････････････････････････････････････････････････････････････････････ 9
18. TXDIS Release Time ････････････････････････････････････････････････････････････････････････ 9
Ⅴ. Package Information ･････････････････････････････････････････････････････････････････････････････ 10
Ⅵ. Circuit Description ･･･････････････････････････････････････････････････････････････････････････････ 11
1. Parameter Nortation･･････････････････････････････････････････････････････････････････････ 11
1.1 Parameter Definition ････････････････････････････････････････････････････････････････ 11
1.2 Operation Overview ･･････････････････････････････････････････････････････････････････ 11
2. Driver･･････････････････････････････････････････････････････････････････････････････････････ 12
3. DATA/CLK I/F (LVPECL) ･･･････････････････････････････････････････････････････････････････ 12
3.1 LVPECL Input (DATAP/DATAN/CLKP/CLKN)･････････････････････････････････････････････ 13
3.2 Duty Adjustment ･･････････････････････････････････････････････････････････････････････ 14
4. APC ･････････････････････････････････････････････････････････････････････････････････････････ 14
4.1 APC_FF Function ･･････････････････････････････････････････････････････････････････････ 15
4.2 APC_FB Function ･･････････････････････････････････････････････････････････････････････ 15
4.2.1 PDGAIN ･･･････････････････････････････････････････････････････････････････････････ 16
4.2.2 DACAPC ･･･････････････････････････････････････････････････････････････････････････ 16
4.2.3 Example of APC Setting ････････････････････････････････････････････････････････ 16
4.3 Temperature Sensor (TEMPSENS) ･････････････････････････････････････････････････････ 20
4.4 Current Monitor ･･････････････････････････････････････････････････････････････････････ 21
5. Alarm･･･････････････････････････････････････････････････････････････････････････････････････ 22
5.1 OPTALM ･････････････････････････････････････････････････････････････････････････････････ 22
5.2 CURRALM････････････････････････････････････････････････････････････････････････････････ 22
5.3 TEMPALM････････････････････････････････････････････････････････････････････････････････ 22
5.4 DATAALM････････････････････････････････････････････････････････････････････････････････ 22
5.5 TXFAULT････････････････････････････････････････････････････････････････････････････････ 22
6. Shutdown ･･･････････････････････････････････････････････････････････････････････････････････ 23
6.1 Shutdown Operation ･･････････････････････････････････････････････････････････････････ 23
<MS0189-E-01>
-2-
2004/5
ASAHI KASEI
[AK2573A]
6.2 Temperature Compensation between Shutdown Request and Release ･･････････････ 23
7. Power-up/down Timing･････････････････････････････････････････････････････････････････････ 24
7.1 Delay Time of TXFAULT Detection with OPTALM ････････････････････････････････････ 24
7.2 Power on Initialization Procedure without Shutdown Request (TXDIS=L)･･････ 25
7.3 Power on Initialization Procedure with Shutdown Request (TXDIS=H) ･････････ 25
7.4 TXDIS Timing during Normal Operation･････････････････････････････････････････････ 26
7.5 TXFAULT Detection / Reset with Recovery ･････････････････････････････････････････ 26
7.6 TXFAULT Detection / Reset without Recovery ･････････････････････････････････････ 27
8. I2CTM I/F ･･･････････････････････････････････････････････････････････････････････････････････ 28
8.1 Memory Map ････････････････････････････････････････････････････････････････････････････ 28
8.2 Read / Write Operation･･････････････････････････････････････････････････････････････ 29
8.2.1 Byte Write ･･････････････････････････････････････････････････････････････････････ 29
8.2.2 Page Write ･･････････････････････････････････････････････････････････････････････ 29
8.2.3 Current Address Read ･･････････････････････････････････････････････････････････ 29
8.2.4 Random Read ･････････････････････････････････････････････････････････････････････ 29
8.2.5 Sequential Read ････････････････････････････････････････････････････････････････ 29
8.2.6 Data Change ･････････････････････････････････････････････････････････････････････ 30
8.2.7 Start / Stop Condition ････････････････････････････････････････････････････････ 30
8.3 EEPROM ･････････････････････････････････････････････････････････････････････････････････ 31
8.4 Register･･･････････････････････････････････････････････････････････････････････････････ 33
9. Operation Mode････････････････････････････････････････････････････････････････････････････ 35
9.1 Self-running Mode････････････････････････････････････････････････････････････････････ 35
9.2 Adjustment Mode ･･････････････････････････････････････････････････････････････････････ 35
9.3 EEPROM Mode ･･･････････････････････････････････････････････････････････････････････････ 35
9.4 MODE Control･･････････････････････････････････････････････････････････････････････････ 35
9.5 Operation Mode Protection ･･････････････････････････････････････････････････････････ 35
10. Module Adjustment Example ･･････････････････････････････････････････････････････････････ 36
Ⅶ. Circuit Example ･････････････････････････････････････････････････････････････････････････････････ 37
<MS0189-E-01>
-3-
2004/5
ASAHI KASEI
[AK2573A]
Ⅰ. Pin Description
The symbol of I/O row shows below.
Ai: Analog input, Ai_l: LVPECL input, Ao: Analog output
Di: Digital input, Di_pu: Digital input with pulled-up resistor, Do: Digital output, Dio: Digital input / output,
Do_od: Digital output (open drain), Dio_od: Didital input / output (open drain)
PWR: Power or VSS
PIN#
1
2
3
4
Symbol
NC
DATAP
DATAN
SEL
Function
No Connection. Connect to the VSS or leave open.
Positive LVPECL data input. Input Inpedance >= 10kΩ
Negative LVPECL data input. Input Indedance >= 10kΩ
“H” for latched data with clock. “L” for direct data.
5
6
CLKP
CLKN
Ai_l
Ai_l
7
WP
8
TXDIS1
9
TXDIS2
10
11
DVDD
TXFAULT
12
13
NC
SDA
Positive LVPECL clock input. Connect to VSS when SEL =“L”.
Negative LVPECL clock input. Connect to VDD or leave open
when SEL = “L”.
Write Protect. Internally pulled-up with 20kΩ (typ).
“H” sets device address 101000 and only user area of EEPROM
can access as read-only. “L” sets device address as 1010 and full
of EEPROM can access as read/write. For more information, see
Table 8-2 and 9-1.
TX Disable.
“H” for disable MOD and BIAS current. TXDIS1 and TXDIS2
are ORed internally. Use 4.7kΩ or more for externally pulled-up
or pulled-down.
Power supply for digital circuit.
TX Fault detection output (Open drain). Connect to VDD with
4.7kΩ to 10kΩ resistor.
Set “H” when detect TEMPALM, CURRALM, OPTALM or
DATAALM.
When set RE_SFP=1 and detect the ALM, TXFAULT is kept
“H” until receiving disable request at TXDIS1 or TXDIS2.
No Connection. Connect to the VSS or leave open.
Serial data input / output (Open drain). Connect to VDD with
4.7k to 10k resistor.
14
SCL
Di
15
16
17
DVSS
NC
DATAALM
18
OPTALM
19
CURRALM
Serial clock input. The data (SDA) is shifted in at the rising edge
of SCL and is shifted out at the falling edge of SCL.
VSS for digital circuit.
No Connection. Connect to the VSS or leave open.
Sets the alarm when detects 1’s or 0’s sequential data input. The
detection time is 4.5us (typ).
The polarity can be set with EEPROM.
Sets the alarm when detects monitor PD current drop.
The polarity can be set with EEPROM.
Sets the alarm when detects the over current of I-DAC1 or
I-DAC2.
Alarm level can be set every 6℃.
The polarity can be set with EEPROM.
<MS0189-E-01>
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I/O
Ai_l
Ai_l
Di
Remark
Do not
leave open
Di_pu
Di
PWR
Do_od
Dio_od
Do not
leave open
AC load
≤ 100pF
AC Load
≤ 100pF
Do not
leave open
Do not
leave open
PWR
Do
AC Load
≤ 30pF
Do
AC Load
≤ 30pF
AC Load
≤ 30pF
Do
2004/5
ASAHI KASEI
[AK2573A]
Pin Description (Continued)
PIN# Symbol
Function
20
TEMPALM Sets the alarm when detects the over temperature.
The polarity can be set with EEPROM.
21
TEMPMON Temperature sensor monitor output.
22
BIAS
23
PDMON
24
25
AVSS
AVDD
26
PDIN
27
28
29
VSSBI
IBIAS
30
31
32
33
VSSBI
VSSMD
IMOD
34
35
36
37
38
39
40
41
IMODN
42
MODMON
43
44
45
46
47
48
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
VSSMD
VDDMD
NC
VDDDR
VSSDR
BIASMON
I/O
Do
Ao
BIAS reference for internal circuit. Connect to VSS with 12k +/- Ao
1% resistor.
PDIN regulated output. Adjust PDGAIN to PDMON = 1V Ao
(typ).
VSS for analog circuit.
Power supply for analog circuit. Connect to the power supply
through R-C LPF (R=10Ω, C=1uF is recommended).
Monitor PD voltage input. Monitor PD current is converted to
the voltage with resistor and capacitor that has 1kHz to 10kHz
cut-off frequency.
VSS for BIAS current drive circuit.
BIAS current output. Sinks up to 54mA (typ) current.
BIAS current is adjusted with I-DAC2.
IBIAS voltage should be (VDD – 1.8V) or more.
VSS for BIAS current drive circuit.
VSS for MOD current drive circuit.
Positive MOD current output.
Sinks up to 85mA (typ) MOD current when input data is “H”.
MOD current is adjusted with I-DAC1.
IMOD voltage should be (VDD – 1.8V) or more.
Negative MOD current output.
Sinks MOD current when input data is “L”.
VSS for MOD current drive circuit.
Power supply for MOD current circuit.
No Connection. Connect to the VSS or leave open
Power supply for MOD driver circuit.
VSS for MOD driver circuit.
BIAS monitor current output.
Sources 0.0095 times current of I-DAC2 (BIAS) current.
BIASMON voltage should be 1.3V or less.
MOD Monitor current output.
Sources 0.0095 times current of I-DAC1 (modulation) current.
BIASMON voltage should be 1.3V or less.
Test input. Connect to VSS for normal operation
Test input. Connect to VSS for normal operation
Test input. Connect to VSS for normal operation
Test input. Connect to VSS for normal operation
Test input. Connect to VSS for normal operation
Test input. Leave open for normal operation.
Remark
AC Load
≤ 30pF
AC load
≤ 30pF
DC load
≥ 50kΩ
AC load
≤ 30pF
DC load
≥ 50kΩ
PWR
PWR
Ai
PWR
Ao
PWR
PWR
Ao
Ao
PWR
PWR
PWR
PWR
Ao
Ao
Di
Di
Di
Di
Di
Do
Connect to
VSS.
Leave open
Center PAD of PKG should be connected to the VSS for good electrical performance and radiation of heat.
<MS0189-E-01>
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2004/5
ASAHI KASEI
[AK2573A]
Ⅱ. Absolute Maximum Rating
Item
Symbol
Min
Max
Unit
Supply Voltage
VDD
-0.3
6.0
V
GND
VSS
0.0
0.0
V
Input voltage
VIN
-0.3
VDD + 0.3
V
Input Current
IIN
-10
10
mA
Storage Temperature
TSTG
-55
130
°C
Stress beyond “Absolute Maximum Range” may cause permanent damage to the device.
Note 1: Except Data retention. Data retention is prescribed at section-Ⅳ (2) EEPROM.
Remarks
Reference Voltage
Except VDD
Except VDD
Note 1
Ⅲ. Recommended Operation Conditions
Item
Operating Ambient
Power Supply
Symbol
Ta1
VDD1
VDD2
VSS
Min
-40
3.1
3.0
0.0
Typ
Max
85
3.5
3.5
0.0
3.3
3.3
0.0
Unit
°C
V
V
V
Remarks
Except AVDD
AVDD
ReferenceVoltage
Ⅳ. Electrical Characteristics
1. Power Consumption
Item
Symbol
min
typ
max
Unit
Remarks
Supply Current 1 (All VDD)
IDD1
7.8
9.4
mA Note 1, 2, 3
Supply Current 2 (All VDD)
IDD2
15
20
mA Note 1, 2, 4
Supply Current 3 (AVDD only)
IDD3
5
mA Note 1, 5
Note 1: without BIAS and modulation current
Note 2: I-DAC1 = 0, I-DAC2 = 0, Gain = 1, PDGAIN = 0dB, PDIN = 1V
Note 3: DATAP = CLKP = “L”, DATAN =CLKN = “H”
Note 4: 155.52Mbps, PN7
Note 5: I-DAC1 = I-DAC2 = FFh (Full code), Gain = 1, PDGAIN = 0dB, PDIN = 1V
2. EEPROM
Item
Endurance
Data retention
min
10000
10
max
-
Unit
Remarks
Write Cycle Note 1
Year
Junction Temperature = 85℃
Note 1: This parameter is characterized and is not 100% tested.
Important Notice: The AKM factory adjusted data are stored in advance at address location (Device Address = A6h,
Address = 60h) for the offset of the on-chip temperature sensor. If such excess temperature stress is to be applied to
the AK2573A which exceeds a guaranteed EEPROM data retention conditions (for 10 years at 85C), it is important to
read the pre-determined value in advamce and to re-write the same data back into EEPROM after an exposure to the
excess temperature environment. Even if the exposure time is shorter than the retention time, any accelerated
temperature stress tests (such as baking) are performed, it is recommended to read the pre-set data first and to
re-write it after the test. Access to un-used address locations is not functionally guaranteed.
Refer to section-Ⅵ 8.3 for EEPROM map.
<MS0189-E-01>
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2004/5
ASAHI KASEI
[AK2573A]
3. Digital Input / Output DC Characteristics
Item
Symbol
min
Input High Level
VIH
2.0
Input Low Level
VIL
Output High Level
VOH
0.9VDD
Output Low Level
VOL
max
0.4
Unit
V
V
V
V
10
350
uA
uA
0.8
Input Leakage Current 1
IL1
Input Leakage Current 2
IL2
Note 1: except DATAP, DATAN, CLKP and CLKN pins.
Note 2: SDA and TXFAULT pins
Note 3: except SDA and TXFAULT pins
I2CTM I/F AC Characteristics
Symbol
Parameter
min
tSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
4.7
thigh
Clock Pulse Width High
4.0
tI
Noise Suppression Time
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time Before a New Transmission
4.7
tHD.STA
Start Hold Time
4.7
tSU.STA
Start Setup Time
4.0
tHD.DAT Data Hold Time
0
tSU.DAT
Data Setup Time
200
tR
Input Rise Time
tF
Input Fall Time
tSU.STO
Stop Setup Time
4.7
tDH
SDATA Hold Time
100
tWR
Write Cycle Time
Note 1: This parameter is characterized and is not 100% tested.
Conditions
Note 1
IOH = -0.2mA
IOL = 1mA (Note 2)
IOL = 0.2mA (Note 3)
except WP pin
WP pin
4.
tF
max
100
100
4.5
1.0
0.3
10
Unit
kHz
us
us
ns
us
us
us
us
us
ns
us
us
us
ns
ms
Remark
Note 1
Note 1
tR
SCL
tSU.STA
tHD.DAT tSU.DAT tSU.STO
tHD.STA
SDA (IN)
tBUF
tAA
tDH
SDA (OUT)
5. LVPECL I/F
Item
Symbol
min
typ
Single-ended Input Voltage Swing Vamp
0.1
Common Voltage
Vcom 0.5*VDD
BIAS Voltage
Vbias
0.6*VDD
Input Impedance
Zin
10
Set-up Time
tsu
1.5
Hold Time
th
1.5
Note 1: This parameter is characterized and is not 100% tested.
<MS0189-E-01>
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max
1.2
VDD – 1.0
Unit
V
V
V
kΩ
ns
ns
Remarks
SEL=”H”
Note 1
2004/5
ASAHI KASEI
[AK2573A]
Vamp
DATA
(DATAP - DATAN)
Vcom
CLKP/CLKN
DATAP/DATAN
tsu
th
CLK
(CLKP - CLKN)
6. I-DAC1
Item
Resolution
Output Current with
Full Code 1
Output Current with
Full Code 2
Current Supply with
Shutdown
1 LSB Current Step 1
1 LSB Current Step 2
DNL
7. I-DAC2
Item
Resolution
Output Current with
Full Code 1
Output Current with
Full Code 2
Current Supply with
Shutdown
1 LSB Current Step 1
1 LSB Current Step 2
DNL
Condition
min
max
76
typ
8
85
94
Unit Remark
bit
mA RE_DAC1_GAIN = 1
IMOD = 1.3V
IMOD = 1.3V
38
43
50
mA
RE_DAC1_GAIN = 0
100
uA
TXDISx = “H”
+1
mA RE_DAC1_GAIN = 1
mA RE_DAC1_GAIN = 0
LSB Code 20h to FFh
IMOD = VDD
IMOD = 1.3V
IMOD = 1.3V
IMOD = 1.3V
0.333
0.169
-1
Condition
min
IMOD = 1.3V
IMOD = 1.3V
max
48
typ
8
54
60
Unit Remark
bit
mA RE_DAC2_GAIN = 1
24
27
30
mA
RE_DAC2_GAIN = 0
100
uA
TXDISx = “H”
+1
mA RE_DAC2_GAIN = 1
mA RE_DAC2_GAIN = 0
LSB Code 20h to FFh
IMOD = VDD
IMOD = 1.3V
IMOD = 1.3V
IMOD = 1.3V
8. Duty Cycle Adjustment
Item
Maximum Pulse Extended
1 LSB Pulse Extended Step
Pulse Extended Stability
min
0.5
0.212
0.106
-1
typ
max
0.03
0.2
Unit
ns
ns
ns
Remarks
Note 1
32 Steps
Ta=-40 to 85℃, VDDDR=3.1～3.5V,
0.3ns Extended (Note 1)
Note 1: This parameter is characterized and is not 100% tested.
9. Current Monitor
Item
Condition
MODMON to
MODMON = 1.3V
I-DAC1 Gain
Full Code
BIASMON to
BIASMON = 1.3V
I-DAC2 Gain
Full Code
<MS0189-E-01>
min
0.008
typ
0.0095
max
0.011
Unit
A/A
0.008
0.0095
0.011
A/A
-8-
Remark
2004/5
ASAHI KASEI
10. PDGAIN
Item
PDIN Input Range
PDGAIN Gain Error
11. DACAPC
Item
Maximum Output Voltage
Minimum Output Voltage
DNL
12. BIASGEN
Item
BIAS pin Voltage
[AK2573A]
min
0.08
-0.5
条件
PDMON=1V±10%
PDIN→PDMON
Condition
Test Mode
Test Mode
Test Mode
min
1.135
0.752
-1
Condition
typ
1.195
0.792
min
typ
1.2
13. Temperature Sensor
Item
Condition
min
Voltage Slope
TEMPMON Voltage
-12.14
Offset Adjustment Target Ta = 35℃
Note 1: This parameter is characterized and is not 100% tested.
14. ADC
Item
Resolution
Maximum Input Voltage
Minimum Input Voltage
DNL
15. Power On Reset
Item
Detect Voltage
Condition
min
2.09
typ
-11.56
1.215
typ
7
2.2
0
max
2.5
+0.5
Unit
V
dB
max
1.255
0.832
+1
Unit
V
max
Unit
V
max
-10.98
max
Unit
bit
V
V
LSB
2.31
-1/2
Condition
typ
+1/2
Remark
Remark
LSB
Remark
Unit
mV / ℃
V
Remark
Note-1
Remark
min
2.3
typ
2.5
max
2.7
Unit
V
Remark
min
typ
2.15
max
Unit
MHz
Remark
min
1/3.2
1/4.3
1/6.4
1/7.5
typ
1/3
1/4
1/6
1/7
max
1/2.8
1/3.7
1/5.6
1/6.5
18. TXDIS Release Time
Item
Condition
min
typ
TXDIS Release Time
Note 1: This parameter is characterized and is not 100% tested.
max
500
Unit
us
16. On-chip Oscillator
Item
Condition
Clock Frequency
Test Mode
17. OPTALM Detect Level
Condition
項目
OPTALM Detect Level 1/3 Setting, PDGAIN=0dB
1/4 Setting, PDGAIN=0dB
1/6 Setting, PDGAIN=0dB
1/7 Setting, PDGAIN=0dB
<MS0189-E-01>
-9-
Unit
Remark
Remark
Note 1
2004/5
ASAHI KASEI
[AK2573A]
Ⅴ. Package Information
(1) Package Type: 48 pin BCC++
(2) Marking Information:
(a) PIN#1 Indication: ○
(b) Logo: AKM
(c) Marking Code: AK2573AVB
(d) Date Code: YYWWXXX (7 digit)
AKM
AK2573AVB
YYWWXXX
(3) Package Outline
6.2
0.5
7.0±0.1
0.09MIN
0.5±0.1
37
25
25
37
5.1
5.0
6.15
6.2
7.0±0.1
5.5±0.06
"A"
1
13
13
1
"B"
"C"
5.0
6.15
0.3±0.06
<MS0189-E-01>
-10-
C0.2
0.45±0.06
0.45±0.06
0.14
MIN
0.4±0.06
0.075±0.025
0.80
MAX
0.05
"C" Part
0.45±0.06
"B" Part
"A" Part
0.45±0.06
2004/5
ASAHI KASEI
[AK2573A]
Ⅵ. Circuit Description
1. Parameter Notation
1.1 Parameter Definition
In the AK2573A Circuit Description, in order to distinguish various pre-set parameter sources from EEPROM,
Registers or Device pins, “Identifier - Main name” notation is used as shown in Table 1-1. For ease of operational
description, small letters sometimes expresses internal signals.
Table 1-1 Parameter Definitions
Identifier
Register
R_
EEPROM
E_
Ether or both Register
or /and EEPROM
RE_
PIN
P_
BLOCK
None
Internal Node
None
Main Name
REGISTER name
(All Capital)
EEPROM name
(All Capital))
REGISTER /
EEPROM name
(All Capital)
PIN name
(All Capital)
BLOCK name
(All Capital))
signal name
(small letter)
Remark
Indicates register
Example
R_APC_FB
R_DAC1
Indicates EEPROM
E_PDGAIN
E_DAC1_FF_TC
Indicates either register RE_DAC1_GAIN
or EEPROM
RE_APC_TRGT
P_PDMON
I-DAC1
APC_COMP
vpd
1.2 Operation Overview
The AK2573A has 3 primary functions; 125M / 156M Laser diode driver part, APC (Automatic Power Control) part
which supplies adequate bias current and modulation current to a Laser Diode, and the Control part to control
operation modes of the AK2573A operation.
There are 3 operation modes in the AK2573A. Since each adjusting function is controlled through I2CTM Interface, it
realizes an automatic parameter adjustment.
(1) Self-running Mode
Self-running mode is ready for normal operation after all adjustments are completed. In this mode, temperature
detection, EEPROM access and feeding current are automatically performed using the on-chip oscillator. The
AK2573A works in this mode after power-on.
(2) Adjustment Mode
Adjustment mode is designed for training the LD characteristics. The AK2573A operates according to the register
settings set through the I2CTM I/F.
(3) EEPROM Mode
EEPROM mode is used for storing LD characteristics into EEPROM via I2CTM I/F.
<MS0189-E-01>
-11-
2004/5
ASAHI KASEI
[AK2573A]
2. Driver
Fig 2-1 illustrates the block diagram of the driver function.
AK2573A has two current DACs, I-DAC1 and I-DAC2. I-DAC1 is for modulation current and I-DAC2 is for bias
current. Table 1-1 and 1-2 show I-DAC1, I-DAC2 characteristics.
Fig 2-1 Driver Block Diagram
LD
IBIAS
AK2573A
IMOD
IMODN
Ibias
I-DAC2
Driver
Imod
I-DAC1
(1) I-DAC1 (Table 2-1)
RE_DAC1_
GAIN
1
0
(2) I-DAC2 (Table 2-2)
RE_DAC2_
GAIN
1
0
DAC1_GAIN
1
1/2
DAC2_GAIN
1
1/2
Output current @ Output Current Current step /
Full code (typ)
Range (typ)
LSB (typ)
85 mA
0 to 85 mA
0.333 mA
43 mA
0 to 43 mA
0.169 mA
Output current @ Output Current Current step /
Full code (typ)
Range (typ)
LSB (typ)
54 mA
0 to 54 mA
0.212 mA
27 mA
0 to 27 mA
0.106 mA
(3) I-DAC1 / I-DAC2 Common Characteristics
Resolution: 8bit
DNL: +/- 1 LSB @ code = 20h to FFh
3. DATA / CLK I/F (LVPECL)
The AK2573A supports direct data or latched data input (see Table 3-1). Connect CLKP = VSS, and connect CLKN
= VDD or leave open when SEL =“L”.
Table 3-1 Data input
SEL (CMOS)
“L”
“H”
<MS0189-E-01>
Direct data
Latched data with clock
-12-
2004/5
ASAHI KASEI
[AK2573A]
3.1 LVPECL Input (DATAP / DATAN / CLKP / CLKN)
Table 3-2 shows LVPECL input characteristics. The AK2573A LVPECL input, which is biased to 0.6 * VDD with
10kΩ or more inpedance respectively, supports both AC and DC coupling. Fig 3-2 illustrates LVPECL input with AC
coupling and Fig3-3 illustrates with DC coupling respectively.
Table 3-2 LVPEL Interface characteristics
Item
Symbol
min
typ
Single-ended Input Voltage |Vamp|
0.1
Swing
Common Voltage
Vcom
0.5*VDD
BIAS Voltage
Vbias
0.6*VDD
Input Impedance
Zin
10
Set-up Time
tsu
1.5
Hold Time
th
1.5
Note 1: This parameter is characterized and is not 100% tested.
max
1.2
Unit
V
VDD – 1.0
V
V
kΩ
ns
ns
Remarks
see Fig 3-1
see Fig 3-2 and 3-3
see Fig 3-4
Note 1
Fig 3-1 DATA / CLK Input Level
Vamp
Vcom
CLKP/CLKN
DATAP/DATAN
Fig 3-2 LVPECL input with AC coupling
Fig3-3 LVPECL input with DC coupling
AK2573A
0.01uF or more
100Ω
AK2573A
Vbias
Zin
130Ω
DATAP
CLKP
82Ω
Zin
0.01uF or more
DATAN
CLKN
Zin
DATAP
DATAN
CLKP
CLKN
Vbias
Vbias
Fig 3-4 Set-up & Hold Time
DATA
(DATAP DATAN)
tsu
th
CLK
(CLKP - CLKN)
<MS0189-E-01>
-13-
2004/5
ASAHI KASEI
[AK2573A]
3.2 Duty Adjustment
AK2573A supplies a programmed duty adjustment in response to the temperature from an on-chip temperature
sensor (every 6℃, Duty data is stored in E_DUTY_TC, see Table 8-3 for more information). Write same data into
E_DUTY_TC for constant duty adjustment. Table 3-3 and 3-4 show the characteristics of duty adjustment function.
Table 3-3 Duty Adjustment characteristics
Item
Symbol
min
Maximum Pulse Extended
Td
0.5
1 LSB Pulse Extended Step
Tstep
Pulse Extended Stability
Tsta
typ
max
Unit
ns
ns
ns
0.03
0.2
Remarks
Note 1
32 Steps
Ta=-40 to 85℃, VDD=3.1～
3.5V, 0.3ns Extended (Note 1)
Note 1: This parameter is characterized and is not 100% tested.
Table 3-4 Pulse Extended
R_DUTY
Pulse Extended (typ) [ns]
0
0
1
0.03
2
0.06
.
.
.
.
30
0.90
31
0.93
Remark
4. APC
The AK2573A has two APC functions, APC FF (Feed-forward) and APC FB (Feedback).
APC FF supplies a programmed current in response to the temperature from an on-chip temperature sensor.
APC_FB provides stable a power control function using a digital feedback algorithm. The APC_FF and APC_FB is
user programmable. Fig4-1 illustrates APC block diagram.
Fig 4-1 APC Block Diagram
ALM Polarity
(RE_ALM_POL)
Temperature ALM
(RE_TEMPALM)
TEMPALM
TEMP
ALM
Gain
(RE_DAC1_GAIN)
RE_TEMP_OFFSET
APC FF
(R_DAC1_FF)
TEMPSN
S
ADC
+
K_DAC1
_FBRT
EEPROM
R_TEMP
APC FB Operation
(RE_APC_FB_SET)
APC Operation
(RE_APC_FF_SET)
TEMPMON
R_DAC1
Imod
I-DAC1
IMOD
Driver
IMODN
I-DAC1 FB
(R_DAC1_FB)
I-DAC2 FB
(R_DAC2_FB)
K_DAC2
_FBRT
* 0.0095
MODMO
Gain
N
(RE_DAC2_GAIN)
Ibias IBIAS
APC FF
(R_DAC2_FF)
APC FB Initial setting
(RE_APC_INIT_SET)
APC Feedback
(R_APC_FB)
PDGAIN
(RE_PDGAIN)
Digital Filter
apc_comp_out
PDIN
CPD
RPD
PDGAIN
vpd
1/N
APC_
COMP
1/s
<MS0189-E-01>
DAC_APC
vapc_ref
ALMPolarity
(RE_ALM_POL)
R_DAC1
CURR
ALM
R_DAC2
BIASMON
CURRALM
Over current ALM
(RE_CURRALM)
ALM Polarity
(RE_ALM_POL)
OPTALM
(RE_OPTALM_)
APC Target
(RE_APC_TRGT)
I-DAC2
R_DAC2
* 0.0095
PDMON
Monitor
PD
+
OPTALM
ATT
OPTALM
OPTALM Reference
(optalm_ref)
-14-
2004/5
ASAHI KASEI
[AK2573A]
4.1 APC_FF Function
Fig 4-2 illustrates the APC FF functions. The operation is as follows:
(1) Analog to digital conversion of the voltage (7 bit) that reflects the temperature for every temperature detection
period (128ms typ).
(2) Read the 8 bit current data (address is indicated by the ADC data) from EEPROM and set this value to the
I-DACs.
If the current data over temperature is set to each EEPROM address, the compensated current is supplied to the LD
automatically.
To use this function, current data should be stored in EEPROM in advance. The temperature sensor is cover–40℃ to
115℃ and EEPROM is prepared with 1.5℃ steps.
Fig 4-2 APC FF function
R_TEMP
ADC
(7bit)
TEMPSENS
Address
Data
R_DAC2_FF
Voltage
I-DAC1
Driver
I-DAC2
BIAS Current
Memory for
I-DAC1
Temperature
LD
MOD Current
Addressing
with
R_TEMP
TEMPSENS
charatcteristics
R_DAC1_FF
EEPROM
Memory for
I-DAC2
4.2 APC_FB Function
Fig 4-3 shows APC_FB functions. It operates as follows:
(1) APC_COMP compares vpd and vapc_ref.
(2) The digital filter calculates the compensation current (R_APC_FB) to equalize vpd with vapc_ref to keep LD
power constant.
The vapc_ref (RE_APC_TRGT) can be changed over temperature automatically. Temperature compensation
procedure is as same as APC FF (data of DAC_APC is read out EEPROM in response to the temperature).
For the stable operation, the cut-off frequency of RPD and CPD should be 1kHz to 10kHz.
Fig 4-3 APC FB function
TEMPSENS
ADC
R_TEMP
APC FF
+
EEPROM
R_DACx
I-DAC
may set initial valuein response to
the temperature at power-on
to accelerate power-up sequence
PDMON
Monitor
PD
512kHz(typ)
Digital Filter
PDIN
CPD
PDGAIN
RPD
APC_
COMP
vpd
comp_out
R_APC_FB
1/N
1/s
Electrical volume for Monitor PD
RE_APC_TRGT
<MS0189-E-01>
DAC_APC
vapc_ref
-15-
2004/5
ASAHI KASEI
[AK2573A]
4.2.1 PDGAIN
PD monitor current is converted to the average voltage with RPD and CPD and input to PDIN. PDIN voltage may be
gained at PDGAIN and monitored at PDMON. PDGAIN should be adjusted to PDMON = 1V typ. The gain range
of PDGAIN is –8.0dB to 23.5dB with 0.5dB steps (6-bits). PDGAIN is set via the I2CTM interface. Table 4-1 shows
PDIN input range and Table 4-2 shows the relationship between PDGAIN and EEPROM setting.
Table 4-1 PDIN input range
Parameter
PDIN Input range
Table 4-2 PDGAIN
RE_PDGAIN_SET
000000 (0)
000001 (1)
:
111110 (62)
111111 (63)
min
0.08V
max
2.5V
Gain (typ) [dB]
23.5
23.0
:
-7.5
-8.0
Remark
Remark
0.5dB step
4.2.2 DACAPC
DACAPC generates the reference voltage of APC (vapc_ref). AK2573A supplies a programmed APC reference in
response to the temperature from an on-chip temperature sensor (every 6℃, APC reference data is stored in
E_APC_TRGT_TC, see Table 8-3 for more information). Write same data into E_APC_TRGT_TC for constant APC
reference. Table 4-3 shows the relationship between APC reference voltage (vapc_ref) and EEPROM setting.
Table 4-3 DACAPC
E_APC_TRGT_TC
(R_APC_TRGT)
00000(0)
:
01111 (15)
10000 (16)
10001 (17)
:
11111 (31)
DACAPC (vapc_ref) (typ) [V]
0.792
Remark
13mV step
0.987
1.0
1.013
1.195
4.2.3 Example of APC Setting
Table 4-4 shows the typical setting of APC function (APC_FF and APC_FB). The combination of APC is set by
RE_APC_FF and RE_APC_FB. Fig 4-5 shows the EEPROM area for MOD current (E_DAC1_TC) and BIAS
current (E_DAC2_TC). The data should be stored in E_DAC1_TC and E_DAC2_TC is determined by RE_APC_FF
and RE_APC_FB. Table 4-7 and 4-8 shows all combination of APC function.
RE_APC_FF is 2bit data to be assigned I-DAC for APC_FF operation. MSB is for I-DAC2 and LSB for I-DAC1.
RE_APC_FB is 2bit data to be assigned I-DAC for APC_FB operation. MSB is for I-DAC2 and LSB for I-DAC1.
In the case of RE_APC_FB=11(binary), AK2573A is in “Dual Feedback” (see Fig 4-9, 4-10 and Table 4-6).
<MS0189-E-01>
-16-
2004/5
ASAHI KASEI
[AK2573A]
Table 4-4 Example of APC FF and APC FB combination
RE_APC_ RE_APC_ BIAS
MOD
Remarks
Reference
FF_SET
FB_SET (I-DAC2) (I-DAC1)
01
10
FB
FF
The initial value of APC FB according to the Fig 4-4
temperature can be set to accelerate power up time.
10
01
FF
FB
The initial value of APC FB according to the Fig 4-5
temperature can be set to accelerate power up time.
11
00
FF
FF
Both BIAS and MOD current are detrmined by Fig 4-6
APC_FF. APC_FB is not work.
11
01
FF
FF+FB Both BIAS and MOD current are detrmined by Fig 4-7
APC_FF. APC_FB is set to MOD for LD aging.
11
10
FF+FB
FF
Both BIAS and MOD current are detrmined by Fig 4-8
APC_FF. APC_FB is set to BIAS for LD aging.
01
11
FB
FF+FB Dual Feedback function.
Fig 4-9
BIAS current is determined by APC_FB. MOD
current is determined by APC_FF and APC_FB.
The initial value of APC_FB according to the
temperature can be set to accelerate power up time.
10
11
FF+FB
FB
Dual Feedback function.
Fig 4-10
MOD current is determined by APC_FB. BIAS
current is determined by APC_FF and APC_FB.
The initial value of APC_FB according to the
temperature can be set to accelerate power up time.
00
11
Prohibit
11
11
Prohibit
RE_APC_FF_SET (Register or EEPROM) is composed of 2-bits. MSB shows BIAS (I-DAC2) and LSB shows MOD
(I-DAC1), and “1” indicates APC Feed-forward function is selected.
RE_APC_FB_SET (Register or EEPROM) is composed of 2-bits. MSB shows BIAS (I-DAC2) and LSB shows MOD
(I-DAC2), and “1” indicates APC Feedback function is selected.
Fig 4-4 APC example-1 (MOD=FF, BIAS=FB)
R_DAC1_FF
Fig 4-5 APC example-2 (MOD=FB, BIAS=FF)
R_DAC1_FF =
0
RE_DAC1_GAIN
I-DAC1
R_APC_FB
0
R_DAC1_FB
=0
+
R_DAC1
85/255
G_DAC1
Imod
R_APC_FB
1
R_DAC1_FB
= R_APC_FB
+
R_DAC1
I-DAC2
1
R_DAC2_FB
= R_APC_FB
R_DAC1 = R_DAC1_FF
+
R_DAC2
RE_DAC1_GAIN
I-DAC1
85/255
G_DAC1
Imod
I-DAC2
54/255
R_DAC2_FF = 0
G_DAC2
Ibias
RE_DAC2_GAIN
R_DAC2 = R_DAC2_FB = R_APC_FB
0
R_DAC2_FB
=0
R_DAC1 = R_DAC1_FB = R_APC_FB
G_DAC1/G_DAC2 = 1 or 0.5
R_DAC2 = R_DAC2_FF
+
R_DAC2
R_DAC2_FF
54/255
G_DAC2
Ibias
RE_DAC2_GAIN
G_DAC1/G_DAC2 = 1 or 0.5
Fig 4-6 APC example-3 (MOD=FF, BIAS=FF)
R_DAC1_FF
RE_DAC1_GAIN
I-DAC1
R_APC_FB
0
R_DAC1_FB
=0
+
R_DAC1
85/255
G_DAC1
Imod
I-DAC2
0
R_DAC2_FB
=0
R_DAC1 = R_DAC1_FF
R_DAC2 = R_DAC2_FF
<MS0189-E-01>
+
R_DAC2
R_DAC2_FF
54/255
G_DAC2
Ibias
RE_DAC2_GAIN
G_DAC1/G_DAC2 = 1 or 0.5
-17-
2004/5
ASAHI KASEI
[AK2573A]
Fig 4-7 APC example-4 (MOD=FF+FB, BIAS=FF)
R_DAC1_FF
R_APC_FB
1
Fig 4-8 APC example-5 (MOD=FF, BIAS=FF+FB)
RE_DAC1_GAIN
R_DAC1_FF
I-DAC1
R_DAC1_FB
=
R_APC_FB
+
R_DAC1
85/255
G_DAC1
Imod
R_APC_FB
0
+
R_DAC1
I-DAC2
0
R_DAC2_FB
=0
R_DAC1_FB = R_APC_FB
+
R_DAC2
R_DAC2_FF
G_DAC2
Ibias
1
R_DAC1_FBRT
(E_DAC_FBRT_FIX)
+
R_DAC2
54/255
R_DAC2_FF
Imod
G_DAC2
Ibias
RE_DAC2_GAIN
R_DAC1 = R_DAC1_FF
G_DAC1/G_DAC2 = 1 or 0.5
R_DAC1_FF
Fig 4-10 APC example-7 (MOD=FB, BIAS=FF+FB)
R_DAC1_FF =
0
RE_DAC1_GAIN
I-DAC1
R_DAC1_FB
+
R_DAC1
85/255
G_DAC1
Imod
R_APC_FB
R_DAC2_FB
= R_APC_FB
+
R_DAC2
R_DAC1_FB = K_DAC1_FBRT * R_APC_FB R_DAC2_FF = 0
R_DAC1 = R_DAC1_FF + R_DAC1_FB
1
R_DAC1_FB
=
R_APC_FB
+
R_DAC1
R_DAC2_FBRT
(E_DAC_FBRT_FIX)
I-DAC2
1
G_DAC1
R_DAC2 = R_DAC2_FF + R_DAC2_FB
Fig 4-9 APC example-6 (MOD=FF+FB, BIAS=FB)
K_DAC1_
FBRT
R_DAC2_FB
= R_APC_FB
R_DAC2_FB = R_APC_FB
RE_DAC2_GAIN
G_DAC1/G_DAC2 = 1 or 0.5
R_DAC2 = R_DAC2_FF
R_APC_FB
85/255
I-DAC2
54/255
R_DAC1 = R_DAC1_FF + R_DAC1_FB
RE_DAC1_GAIN
I-DAC1
R_DAC1_FB
=0
54/255
G_DAC2
Ibias
RE_DAC2_GAIN
G_DAC1/G_DAC2 = 1 or 0.5
R_DAC2 = R_DAC2_FB = R_APC_FB
K_DAC2_
FBRT
R_DAC2_FB
R_DAC2_FB = K_DAC2_FBRT * R_APC_FB
RE_DAC1_GAIN
I-DAC1
85/255
G_DAC1
Imod
I-DAC2
+
R_DAC2
54/255
G_DAC2
Ibias
RE_DAC2_GAIN
R_DAC2_FF
R_DAC1 = R_DAC1_FB = R_APC_FB
G_DAC1/G_DAC2 = 1 or 0.5
R_DAC2 = R_DAC2_FF + R_DAC2_FB
Table 4-5 EEPROM Assignments for typical operation
RE_APC_ RE_APC_ RE_APC_ E_DAC2_TC
E_DAC1_TC
I-DAC2
FF_SET
FB_SET
INIT_SET
(BIAS)
01
10
0
E_DAC1_FF_TC
FB
1
E_APC_INIT_TC E_DAC1_FF_TC
FB
10
01
0
E_DAC2_FF_TC
FF
1
E_DAC2_FF_TC E_APC_INIT_TC
FF
11
00
x
E_DAC2_FF_TC E_DAC1_FF_TC
FF
11
01
x
E_DAC2_FF_TC E_DAC1_FF_TC
FF
11
10
x
E_DAC2_FF_TC E_DAC1_FF_TC
FF+FB
01
11
0
E_DAC1_FF_TC
FB
01
11
1
E_APC_INIT_TC E_DAC1_FF_TC
FB
10
11
0
E_DAC2_FF_TC
FF+FB
10
11
1
E_DAC2_FF_TC E_APC_INIT_TC
FF+FB
00
11
x
Prohibit
11
11
x
E_DAC1_FF_TC: I-DAC1 current data (temperature compensated)
E_DAC2_FF_TC: I-DAC2 current data (temperature compensated)
E_APC_INIT_TC: R_APC_FB initial data (temperature compensated)
I-DAC1
(MOD)
FF
FF
FB
FB
FF
FF+FB
FF
FF+FB
FF+FB
FB
FB
Table 4-6 APC FB Operation
RE_APC_
FB_SET
00
01
10
11
RE_APC_
FF_SET
XX
XX
XX
00
01
10
11
<MS0189-E-01>
K_DAC1_FBRT
K_DAC2_FBRT
Remark
0
1
0
R_DAC1_FBRT*1.25/64/G_DAC1
1
-
0
0
1
1
R_DAC2_FBRT/32/G_DAC2
-
No FB
FB for MOD
FB for BIAS
Prohibit
R_DAC1_FBRT=E_DAC_FBRT
R_DAC2_FBRT=E_DAC_FBRT
Prohibit
-18-
2004/5
ASAHI KASEI
[AK2573A]
Table 4-7 APC and EEPROM assignment (Self-running mode)
RE_APC_ RE_APC
FB_SET _FF_SET
00
00
01
10
11
01
00
00
01
10
10
11
10
00
00
01
01
10
11
11
00
01
0
0
E_DAC2_TC
E_DAC2_TC
0
0
0
E_DAC2_TC
E_DAC2_TC
E_DAC2_TC
0
0
0
0
E_DAC2_TC
E_DAC2_TC
0
R_APC
_FB
0
0
0
0
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
Initial setting
R_APC_FB
0
0
0
0
0
E_DAC1_TC
0
0
E_DAC1_TC
0
0
E_DAC2_TC
0
E_DAC2_TC
0
0
0
E_DAC1_TC
0
FB
E_DAC2_TC
0
0
E_DAC2_TC
FB
0
K_DAC1
_FBRT
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
See
Table 4-6
See
Table 4-6
1
10
1
0
E_DAC2_TC
FB
E_DAC1_TC
1
11
X
-
-
-
-
-
RE_APC_
INIT_SET
X
X
X
X
0
1
X
0
1
X
0
1
0
1
X
X
X
0
R_DAC1_FF
R_DAC2_FF
0
E_DAC1_TC
0
E_DAC1_TC
0
0
E_DAC1_TC
0
0
E_DAC1_TC
0
0
E_DAC1_TC
E_DAC1_TC
0
E_DAC1_TC
E_DAC1_TC
01
1
10
K_DAC2_
FBRT
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
MOD
(R_DAC1)
0
FF
0
FF
FB
FB
FF + FB
FB
FB
FF + FB
0
0
FF
FF
0
FF
FF + FB
BIAS
(R_DAC2)
0
0
FF
FF
0
0
0
FF
FF
FF
FB
FB
FB
FB
FF + FB
FF + FB
FB
E_DAC1
_TC
FF
FF
FB_INIT
FF
FB_INIT
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FB_INIT
FB_INIT
FF
FF
-
1
FF + FB
FB
FF
FB_INIT
See
Table 4-6
See
Table 4-6
-
FB
FF + FB
-
FF
FB
FF + FB
FB_INIT
FF
-
-
-
-
E_DAC2
_TC
Remarks
Prohibit
Prohibit
Table 4-8 APC and EEPROM assignment (Adjustment mode)
RE_APC_
FB_SET
00
01
10
11
RE_APC_
FF_SET
XX
XX
XX
00
01
10
11
<MS0189-E-01>
RE_APC_
INIT_SET
X
X
X
X
X
X
X
R_DAC1_FF
I/F
0
I/F
I/F
0
-
R_DAC2_FF
I/F
I/F
0
0
I/F
-
R_APC_
FB
0
FB
FB
FB
FB
-
R_DAC1_
FBRT
N/A
N/A
N/A
I/F
N/A
-
-19-
R_DAC2_
FBRT
N/A
N/A
N/A
N/A
I/F
-
K_DAC1_
FBRT
0
1
0
See Table 4-6
1
-
K_DAC2_
FBRT
0
0
1
1
See Table 4-6
-
MOD
(R_DAC1)
FF
FB
FF
FF + FB
FB
-
BIAS
(R_DAC2)
FF
FF
FB
FB
FF + FB
-
Remarks
Prohibit
Prohibit
2004/5
ASAHI KASEI
[AK2573A]
4.3 Temperature Sensor (TEMPSENS)
Fig 4-11 shows an on-chip temperature sensor characteristics and Table 4-9 shows the relationship between detected
temperature and ADC code.
Fig 4-11 On-chip Temperature Sensor Characteristics
On-chip Temperature sensor characteristics
2.5
Output voltage V [V]
2.0
1.5
1.0
0.5
0.0
-40
-20
0
20
40
60
80
100
120
Temperature t [°C]
(1)
(2)
(3)
(4)
Slope: -11.56mV/℃ (typ)
V(t) = -0.01156 * t + 1.62 [V] (typ)
AD_code = int( V(t) / 2.2 * 127 +0.5) = int(-0.667*t + 94.0)
Temperature step @ AD_code=1LSB: 1.49℃/LSB
* Temperature sensor detects the junction temperature, not LD or ambient temperature.
<MS0189-E-01>
-20-
2004/5
ASAHI KASEI
Table 4-9 AD code and detected temperature [typ]
AD code
AD code
Temp [℃]
Temp [℃]
0
140.1
32
92.2
1
138.6
33
90.7
2
137.1
34
89.2
3
135.6
35
87.7
4
134.1
36
86.2
5
132.6
37
84.7
6
131.1
38
83.2
7
129.6
39
81.7
8
128.2
40
80.2
9
126.7
41
78.7
10
125.2
42
77.2
11
123.7
43
75.7
12
122.2
44
74.2
13
120.7
45
72.7
14
119.2
46
71.2
15
117.7
47
69.7
16
116.2
48
68.2
17
114.7
49
66.7
18
113.2
50
65.2
19
111.7
51
63.7
20
110.2
52
62.2
21
108.7
53
60.7
22
107.2
54
59.2
23
105.7
55
57.7
24
104.2
56
56.2
25
102.7
57
54.7
26
101.2
58
53.2
27
99.7
59
51.7
28
98.2
60
50.2
29
96.7
61
48.7
30
95.2
62
47.2
31
93.7
63
45.7
[AK2573A]
AD code
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Temp [℃]
44.2
42.7
41.2
39.7
38.2
36.7
35.2
33.7
32.2
30.7
29.2
27.7
26.3
24.8
23.3
21.8
20.3
18.8
17.3
15.8
14.3
12.8
11.3
9.8
8.3
6.8
5.3
3.8
2.3
0.8
-0.7
-2.2
AD code
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Temp [℃]
-3.7
-5.2
-6.7
-8.2
-9.7
-11.2
-12.7
-14.2
-15.7
-17.2
-18.7
-20.2
-21.7
-23.2
-24.7
-26.2
-27.7
-29.2
-30.7
-32.2
-33.7
-35.2
-36.7
-38.2
-39.7
-41.2
-42.7
-44.2
-45.7
-47.2
-48.7
-50.2
4.4 Current Monitor
AK2573A has MOD current and BIAS current monitor, MODMON and BIASMON respectively. MODMON is
0.0095 times of I-DAC1 output (source type) and BIASMON is 0.0095 times of I-DAC2 output (source type).
<MS0189-E-01>
-21-
2004/5
ASAHI KASEI
[AK2573A]
5. Alarm
AK2573A has 5 alarm functions as shown in Table 5-1.
Table 5-1 Alarm function
ALM
Detection condition
OPTALM
When monitor PD current is below the OPTALM level.
CURRALM
When R_DAC1 or R_DAC2 is beyond CURRALM level or
equal to full code.
TEMPALM
When the detected temperature is beyond TEMPALM
level.
DATAALM
When the detected 0s or 1s sequential data input (4.5us
typical).
TXFAULT
When one or more alarm detected.
Polarity
Detected Time
Programmable 5us (typ) (Note 1)
Programmable every 125us (typ)
Programmable every 128ms (typ)
Programmable 4.5us (typ)
“H”
depends on
detected ALM
Note 1: Not include delay time by RPD and CPD.
5.1 OPTALM
OPTALM level (optalm_ref) is selectable among 1/3, 1/4, 1/6 and 1/7 of APC FB reference voltage (vapc_ref) by
RE_OPTALM.
OPTALM is detected when vpd < optalm_ref.
APC FB keeps R_APC_FB during OPTALM detection in the“Self running mode”.
5.2 CURRALM
CURRALM is detected when
R_DAC1(MSB 4bit) > R_CURRALM_DAC1 or R_DAC2(MSB 4bit) > R_CURRALM_DAC2
R_CURRALM_DAC1 and 2 can be set every 6℃.
CURRALM is clear when receiving disable request (TX_DIS1 or TX_DIS2 is set “H”).
5.3 TEMPALM
TEMPALM is detected when R_TEMP < R_TEMPALM.
R_TEMP has negative slope compared to the temperature, TEMPALM is detected when the detected temperature
beyond R_TEMPALM.
5.4 DATAALM
DATAALM is detected when input DATA is 0’s or 1’s fixed more than 4.5us (typ).
APC FB keeps R_APC_FB during DATAALM detection in the“Self running mode”.
DATAALM detection is ignored when RE_DATAALM_MASK= “1”.
5.5 TXFAULT
TXFAULT function is shown in Table 5-2.
Table 5-2 TXFAULT
RE_SFP
Shutdown request
(TXDIS 1, 2)
0
0
0
0
0
1
1
0
1
0
1
1
<MS0189-E-01>
ORed ALM
0
1
X
0
1
X
TXFAULT
0
1
ORed ALM
0
1 (Hold)
0 or 1 (Hold)
-22-
I-DAC output
Normal Operation
Normal Operation
Shutdown
Normal Operation
Shutdown
Shutdown
2004/5
ASAHI KASEI
[AK2573A]
RE_SFP = 0 operation
Set “H” when OPTALM, CURRALM, TEMPALM or DATAALM is detected
Set “L” when no ALM detected.
RE_SFP=1 operation
Support TX_FAULT of the SFP (Small Form-factor Pluggable) requirement.
Set and hold “H” when detected OPTALM, CURRALM, TEMPALM or DATAALM and go into shutdown
mode.
Reset to “L” when TXDIS1 or TXDIS2 is “H“ → “L”. Refer to “6. Shutdown” for more information.
During “Adjustment mode”, TXFAULT detection is ignored.
6. Shutdown
6.1 Shutdown Operation
Fig 6-1 shows the shutdown operation. The AK2573A supports the SFP (Small Form-factor Pluggable) requirement.
Fig 6-1 Shutdown Operation
TXDIS1
TXDIS2
1
X
X
1
0
0
0
0
0
0
RE_SFP
X
X
0
1
1
TXFAULT
X
X
X
0
1
Operation
Shutdown
Shutdown
Normal Operation
Normal Operation
Shutdown
Fig 6-2 Shutdown Condition
Function
Operation
I-DAC1 / 2 output High-Z (0mA output)
APC_FF
Normal Operation.
APC_FB
Keep the data at shutdown request.
ALM
Normal Operation
TXFAULT
R_SFP=0: Normal Operation
R_SFP=1: Keep the data at shutdown request.
Remarks
Shutdown with pin
Shutdown with pin
SFP TXFAULT
Operation
Remarks
6.2 Temperature Comparison between Shutdown Request and Release
The AK2573A keeps the temperature data at shutdown request and compares it with temperature at release request
to avoid over-current conditions at the LD. When the AK2573A detects a temperature difference between at
shutdown request and the release request, the APC FB data is set to 0 or to initial values in response to the
temperature at the release request. The temperaturedifference is programmable.
When the AK2573A does not detect a temperature difference,it keeps the APC FB data, resulting in faster operation.
This function works at release request as follows:
if (ABS(R_TEMP_STDW – R_TEMP)) > R_TEMP_WIN)
R_APC_FB = 0 or reset to the initial value in response to the R_TEMP
where, R_TEMP_STDW is a temperature at shutdown request
R_TEMP is a temperature at release request
R_TEMP_WIN is a temperature difference (user programmable)
APC FF continues to operate during shutdown for fast performance when a release request is received. However, the
I-DAC current stays at 0mA.
<MS0189-E-01>
-23-
2004/5
ASAHI KASEI
[AK2573A]
Table 6-3 Operation at shutdown release
RE_SFP TXFAULT at
RE_TEMP_ Temp Difference
Shutdown request DET
result
0
X
0
X
0
X
1
0
0
X
1
1
1
0
0
X
1
0
1
0
1
0
1
1
1
1
X
X
R_APC_FB
Remark
Initial value
Hold data
Initial value
Initial value
Hold data
Initial value
Initial value
7. Power-up / down Timing
7.1 Delay Time of TXFAULT Detection with OPTALM
In correspond to the delay time caused by RPD and CPD to get the moniter PD average current, the delay time of
TXFAULT detection with OPTALM is set when RE_SFP=”1” (SFP support). AK2573A has 2 delay time when
RE_SFP=”1”: normal delay and accelerated delay. Accelerated delay may be selected when both I-DAC1 and I-DAC2
are set to APC_FF or APC_FB with an initial value setting.
Table 7-1 shows the delay time of TXFAULT detection with OPTALM and Fig 7-1 illustrated block diagram.
Note: When accelerated delay is selected with RE_SFP=”1”, APC_FF data or initial data of APC_FB should be
suitable, otherwise AK2573A might go into shutdown by detection of OPTALM after delay time.
Fig 7-1 APC_FB Block Diagram
PDGAIN
(R_PDGAIN)
Monitor
PD
LD
PDIN
CPD
PDGAIN
RPD
Detection and reset OPTALM
vary with the cut-off
frequency of CPD and RPD
APC_
COMP
Digital
Filter
APC Feedback
(R_APC_FB)
TX_FAULT
Control
vpd
OPTALM Level
(R_OPTALM)
APC Terget
(R_APC_TRGT
)
DAC_APC
vapc_ref
ATT
OPTALM
OPTALM
reference
(opalm_ref)
Table 7-1 Delay time of TXFAULT detection with OPTALM
RE_SFP R_TIMER_
R_APC_
R_APC_
Delay Time of TXFAULT Remarks
OPTALM
INIT_SET FF_SET
detection with OPTALM
0
X
X
X
0 ms
disable TXFAULT
detection
1
0
X
X
160 ms (typ)
1
1
0
00
160 ms (typ)
01
10
1
1
X
11
2 ms (typ)
Acceleration
power-up
1
1
1
X
2 ms (typ)
<MS0189-E-01>
-24-
2004/5
ASAHI KASEI
[AK2573A]
7.2 Power on Initialization Procedure without Shutdown Request (TXDIS=L)
VDD
TXDIS
TXFAULT with OPTALM enable
(if accelerated delay time is selected)
2ms
LD Current
APC FF or
FB initial setting
Normal Operation
APC FF
APC FB initial procedure
ALM operation
Power On Reset
TXFAULT enable （without OPTALM)
TXFAULT with
OPTALM enable
t_init: 160ms (typ)
7.3 Power on Initialization Procedure with Shutdown request (TXDIS=H)
VDD
TXDIS
LD current
2ms
TXFAULT with OPTALM enable
(if accelerated delay time is selected)
APC FF or
FB initial setting
Normal Operation
APC FF
APC FB initial procedure
Power On Reset
ALM operation
TXFAULT enable （without OPTALM)
TXFAULT with
OPTALM enable
t_init: 160ms (typ)
<MS0189-E-01>
-25-
2004/5
ASAHI KASEI
[AK2573A]
7.4 TXDIS Timing during Normal Operation
VDD
10us (min)
TXDIS
TXFAULT
TXFAULT enable
(without
OPTALM)
TXFAULT disable
TXFAULT enable (+ OPTALM)
LD current
2ms
t_off: 10us (max)
t_on: 1ms (max)
Temperature gap detection
Normal Initialize Procedure: 160ms (typ)
Acceleration Procedure: 1ms (max)
7.5 TXFAULT Detection / Reset with Recovery
VDD
TXDIS
FAULT
t_reset: 10us
(min)
TXFAULT
Acceleration selected
LD current
Depends on detected ALM
(see Table 5-1)
APC Feedback
Power-up Sequence
t_init: 160ms (max)
<MS0189-E-01>
-26-
2004/5
ASAHI KASEI
[AK2573A]
7.6 TXFAULT Detection / Reset without Recovery
VDD
TXDIS
t_reset: 10us
(min)
FAULT
TXFAULT
LD current
Depends on detected ALM
(see Table 5-1)
t_fault
TX_FAULT with OPTALM
Accelerated delay time is selected: 2ms (typ)
Normal delay time is sekected: 160ms (typ)
<MS0189-E-01>
-27-
2004/5
ASAHI KASEI
[AK2573A]
8. I2CTM I/F
8.1 Memory Map
Table 8-1 shows the EEPROM / Register address map. Accessto memory (EEPROM / registers) is done via the I2CTM
I/F format.
WP (Write Protect) may limit the access of memory as shown in Table 8-2.
Table 8-1 Memory map
Device Address Device Address-1
A0h
1010
Device Address-2
000
A0h
1010
000
A2h
1010
001
A4h
1010
010
A6h
1010
011
A6h
1010
011
A8h
1010
100
A8h
1010
100
A8h
1010
100
Address
00000000 to
01111111
10000000 to
11111111
00000000 to
11111111
00000000 to
11111111
00000000 to
01111111
10000000 to
11111111
00000000 to
00011001
00011010 to
11111110
11111111
Table 8-2 Memory access limitation with WP
Item
WP = “L”
Device Address
1010xxx
ACK (Note 1)
when receive device address
EEPROM / Register
Full access
Access
Operating mode
Full
Page Write
16 byte (without registers)
Sequential Read
from 00000000000 to 01111111111
Registers Access
Random access only
Note 1) During EEPROM Write operation, no ACK is generated.
<MS0189-E-01>
-28-
Data
User Area
(EEPROM, 1kbit)
No memory
No memory
Adjustment data
(EEPROM, 3kbit)
No memory
Registers
No memory
AK2573A Operation mode
change
WP = “H”
1010000
when receive device address
User area only (read only)
Self runnig mode only
from 00000000 to 01111111
-
2004/5
ASAHI KASEI
[AK2573A]
8.2 Read/Write Operation
8.2.1 Byte Write
SDA
0 0
1 0 1 0
S
T
A
R
T
Device
Address-1
Device
R/
Address-2 W
0
Address
(MSB First)
A
C
K
0
Data
(MSB First)
A
C
K
A
C
K
S
T
O
P
8.2.2 Page Write
AK2573A is capable of 16-byte page write.
SDA
0 0
1 0 1 0
S
T
A
R
T
Device
Address-1
R/
Device
Address-2 W
Address
(MSB First)
A
C
K
0
0
0
A
C
K
A
C
K
A
C
K
Data (Address)
Data (Address + 1)
....
0
A
C
K
0
A S
C T
K O
P
Data (Address + n)
8.2.3 Current Address Read
The internal address counter maintains the last address accessed during the last read or write operation, incremented
by one. The roll over address is changed WP setting. Refer to Table 7-2 in detail.
SDA
1 0
1 0 1 0
S
T
A
R
T
Device
Address-1
Device
R/
Address-2 W
1
N
O
A
C
K
Data
(MSB First)
A
C
K
S
T
O
P
8.2.4 Random Read
A random read requires a “dummy” byte write sequence to specified “Address”. After receive the ACK from AK2573A,
perform “current address read” (see 8.2.2).
SDA
0 0
1 0 1 0
S
T
A
R
T
Device
Address-1
Device
R/
Address-2 W
0
*1
A S
C T
K A
R
T
Address
(MSB First)
A
C
K
Dummy Write
1 0
1 0 1 0
Device
Address-1
Device
R/ A
Address-2 W C
K
1
Data
(MSB First)
N S
O T
A O
C P
K
*1: Don't care when WP="H"
8.2.5 Sequential Read
Sequential read can be initiated as ether“Current Address Read” or “Random Read”. After issuing either of them, the
AK2573A continues to output data for each ACK received.
SDA
....
1 0
Device
R/ A
Address-2 W C
K
<MS0189-E-01>
0
Data-1
(MSB First)
A
C
K
0
A
C
K
Data-2
-29-
....
0
A
C
K
1
Data-n
N S
O T
A O
C P
K
2004/5
ASAHI KASEI
[AK2573A]
8.2.6 Data Change
The SDA pin is normally pulled high with 4.7k to 10kΩ. Data on the SDA pin may change only during SCL low time
period. Data changes during SCL high periods will indicate a start or stop condition.
SCL
SDA
Data
Stable
Data
Change
8.2.7 Start / Stop Condition
Start Condition: A high-to-low transition of SDA with SCL high is a start condition that must precede any other
command.
Stop Condition: A high-to-low transition of SDA with SCL high is a stop condition.
SCL
SDA
START
<MS0189-E-01>
STOP
-30-
2004/5
ASAHI KASEI
[AK2573A]
8.3 EEPROM
EEPROM memory map is shown in Table 8-3, 8-4 and 8-5.
EEPROM access islimited with WP pin and Operation mode (refer to Table 9-1, for more information).
WP = “L”: Full access
WP = “H”: User area only with read only
(Note) The AKM factory adjusted data are stored in advance at address (Device Address2 = 011, Address=60h) for
the offset of the on-chip temperature sensor. If such excess temperature stress is to be applied to this device
which exceeds a guaranteed EEPROM data retention conditions ( for 10 years at 85℃), it is important to read
the pre-determined value in advance and to re-write the same data back into EEPROM after an exposure to
the excess temperature environment. Even if the exposure time is shorter than the retention time, any
accelerated temperature stress tests (such as baking) are performed, it is recommended to read the pre-set
data first and to re-write it after the tests.
Table 8-3 EEPROM Address MAP
Device
Address DATA (D7-D0)
Address
A0h
00h (0)
User Area
(1kbit)
～
7Fh (127)
A0h
80h (128)
No Memory
～
FFh (255)
A2h
00h (0)
～
FFh (255)
A4h
00 h(0)
E_DAC1_TC
Temperature data for I-DAC1 (1kbit)
～
7F h(127)
A4h
80h (128)
E_DAC2_TC
Temperature data for I-DAC2 (1kbit)
～
FFh (255)
A6h
00h (0)
E_DUTY_TC (5bit)
Temperature
data
for
Duty
～
Adjustment (256bit)
1Fh(31)
A6h
20h (32)
E_APC_TRGT_TC (5bit)
Temperature data for APC FB
～
reference (R_APC_TARGT) (256bit)
3Fh (63)
A6h
40h (64)
MSB 4bit: E_CURRALM_DAC1_TC
LSB 4bit: E_CURRALM_DAC2_TC
～
Temperature data for CURRALM
5Fh (95)
(256bit)
A6h
60h (96)
Adjustment data
(256bit)
～
7Fh (255)
<MS0189-E-01>
-31-
Initial
Value
00h
Remark
00h
Addressing with R_TEMP
(1.5℃ step)
00h
Addressing with R_TEMP
(1.5℃ step)
00h
Addressing with MSB 5bit of
R_TEMP
(6℃ step)
Addressing with MSB 5bit of
R_TEMP
(6℃ step)
Addressing with MSB 5bit of
R_TEMP
(6℃ step)
00h
FFh
see Table 8-4 and 8-5
2004/5
ASAHI KASEI
[AK2573A]
Table 8-4 Adjustment Data Area (Device Address-2 = 011)
Address
EEPROM
Function
E_VRFTRIM[7:4]
60h
Oscillator Frequency
E_TEMP_OFFSET[3:0] 60h
Temperature sensor offset
E_APC_FF_SET[7:6]
61h
APC FF Setting
E_APC_FB_SET[5:4]
61h
APC FB Setting
E_APC_INIT_SET[3]
61h
APC FB Initial Setting
Bit
4
4
2
2
1
E_SFP[2]
61h
SFP Setting
1
E_DAC1_GAIN[1]
61h
I-DAC1 Gain
1
E_DAC2_GAIN[0]
61h
I-DAC2 Gain
1
E_TEMP_DET[5]
62h
E_TIMER_OPTALM[4]
62h
E_ALM_POL[3]
62h
Temperature compensation 1
at shutdown release ON/OFF
Delay time of TXFAULT 1
detection with OPTALM
ALM Polarity
1
E_OPTALM[1:0]
62h
OPTALM Reference Level
E_TEMP_WIN[6:0]
63h
E_DAC_FBRT_FIX[6:0]
65h
E_DATAALM_MASK[0] 67h
Temperature Difference
7
Detection Level
APC FB Dual Feedback 7
Ratio
DATAALM mask
1
E_PDGAIN[5:0]
E_TEMPALM[6:0]
PDGAIN
TEMPALM Level
68h
6Ch
Table 8-5 EEPROM Map (Adjustment Data Area)
Address
D7
D6
D5
D4
60h
VREFTRIM
61h
APC_FF_SET
APC_FB_SET
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh –
7Fh
<MS0189-E-01>
TEMP_
DET
2
6
7
Initial Value
Remark
Factory Setting
Factory Setting
00
see Table 4-4
00
see Table 4-4
0
0: No Initial Setting
1: Initial Setting
0
0: No SFP Support
1: SFP Support
0
0: Gain = 1/2
1: Gain = 1
0
0: Gain = 1/2
1: Gain = 1
1
0: OFF
1: ON
0
0: 160ms
1: 2ms
0
0: “H”
1: “L”
00
00: 1/3, 01: 1/4
10: 1/6, 11: 1/7
00h
see section 6.2
00h
see section 4.3
0
0: DATAALM Valid
1: DATAALM Invalid
see Table 4-2
see Table 4-9
00h
00h
D3
APC_
INIT_SET
TIMER_
ALM_
OPTALM
POL
TEMP_WIN
D2
D1
D0
TEMP_OFFSET
SFP
DAC1_
DAC2_
GAIN
GAIN
OPTALM
DAC_FBRT_FIX
DATAALM_
MASK
PDGAIN
TEMPALM
Reserved (for AKM Test)
-32-
2004/5
ASAHI KASEI
[AK2573A]
8.4 Register
Register memory map is shown in Table 8-6 and 8-7. Register access is limited with WP pin and Operation mode
(refer to Fig 9-1, for more information).
Table 8-6 Register (Device Address = A8h)
Address
Register
Function
R_VRFTRIM[7:4]
00h
Oscillator Frequency
R_TEMP_OFFSET[3:0]
00h
Temperature sensor offset
R_APC_FF_SET[7:6]
01h
APC FF Setting
R_APC_FB_SET[5:4]
01h
APC FB Setting
R_APC_INIT_SET[3]
01h
APC FB Initial Setting
Bit
4
4
2
2
1
Type
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
Remark
see Table 4-4
see Table 4-4
0: No initial Setting
1: Initial Setting
0: No SFP Support
1: SFP Support
0: Gain = 1/2
1: Gain = 1
0: Gain = 1/2
1: Gain = 1
0: OFF
1: ON
0: 160ms
1: 2ms
0: “H”
1: “L”
00: 1/3, 01: 1/4
10: 1/6, 11: 1/7
see section 6.2
R_SFP[2]
01h
MSA(SFP) Setting
1
U
R/W
R_DAC1_GAIN[1]
01h
I-DAC1 Gain
1
U
R/W
R_DAC2_GAIN[0]
01h
I-DAC2 Gain
1
U
R/W
R_TEMP_DET[5]
02h
U
R/W
R_TIMER_OPTALM[4]
02h
U
R/W
R_ALM_POL[3]
02h
Temperature compensation 1
at shutdown release ON/OFF
Delay time of TXFAULT 1
detection with OPTALM
ALM Polarity
1
U
R/W
R_OPTALM[1:0]
02h
OPTALM Reference Level
2
U
R/W
R_TEMP_WIN[6:0]
03h
7
U
R/W
R_DAC1_FBRT[6:0]
R_DATAALM_MASK[0]
05h
06h
Temperature Difference
Detection Level
APC FB Ratio for I-DAC1
DATAALM Mask
7
1
U
U
R/W
R/W
R_DAC2_FBRT[6:0]
R_PDGAIN[5:0]
R_TEMPALM[6:0]
R_TEMP[6:0]
R_TEMP_STDW[6:0]
07h
08h
09h
0Ah
0Bh
7
6
7
7
7
U
U
U
U
U
see section 4.3
0: DATAALM Valid
1: DATAALM Invalid
R/W see section 4.3
R/W see Table 4-2
R/W see Table 4-9
R/(W) see Table 4-9
R/(W) see section 6.2
0Ch
8
0Dh
8
0Eh
9
11h
9
12h
9
13h
8
14h
8
15h
5
16h
4
16h
4
17h
5
18h1Dh
Note 1: The data format of read / write via I2CTM (8bit) is shown in Fig 8-1.
Note 2: R_DAC1 = R_DAC1_FF + R_DAC1_FB, R_DAC1>=0,
Note 3: R_DAC2 = R_DAC2_FF + R_DAC2_FB, R_DAC2 >= 0
U
U
S
S
S
U
U
U
U
U
U
-
R/W
R/W
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/W
R/W
R/W
R/W
-
R_DAC1_FF[7:0]
R_DAC2_FF[7:0]
R_APC_FB[8:0]
R_DAC1_FB[8:0]
R_DAC2_FB[8:0]
R_DAC1[7:0]
R_DAC2[7:0]
R_APC_TRGT[4:0]
R_CURRALM_DAC1[7:4]
R_CURRALM_DAC2[3:0]
R_DUTY[4:0]
AKM Test
<MS0189-E-01>
APC FB Ratio for I-DAC2
PDGAIN
TEMPALM Level
Detected Temperature
Temperature at Shutdown
request
I-DAC1 FF
I-DAC2 FF
APC FB
I-DAC1 FB
I-DAC2 FB
I-DAC1
I-DAC2
APC Reference
CURRALM for I-DAC1
CURRALM for I-DAC2
Duty Adjust
Test for AKM
-33-
Note 2
Note 3
Note 1
Note 1
Note 1
Note 2
Note 3
see Table 4-3
see section 5.2
see section 5.2
2004/5
ASAHI KASEI
[AK2573A]
Note 4:
(1) R/W
R: Read Only.
R/(W): Read / Write, Write data may be changed by internal operation.
R/W: Read/Write, Write data is hold unless re-writing or operation mode changing. All adjustment would be
done by R/W registers.
(2) Data Type
U: Unsigned, S: Signed (2’s Complement)
Table 8-7 Register Map
Address
D7
D6
D5
D4
00h
VREFTRIM
01h
APC_FF_SET
APC_FB_SET
02h
TEMP_
DET
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h 1Dh
<MS0189-E-01>
D3
APC_
INIT_SET
TIMER_
ALM_
OPTALM
POL
TEMP_WIN
D2
D1
D0
TEMP_OFFSET
SFP
DAC1_
DAC2_
GAIN
GAIN
OPTALM
DAC1_FBRT
DATAALM_
MASK
DAC2_FBRT
PDGAIN
TEMPALM
TEMP
TEMP_STDW
DAC1_FF
DAC2_FF
APC_FB (see Fig 8-1)
DAC1_FB
DAC2_FB
DAC1
DAC2
CURRALM_DAC1
APC_TRGT
CURRALM_DAC2
DUTY
Reserved (for AKM test)
-34-
2004/5
ASAHI KASEI
[AK2573A]
Fig 8-1 The data format of signed 9 bit register
Register (9bit 2's complement)
Body (8bit)
Sign
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read Data via Digital I/F (8 bit)
(Sign + Body (MSB 7bit)
Write Data via Digital I/F (8 bit)
(Body 8bit, Negative Data can not be written)
9. Operation Mode
The AK2573A has 3 operating modes: Self-running, Adjustment and EEPROM mode.
9.1 Self-running Mode
Self-running mode is ready for normal operation after all adjustments are completed. In this mode, temperature
detection, EEPROM access and feeding current are automatically performed using the on-chip oscillator. The
AK2573A works in this mode after power-on.
9.2 Adjustment Mode
Adjustment mode is designed for training the LD characteristics. The AK2573A operates according to the register
settings set through the I2CTM I/F. During adjustment mode, R_SFP should be 0.
9.3 EEPROM Mode
EEPROM mode is used for storing LD characteristics into EEPROM.
9.4 MODE Control
The AK2573A operation modes are changed through the I2CTM interface. Table 9-1 shows the access limitation of
each operation mode and Table 9-2 shows the command to change operation mode.
Note: The I2CTM interface access is prohibited for 1ms after power-on or mode transfer to self-running mode.
Table 9-1 Access limitation of each operation mode
EEPROM Access
Operation mode
Read
Write
Self-running mode
○
×
(WP=”L”)
Adjustment mode
○
×
(WP=”L”)
EEPROM mode
○
○
(WP=”L”)
WP = “H”
○
×
Self-running mode only
(User Area Only)
Table 9-2 Operation mode change
Device Address R/W
1010100
W
1010100
W
1010100
W
Address
11111111
11111111
11111111
Read
○
○
○
×
Data
10100000
10100111
10101110
Register Access
Write
×
(except mode-change command)
○
×
(except mode-change command)
×
Operation mode
Self-running mode
Adjustment mode
EEPROM mode
9.5 Operation Mode Protection
When set WP = “H”, only self-running mode is selected.
<MS0189-E-01>
-35-
2004/5
ASAHI KASEI
[AK2573A]
10. Module Adjustment Example
Table 10-1 shows the module adjustment example.
Table 10-1 Module Adjustment Example
No.
Item
Contents
1
Go to Adjustment mode
Issues “Changing to Adjustment mode command” (see Table 9-2) via
I2CTM I/F.
2
SFP setting
Set R_SFP = 0 to avoid TXFAULT detection at adjustment mode.
3
APC setting
Set R_APC_FB_SET = ”00” and R_APC_FF=11. BIAS and MOD
current is set as “Open Loop”.
4
LD current adjustment
Set R_DAC1_GAIN and R_DAC2_GAIN, then adjust
R_APC_FF_DAC1 for modulation current and R_APC_FF_DAC2 for
BIAS current of LD.
5
Duty adjustment
Adjust R_DUTY for 50% duty of LD power, if necessary. After duty
adjustment, tune MOD and BIAS current by R_APC_FF_DAC1 and 2, if
necessary.
6-A
PDGAIN adjustment
Adjust R_PDGAIN for PDMON = 1V. Go to step-7.
If you cannot measure PDMON voltage, see step 6-B.
6-B
PDGAIN adjustment
Set R_APC_TRGT=100000 and R_PDGAIN=000000 (Gain=23.5dB).
Then set R_APC_FF_SET and R_APC_FB_SET as your configulation.
APC FB adjusts LD output automatically. Adjust R_PDGAIN for
normal LD output. R_APC_TRGT adjustment is for fine tunning of
optical power. Go to step-8.
7
APC FB setting
Set R_APC_TRGT = “10000”.
Set R_APC_FB_SET according to your configuration.
8
APC FB target
Adjust R_APC_TRGT to tunning LD output. LD output is adjusted
adjustment
automaticaaly according to the R_APC_TRGT.
9
Read temperature data
Read R_TEMP (on-chip temperature sensor detection temperature).
10
Estimate LD temperature (1) 2 or more temperature adjustment
characteristics
Do step 2 to 8 with different temperature and estimate LD current data of
look-up table.
11
12
(2) Single point adjustment
Calculate LD current data of look-up table with on-chip temperature
sensor gain (-1.49℃/LSB), R_TEMP and LD characteristics.
Write adjustment data to (1) Make the data for EEPROM.
EEPROM
(2) Issue mode change command to EEPROM.
(3) Write adjustment data to EEPROM.
(4) Read EEPROM data and verify it.
Self running mode
Issue mode change command to self-running. AK2573A operates
temperature detection, feed current in response to temperature, and a
feedback operation automatically according to the data in EEPROM.
<MS0189-E-01>
-36-
2004/5
ASAHI KASEI
[AK2573A]
Ⅶ. Circuit Example
Fig-A illustrates circuit example of AK2573A.
Fig-A Circuit Example
VCC = 3.3V +/- 0.2V
C11 C12 C13 C14
PD
RPD
LD
L1
CPD
R1
MODMON
TEST1
R2 = 12kΩ +/- 1%
R3 = R4 = R5 = R6 = 4.7kΩ～10kΩ
PDIN
AVDD
IBIAS
VSSBI
IBIAS
VSSBI
VSSMD
AK2573AVB
C1 = 1uF
TEMPALM
C12=C14=C16=C18=C20 = 0.01uF or 0.001uF
CURRALM
C11=C13=C15=C17=C19 = 0.1uF
OPTALM
DATAALM
TEST2
TXFAULT
DVDD
TXDIS2
TXDIS1
WP
CLKN
SCL
CLKP
TEST5
SEL
DVSS
DATAN
NC
TEST4
DATAP
TEST3
NC
R2
TEMPMON
BIASMON
TEST6
fpd = 1/ (2*π*RPD*CPD) = 1kHz～10kHz
R1 = 10Ω +/- 1%
BIAS
VSSDR
Open
L1: Ferrite Bead (Murata BLM18BD102)
AVSS
PDMON
VDDDR
C18
C1
SDA
Mod_def 2
C16
C15
For full access: GND
For write protection: Open or VDD
R4
R5
Tx_Fault
LVPECL I/F
(see below)
R3
Mod_def 1
NC
C17
IMOD
VDDMD
NC
IMOD
IMODN
C19
IMODN
VSSMD
C20
VCC or GND
Normal Operation with Open: Pull-down
Shutdown Operation with Open: Pull-up
R6
Tx_Disable
LVPECL I/F
DATA Only
AC Coupling
TD + C101
TD -
DATAP
DATA Only
DC Coupling
R111
TD +
R101
C102
DATAN
SEL
R113
TD R114
CLKN
R101 = 100Ω
C101 = C102 >= 0.01uF
DATAP
R123
SEL
DATAN
R124
SEL
R125
CLK +
CLKN
R127
R111 = R113 = 130Ω
R112 = R114 = 82Ω
CLK R128
<MS0189-E-01>
R122
TD -
DATAN
CLKP
VDD or Open
R121
TD +
DATAP
R112
CLKP
VDD or Open
DATA & CLK
DC Coupling
-37-
CLKP
R126
CLKN
R121 = R123 = R125 = R127 = 130Ω
R122 = R124 = R126 = R128 = 82Ω
2004/5
ASAHI KASEI
[AK2573A]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice.
Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use
of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other
hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the
express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for
applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether
directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which
must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places
the product with a third party to notify that party in advance of the above content and conditions, and the buyer or
distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
<MS0189-E-01>
-38-
2004/5