PANASONIC AN8018SA

Voltage Regulators
AN8018SA
1.8-volt 2-channel step-up, step-down,
or inverting DC-DC converter control IC
Unit: mm
■ Overview
The AN8018SA is a two-channel PWM DC-DC converter control IC that features low-voltage operation.
This IC can obtain the step-up, step-down and inverting voltages with a small number of external components.
The minimum operating voltage is as low as 1.8 V so
that it can operate with two dry batteries. In addition,
since it uses the 16-pin surface mounting type package
with 0.65 mm pitch, it is suitable for miniaturized highly
efficient potable power supply.
9
+0.10
0.15 −0.05
6.4±0.3
4.4±0.2
(1.0)
0° to 10°
1
(0.225)
8
0.65
+0.10
0.22 − 0.05
1.2±0.2
0.5±0.2
0.1±0.1
■ Features
5.0±0.2
16
Seating plane
• Wide operating supply voltage range (1.8 V to 14 V)
• Incorporating a high precision reference voltage circuit
SSOP016-P-0225A
(allowance: ± 2%)
• Control in a wide output frequency range is possible
(20 kHz to 1 MHz).
• Built-in wideband error amplifier (single gain bandwidth
10 MHz typical)
• Built-in timer latch short-circuit protection circuit
(charge current 1.1 µA typical)
• Incorporating the under-voltage lock-out circuit (U.V.L.O.)
(circuit operation-starting voltage 1.67 V typical)
• Dead-time is variable.
• Flatness of switching current can be obtained by staggering the turn-on timing of each channel.
• Built-in unlatch function
When DT1 pin is low level, or DT2 pin is high level, independent turn-off is possible.
• Incorporating a on/off control function
(active-high control input, standby mode current: 5 µA maximum)
• Parallel operation is possible.
• Output block
• Totem pole 1 output
• Output source-current: −50 mA maximum (Constant current output with a less supply voltage fluctuation is
possible by connecting an external resistor to pin 11)
• Output sink-current: +80 mA maximum
• Open-collector 1 output
• Output current: 50 mA maximum
■ Applications
• LCD displays, digital still cameras, and PDAs
1
AN8018SA
Voltage Regulators
On/ 15
off
FB1
0.9 V
IN+2
7
0.2 V
PWM1
Unlatch1
Out1
U.V.L.O.
H
L
Latch
R
Q
S
0.9 V
Error amp. 2
14
VREF
VREF
5
13
6
Reference 1.19 V Triangular wave
voltage source
oscillation
On/off
control
Error amp. 1
IN−1 4
IN+1
3
FB2
DT1
OSC
1
16
9
VCC
VREF
■ Block Diagram
S.C.P.
comp.
0.22 V
VCC
11
RB2
VREF
PWM2
0.9 V
10
Out2
0.9 V
1.19 V
VREF
Unlatch2
GND
DT2
S.C.P.
2
12
8
■ Pin Descriptions
Pin No. Symbol
1
2
3
2
OSC
S.C.P.
IN+1
Description
Pin No. Symbol
Description
Pin for oscillation timing resistor
8
GND
Grounding pin
and capacitor connection
9
VCC
Power supply voltage application pin
Pin for connecting the time constant set-
10
Out2
Out2 block push-pull type output pin
ting capacitor for short-circuit protection
11
RB2
Out2 block output source current
setting resistor connection pin
Error amplifier 1 block noninverting
input pin
12
DT2
PWM2 block dead-time setting pin
4
IN−1
Error amplifier 1 block inverting input pin
13
FB2
Output pin of error amplifier 2 block
5
FB1
Output pin of error amplifier 1 block
14
IN+2
Error amplifier 2 block inverting input
6
DT1
PWM1 block dead-time setting pin
7
Out1
Out1 block open-collector type
15
Off
output pin
16
VREF
pin
On/off control pin
Reference voltage output pin
Voltage Regulators
AN8018SA
■ Absolute Maximum Ratings
Parameter
Supply voltage
Off terminal allowable application voltage
Symbol
Rating
Unit
VCC
15
V
VOFF
15
V
IN+1 terminal allowable application voltage
*2
VIN−1
6
V
IN−1 terminal allowable application voltage
*2
VIN−1
6
V
IN+2 terminal allowable application voltage
*2
VIN+2
6
V
VOUT
15
V
Supply current
ICC

mA
Out1 terminal output current
IO
+50
mA
Out2 terminal source current
ISO(OUT)
−50
mA
Out2 terminal sink current
ISI(OUT)
+80
mA
PD
135
mW
Operating ambient temperature
Topr
−30 to +85
°C
Storage temperature
Tstg
−55 to +150
°C
Out1 terminal allowable application voltage
Power dissipation
*1
Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned.
For the circuit currents, '+' denotes current flowing into the IC, and '−' denotes current flowing out of the IC.
2. Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C.
3. *1: Ta = 85 °C. For the independent IC without a heat sink. Note that applications must observe the derating curve for the
relationship between the IC power consumption and the ambient temperature.
*2: VIN−1 , VIN-1 , VIN+2 = VCC when VCC < 6 V.
■ Recommended Operating Range
Parameter
Symbol
Range
Unit
Supply voltage
VCC
1.8 to 14
V
Off control terminal application voltage
VOFF
0 to 14
V
Output source current
ISO(OUT)
−40 (minimum)
mA
Output sink current
ISI(OUT)
70 (maximum)
mA
Timing resistance
RT
1 to 51
kΩ
Timing capacitance
CT
100 to 10 000
pF
Oscillation frequency
fOUT
20 to 1 000
kHz
Short-circuit protection time constant
setting capacitance
CSCP
1 000 (minimum)
pF
RB
180 to 15 000
Ω
Output current setting resistance
■ Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.166
1.19
1.214
V
Reference voltage block
Reference voltage
VREF
IREF = − 0.1 mA
Input regulation with input fluctuation
Line
VCC = 1.8 V to 14 V

15
30
mV
Load regulation
Load
IREF = − 0.1 mA to −1 mA
−20
−5

mV
3
AN8018SA
Voltage Regulators
■ Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VUON
1.59
1.67
1.75
V
Input offset voltage
VIO
−6

+6
mV
Common-mode input voltage range
VICR
0.3

0.7
V
IB1
− 0.6
− 0.2

µA
High-level output voltage 1
VEH1
0.83
0.93
1.03
V
Low-level output voltage 1
VEL1


0.2
V
Output source current 1
ISO(FB)1
−61
−47
−33
µA
Output sink current 1
ISI(FB)1
33
47
61
µA
Input threshold voltage
VTH
1.16
1.19
1.22
V
Input bias current 2
IB2

0.2
0.8
µA
High-level output voltage 2
VEH2
0.83
0.93
1.03
V
Low-level output voltage 2
VEL2


0.2
V
Output source current 2
ISO(FB)2
−61
−47
−33
µA
Output sink current 2
ISI(FB)2
33
47
61
µA
VTH(OSC)
0.8
0.9
1.0
V
185
205
225
kHz
75
80
85
%
U.V.L.O. block
Circuit operation start voltage
Error amplifier 1 block
Input bias current 1
Error amplifier 2 block
Oscillator block
Output off threshold voltage
Output 1 block
Oscillation frequency 1
fOUT1
Output duty ratio 1
Du1
RT = 12 kΩ, CT = 330 pF
VO(SAT)
IO = 30 mA


0.5
V
IOLE
VCC = 14 V


1
µA
Oscillation frequency 2
fOUT2
RT = 12 kΩ, CT = 330 pF
185
205
225
kHz
Output duty ratio 2
Du2
72
77
82
%
High-level output voltage
VOH
IO = −10 mA, RB = 820 Ω
1.4


V
Low-level output voltage
VOL
IO = 10 mA, RB = 820 Ω


0.2
V
Output source current
ISO(OUT) VO = 0.7 V, RB = 820 Ω
−40
−30
−20
mA
Output sink current
ISI(OUT)
VO = 0.7 V, RB = 820 Ω
20


mA
Pull-down resistance
RO
20
30
40
kΩ

0.28
0.30
V
Output saturation voltage
Output leak current
Output 2 block
PWM1 block
VT0-1
Output full-on input threshold
voltage 1
VT100-1
Duty = 100%
0.65
0.72

V
IDT1
VDT1 = 0.4 V
−1.1
− 0.5

µA
Input current 1
4
Duty = 0%
Output full-off input threshold
voltage 1
Voltage Regulators
AN8018SA
■ Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
0.65
0.72

V

0.28
0.30
V
−1.1
− 0.5

µA
VTHUL1
0.15
0.20
0.25
V
VTHUL2
0.8
0.9
1.0
V
Input standby voltage
VSTBY

60
120
mV
Input threshold voltage 1
VTHPC1
0.8
0.9
1.0
V
Input threshold voltage 2
VTHPC2
0.17
0.22
0.27
V
Input latch voltage
VIN

60
120
mV
Charge current
ICHG
PWM2 block
Output full-off input threshold
voltage 2
VT0-2
Output full-on input threshold
voltage 2
VT100-2
Input current 2
IDT2
Duty = 0%
Duty = 100%
VDT2 = 0 V
Unlatch circuit 1 block
Input threshold voltage 1
Unlatch circuit 2 block
Input threshold voltage 2
Short-circuit protection circuit block
VSCP = 0 V
−1.43
−1.1 − 0.77
µA
0.8
1.0
1.3
V
On/off control block
Input threshold voltage
VON(TH)
Whole device
Output off consumption current
ICC(OFF)
RB = 820 Ω, duty = 0%

5.7
8.0
mA
Latch mode consumption current
ICC(LA)
RB = 820 Ω

5.6
7.8
mA
Standby current
ICC(SB)


1
µA
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
−1

+1
%
IOC

−11

mA
VR

0.8

V
− 0.3

Reference voltage block
VREF temperature characteristics
Over-current protection drive current
VREFdT
Ta = −30°C to +85°C
U.V.L.O. block
Reset voltage
Error amplifier 1/2 blocks
VTH temperature characteristics
VTHdT
Ta = −30°C to +85°C
+ 0.3 mV/°C
Open-loop gain
AV

57

dB
Single gain bandwidth
fBW

10

MHz
Frequency supply voltage
characteristics
fdV
−1

+1
%
Frequency temperature characteristics
fdT
−3

+3
%
Output 1/2 blocks
5
AN8018SA
Voltage Regulators
■ Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VB

0.36

V
VTHL

1.19

V
IOFF

23

µA
Output 2 block
RB terminal voltage
Short-circuit protection block
Comparator threshold voltage
On/off control block
Off terminal current
■ Terminal Equivalent Circuits
Pin No.
Equivalent circuit
1
VCC
Latch
0.2 V
S
R
Q
1
2
VCC
1.1 µA
Latch
S
R
1.19 V
2 kΩ
Q
Output
cut-off
Description
I/O
OSC:
The terminal used for connecting a timing capacitor/resistor to set oscillation frequency.
Use a capacitance value within the range of 100 pF
to 10 000 pF and a resistance value within the range
of 3 kΩ to 30 kΩ. Use an oscillation frequency in the
range of 20 kHz to 1 MHz. When operating the
circuit in parallel and synchronously, the channel 2
output stops when this pin becomes 0.9 V or more.
(Refer to the "Application Notes, [7]" section.)
O
S.C.P.:
The terminal for connecting a capacitor to set the
time constant of the timer latch short-circuit protection circuit. Use a capacitance value in the range
of 1 000 pF or more. The charge current ICHG is
1.1 µA typical.
O
IN+1:
The noninverting input pin for error amplifier 1
block.
I
IN−1:
The inverting input pin for error amplifier 1 block.
I
FB1:
The output pin for error amplifier 1 block.
The source current is −47 µA and the sink current
is 47 µA.
Correct the frequency characteristics of the gain
and the phase by connecting a resistor and a capacitor between this terminal and GND.
O
2
3
VCC
4
4
5
100 Ω
100 Ω
47 µA
IN+1
IN−1
OSC
47 µA
5
6
3
PWM
Voltage Regulators
AN8018SA
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
6
VCC
FB1 OSC
PWM
0.2 V
6
7
VCC
7
8
8
9
9
I/O
DT1:
The pin for setting channel 1 output maximum
duty ratio.
If this terminal is set at a voltage of 0.20 V or less,
FB1 terminal becomes low-level voltage and the
protective function for channel 1 output shortcircuit will stop (Unlatch function).
I
Out1:
The pin is open-collector type output terminal.
The absolute maximum rating of output current is
+50 mA.
O
GND:
Grounding terminal

VCC:

The supply voltage application terminal
Use the operating supply voltage in the range of
1.8 V to 14 V.
10
VCC
RB2
ISO(OUT)
10
30 kΩ
11
Description
VCC
Out2
Out2:
The pin is push-pull type output terminal.
The absolute maximum rating of output source
current is −50 mA.
The absolute maximum rating of output sink current is +80 mA.
A constant current output with less fluctuation
with power supply voltage and dispersion can be
obtained by the resistor externally attached to RB2
pin.
VRB2
ISO(OUT)2 = 68 ×
[A]
RB2
O
RB2:
The pin for connecting a resistor for setting channel 2 output current.
Use a resistance value in the range of 180 Ω to 1.1
kΩ.
The terminal voltage is 0.36 V (at RB2 = 820 Ω).
I
120 Ω
11
7
AN8018SA
Voltage Regulators
■ Terminal Equivalent Circuits (continued)
Pin No.
Equivalent circuit
12
VCC
0.9 V
FB2 OSC
0.9 V
PWM
12
13
VCC
47 µA
OSC
IN+2
PWM
47 µA
1.19 V
13
14
VCC
14
Description
I/O
DT2:
The pin for setting channel 2 output maximum
duty ratio.
If this terminal is set at a voltage of 0.9 V or more,
FB2 terminal becomes high-level voltage and the
protective function for channel 2 output shortcircuit will stop (Unlatch function).
I
FB2:
The output pin for error amplifier 2 block.
The source current is −47 µA and the sink current
is 47 µA.
Correct the frequency characteristics of the gain
and the phase by connecting a resistor and a capacitor between this terminal and GND.
O
IN+2:
The noninverting input pin for error amplifier 2
block.
I
Off:
The terminal for on/off control.
High-level input: Normal operation (VOFF > 1.3
V)
Low-level input: Standby state (VOFF < 0.8 V)
The total current consumption in the standby state
can be suppressed to a value 1 mA or less.
I
VREF:
The output terminal for the internal reference
voltage.
The reference voltage is 1.19 V (allowance: ± 2%) at
VCC = 2.4 V and IREF = − 0.1 mA.
Connect a capacitor of 0.01 µF or more between
VREF and GND for phase compensation.
O
100 Ω
1.19 V
15
30 kΩ
15
Internal circuit
start/stop
60 kΩ
16
VCC
16
8
Voltage Regulators
AN8018SA
■ Usage Notes
[1] The loss P of this IC increases in proportion to the supply voltage. Use the IC so as not to exceed the allowable
power dissipation of package PD .
Reference formula:
P = VO(SAT)1 × IOUT1 × Du1 + (VCC − VBEQ2) × ISO(OUT) × Du2 + VCC × ICC < PD
VO(SAT)1 : Out1 terminal saturation voltage (0.5 V maximum at IOUT1 = 30 mA)
IOUT1
: Out1 terminal output current (= {VCC − VBEQ1− VO(SAT)1} / RO1)
Du1
: Output1 duty ratio
VBEQ2 : Base-emitter voltage of NPN transistor Q2
ISO(OUT) : Out2 terminal output source current
(set by RB, ISO(OUT) = 40 mA maximum at RB2 = 820 Ω)
Du2
: Output2 duty ratio
ICC
: VCC terminal current (8.0 mA maximum but at VCC = 2.4 V)
[2] Since the output 2 of the AN8018SA is assuming the bipolar transistor driving, it is necessary to pay attention to
the following points when directly driving n-channel MOSFET.
1. Select an n-channel MOSFET having a low input
capacitance
The AN8018SA is of the constant-current (50 mA
maximum) output source-current type circuit assuming the bipolar transistor driving. Also, its sink current capability is around 80 mA maximum. For those
reason, it is necessary to pay attention to the increase
of loss due to the extension of the output rise time and
the output fall time.
If any problem arises, there is a method to solve it
by amplifying with inverters as shown in figure 1.
2. Select an n-channel MOSFET having a low gate
threshold value
The output high-level voltage of Out2 pin of the
AN8018SA is VCC −1.0 V minimum, so that it is
necessary to select a low VT MOSFET having a sufficiently low on-state resistance in accordance with the
using operating supply voltage.
If a larger VGS is desired, there is a method to apply
the double-voltage of the input to the IC's VCC pin by
using the transformer as shown in figure 2.
SBD
VIN
VOUT
10
Out2
Figure 1. Output boost circuit example
SBD
VIN
VCC
VOUT
SBD
9
10
Out2
VCC ≈ 2 × VIN − VD
Figure 2. Gate drive voltage increasing method
[3] In order to realize a low noise and high efficiency, a care should be taken in the following points in designing the
board layout.
1. The wiring for ground line should be taken as wide as possible and grounded separately from the power system.
2. The input filter capacitor should be arranged in a place as close to VCC and GND pin as possible so as not to
allow switching noise to enter into the IC inside.
3. The wiring between the Out terminal and switching device (transistor or MOSFET) should be as short as possible
to obtain a clean switching waveform.
4. In wiring the detection resistor of the output voltage, the wiring for the low impedance side should be longer.
[4] There is a case in which this IC does not start charging to the S.C.P. capacitor when the output is short-circuited
due to the malfunction of U.V.L.O. circuit biased by VCC that has ripples generated by turning on and off of the
switching transistor. The allowable range of the VCC ripple is as shown in the following figure. Reduce the VCC ripple
by inserting a capacitor near the VCC terminal and GND terminal of this IC so that the VCC ripple is in this allowable
range. However, this allowable range is design reference value and not the guaranteed value.
9
AN8018SA
Voltage Regulators
■ Usage Notes (continued)
[4] (continued)
VCC ripple allowable range
VCC ripple frequency (MHz)
100
10
2
Recommended
operating range
1
0.5
0.1
0
0.3
0.5
1
1.5
VCC ripple width (V[p-p])
■ Application Notes
[1] PD  Ta curves of SSOP016-P-0225A
PD  T a
700
Power dissipation PD (mW)
600
582
Glass epoxy board
(50 × 50 × t0.8 mm3)
Rth(j−a) = 171.8°C/W
500
400
Independent IC
without a heat sink
338
Rth( j−a) = 295.6°C/W
300
233
200
135
100
0
0
25
[2] Main characteristics
VREF temperature characteristics
50
75 85
100
125
Ambient temperature Ta (°C)
Frequency characteristics
1M
1.195
CT = 100 pF
fOUT (Hz)
VREF (V)
CT = 330 pF
1.190
100k
CT = 0.01 µF
1.185
−30
−10
10k
10
30
Ta (°C)
10
50
70
90
1k
10k
RT (Ω)
100k
Voltage Regulators
AN8018SA
■ Application Notes (continued)
[2] Main characteristics
ISO(OUT)  RB
ISI(OUT)  RB
70
90
80
60
VCC = 2.4 V
VCC = 14 V
70
VCC = 14 V
50
40
ISI(OUT) (mA)
ISO(OUT) (mA)
60
VCC = 7 V
30
VCC = 1.8 V
VCC = 2.4 V
50
VCC = 7 V
40
VCC = 1.8 V
30
20
20
10
10
1k
10k
0
100
100k
Du1  VDT1
Du2  VDT2
100
90
90
80
80
70
70
60
60
50
40
40
30
20
20
10
10
0.4
0.5
0.6
0.7
0
0.2
0.8
100k
50
30
0.3
10k
RB (Ω)
100
0
0.2
1k
RB (Ω)
Du2 (%)
Du1 (%)
0
100
VDT1 (V)
0.3
0.4
0.5
0.6
0.7
0.8
VDT2 (V)
ICC(OFF)  VCC
ICC(OFF)  RB
12
8
7
10
6
ICC(OFF) (mA)
ICC(OFF) (mA)
8
5
4
3
6
4
2
2
1
0
0
0
2
4
6
8
VCC (V)
10
12
14
100
1k
10k
RB (Ω)
11
AN8018SA
Voltage Regulators
■ Application Notes (continued)
[3] Timing chart (inside waveform)
VCC terminal
voltage waveform
1.6 V
1.22 V
Output short-circuit
S.C.P. terminal
voltage waveform
FB1
Channel 1
OSC
DT1
Out1 terminal
voltage waveform
Open-collector
output
Channel 2
FB2
Out 2 terminal
voltage waveform
Totem pole output
12
OSC
DT2
Voltage Regulators
AN8018SA
■ Application Notes (continued)
[4] Function descriptions
1. Reference voltage block
This block is composed of the band gap circuit, and outputs the temperature compensated 1.19 V reference
voltage. The reference voltage is stabilized when the supply voltage is 1.8 V or more. The reference voltage is also
used as the reference voltage for the error amplifier 2 block.
2. Triangular wave oscillation block
The sawtooth-waveform-like triangular wave having
VOSCH ≈ 0.7 V
a peak of approximately 0.7 V and a trough of approximately 0.2 V can be generated by connecting the timing
capacitor CT and resistor RT to the OSC terminal (pin 1).
The oscillation frequency can be freely set by the value of
VOSCL ≈ 0.2 V
CT and RT to be connected externally. The usable oscillation frequency is from 20 kHz to the maximum 1 MHz.
t1
t2
The triangular wave is connected with the inverting input
Boosting
Discharging
of PWM comparator for channel 1 side and the
charge
noninverting input of PWM comparator for channel 2 side
T
within the IC inside. Rough calculation of oscillation freFigure 1. Triangular wave oscillation waveform
quency can be calculated by the following equation.
1
1
fOSC ≈ −
≈ 0.8 ×
[Hz]
CT × RT × ln VOSCL
CT × RT
VOSCH
However, boosting charge time, over-shoot and under shoot quantities are not considered in the above equation.
And refer to the experimentally determined graph of the frequency characteristics provided in the main
characteristics section.
3. Error amplifier 1 block
The output voltage of DC-DC converter is detected by the PNP-transistor-input type error-amplifier and the
amplified signal is input to the PWM comparator.
Also, it is possible to perform the gain setting and the phase compensation arbitrarily by connecting a resistor
and a capacitor from the FB1 terminal (pin 5) to GND in series.
The output voltage VOUT1 can be set by making connection as shown in figure 2.
Case of step-up output
Case of inverting output
FB2 5
FB2 5
VREF
VREF VOUT1
R1
R3
R2
R4
IN+1 3
IN−1 4
VOUT1 =
Error amplifier 1
block
R1
R3
To PWM
comparator input R2
R4
R3 + R4
R2
·
· VREF
R4
R1 + R2
VOUT1
IN+1 3
Error amplifier 1
block
IN−1 4
To PWM
comparator input
VOUT1 = − (VREF − VIN−1) ·
VIN−1 = VREF ·
R1 + R2
+ VREF
R1
R4
R3 + R4
Figure 2. Connection method of error amplifier 1 block
4. Error amplifier 2 block
The output voltage of DC-DC converter is detected by the NPN-transistor-input type error-amplifier and the
amplified signal is input to the PWM comparator. The internal reference voltage 1.19 V is given to the noninverting
input.
13
AN8018SA
Voltage Regulators
■ Application Notes (continued)
[4] Function descriptions (continued)
4. Error amplifier 2 block (continued)
Also, it is possible to perform the gain setting
and the phase compensation arbitrarily by connecting a resistor and a capacitor from the FB2
terminal (pin 13) to GND in series.
The output voltage VOUT2 can be set by making connection as shown in figure 3.
VOUT2
FB2 13
Error amplifier 2
block
14
R1
R2
IN+2
1.19 V
VOUT2 = 1.19 ×
To PWM
comparator input
R1 + R2
R2
Figure 3. Connection method of error amplifier 2 block
(step-up output)
5.
Timer latch short-circuit protection circuit
This circuit protects the external main switching devices, flywheel diodes, and choke coils, etc. from
destruction or deterioration if overload or short-circuit condition of power supply output lasts for a certain time.
The timer latch short-circuit protection circuit detects the output level of the error amplifier. When the output
voltage of DC-DC converter drops and the FB1 terminal (pin 5) becomes 0.9 V or more, or the FB2 terminal
(pin 13) becomes 0.22 V or less, the low-level output is given and the timer circuit is actuated to start the charge
of the external protection-enable capacitor.
If the output of the error amplifier does not return to a normal voltage range by the time when the voltage of
this capacitor reaches 1.19 V, it sets the latch circuit, and cuts off the output drive transistor, and sets the dead-time
to 100%.
6. Low input voltage malfunction prevention circuit (U.V.L.O.)
This circuit protects the system from destruction or deterioration due to control malfunction when the supply
voltage is low in the transient state of power on/off.
The low input voltage malfunction prevention circuit detects the internal reference voltage which changes
according to the supply voltage level. Until the supply voltage reaches 1.67 V during its rise time, it cuts off the
output drive transistor, and sets the dead-time to 100%. At the same time, it holds the S.C.P. terminal (pin 2) and
DT1 terminal (pin 6) to low-level, and the OSC terminal (pin 1) and DT2 terminal (pin 12) to high-level.
7. PWM comparator block
The PWM comparator controls the on-period of the output pulse according to the input voltage. The PWM1
and PWM2 block are set in an opposite logic relation of each other and on-period of each output is staggered.
The PWM1 block turns on the output transistor during the period when the triangular wave of OSC terminal
(pin 1) is lower than any lower one of the FB1 (pin 5) terminal voltage and the DT1 (pin 6) terminal voltage.
The PWM2 block turns on the output transistor during the period when the triangular wave of OSC terminal
(pin 1) is higher than any higher one of the FB2 (pin 13) terminal voltage and the DT2 (pin 12) terminal voltage.
The maximum duty ratio is variable from the outside.
Also, the soft start which gradually extends on-period of the output pulse is activated by connecting a capacitor in parallel with the resistor-dividing for the maximum duty ratio setting.
8. Unlatch block
The unlatch circuit 1 block fixes the FB1 terminal (pin 5) at low level at the DT1 terminal (pin 6) is 0.20 V or
less. The unlatch circuit 2 block fixes the FB2 terminal (pin 13) at high-level at the DT2 terminal (pin 12) is 0.9
V or more. Consequently, by controlling the DT1 and the DT2 terminal voltages, it is possible to operate only one
channel or to start and stop each channel in any required sequence.
9. Output 1 block
This output circuit is open-collector type. The available output current is up to 50 mA. The breakdown voltage
of output terminal is 15 V.
10. Output 2 block
This block uses a totem pole type output circuit. By connecting the current setting resistor to the RB2 terminal,
it is possible to arbitrarily set a constant-current source-output having a small fluctuation with the supply voltage.
The available constant-current source-output is up to 50 mA.
14
Voltage Regulators
AN8018SA
■ Application Notes (continued)
[5] About logic of PWM block
The logic for channel 1 and channel 2 of this IC is reversed. Thereby an input current flatness is realized. At the
same time, noise can be suppressed to a lower level by staggering the turn on timing.
The PWM1 block turns on the output transistor during the period when the triangular wave of the OSC terminal
(pin 1) is lower than both of the FB1 (pin 5) terminal voltage and the DT1 (pin 6) terminal voltage.
The PWM2 block turns on the output transistor during the period when the triangular wave of OSC terminal
(pin 1) is higher than both of the FB2 (pin 13) terminal voltage and the DT2 (pin 12) terminal voltage.
(Refer to figure 4.)
OSC
FB1
DT1 and DT2
are omitted
FB2
Out1
(Open-collector output)
Out2
(Totem pole output)
Channel 1
Switching transistor
emitter current IE1
Channel 2
Switching transistor
collector current IC2
IE1 + IC2
SBD
+
10 Out2
VIN
IC2
IE1
−
Out1 7
SBD
Figure 4. PWM logic explanation chart
15
AN8018SA
Voltage Regulators
■ Application Notes (continued)
[6] Time constant setting method for timer latch short-circuit protection circuit
The constructional block diagram of protection latch circuit is shown in figure 6. The comparator for short-circuit
protection compares the error amplifier 1 output FB1 with the reference voltage of 0.9 V for channel 1 side, and the
error amplifier 2 output FB2 with the reference voltage of 0.22 V for channel 2 side at all the time.
When the load conditions of DC-DC converter output is stabilized, there is no fluctuation of error amplifier
output and the short-circuit protection comparator also keeps the balance. At this moment, the output transistor Q1 is
in the conductive state and the S.C.P. terminal is held to approximately 60 mV.
When the load conditions for channel 1 side suddenly change and high-level signal (0.9 V or more) is input from
the error amplifier 1 block to the short-circuit protection comparator, the short-circuit protection comparator outputs
the low-level signal to cut off the output transistor Q1. Also, when the load conditions for channel 2 side suddenly
change and low-level signal (0.22 V or less) is inputted from the error amplifier 2 block to the short-circuit protection
comparator, the short-circuit protection comparator outputs the low-level signal to cut off the output transistor Q1.
The capacitor CSCP connected to the S.C.P. terminal starts charging. When the external capacitor CSCP has been charged
to approximately 1.19 V with the constant current of approximately 1.1 µA, the latch circuit is set, the output terminal
is fixed to low level, and the dead-time is set to 100%. Once the latch circuit is set, the S.C.P. terminal is discharged
to approximately 40 mV, However, the latch circuit is not reset unless the power for the latch circuit is turned off or
restarted by the on/off control.
tPE
VSCP [V]
1.19 V = ICHG ×
CSCP
∴ tPE [s] = 1.08 × CSCP
1.19
When the power supply is turned on, the output is
considered to be short-circuited state so that the S.C.P.
terminal voltage starts charging. It is necessary to set the
external capacitor so as to start up the DC-DC converter
output voltage before setting the latch circuit in the later
stage. Especially, pay attention to the delay of the start-up
time when applying the soft-start.
FB1 5
IN+1 3
IN+2 14
0.06
t [s]
Figure 5. S.C.P. terminal charging waveform
Internal
reference
On/off
control
U.V.L.O.
Error amp.1
1.1 µA
IN−1 4
FB2 13
Short-circuit detection time tPE
0.9 V
High-level detection comp.
1.19 V
Error amp.2
S.C.P.
comp.
Q1
S.C.P. 2
1.19 V
0.22 V
Latch
R
Q
S
Figure 6. Short-circuit protection circuit
16
Output cut-off
Voltage Regulators
AN8018SA
■ Application Notes (continued)
[7] Parallel synchronous operation of multiple ICs
Multiple instances of this IC can be operated in parallel. If the OSC terminals (pin 1) and Off terminals (pin 15) are
connected to each other as shown in figure 7, the ICs will operate at the same frequency.
It is possible to operate this IC (the AN8018SA) with the two-channel totem pole output IC AN8017SA in parallel
synchronous mode.
1. Usage notes
1) The parallel synchronous operation with the single-channel AN8016SH/AN8016NSH is not possible.
2) The remote on/off with the single IC itself is not possible. Only the simultaneous remote on/off of all ICs is
possible.
H
L
9 VCC
Out2
10
11 RB2
DT2
12
13 FB2
IN+2
14
15 Off
16 VREF
Input
GND 8
9 VCC
GND 8
7
Out1
10 Out2
Out1 7
6
DT1
11 RB2
DT1 6
FB1 5
12 DT2
FB1 5
4
IN−1
13
IN−1 4
3
IN+1
S.C.P. 2
OSC 1
Off terminals
connected together
15 Off
14 IN+2
S.C.P. 2
IN+1 3
FB2
16 VREF
OSC 1
0.1 µF
OSC terminals
connected together
Figure 7. Slave operation circuit example
17
AN8018SA
Voltage Regulators
■ Application Notes (continued)
[7] Parallel synchronous operation of multiple ICs (continued)
16
2. About the operation of short-circuit protection at parallel synchronous operation
In the case of the operation in parallel, if the single output (or multiple outputs) of them is short-circuited and
the timer latch short circuit protection of the IC is operated, the output of other ICs will be also shut down, then
enter into latch mode.
In figure 8, if the IC-2 entered timer latch mode, Q1 turns on and the OSC terminal (pin 1) is fixed to
approximately 1.1 V and the oscillator stops.
Then channel 1 of IC-1 becomes low level than the DT1 terminal (pin 6) voltage or high-level voltage (0.9 V)
of the FB1 terminal set by terminal voltage, and then output 2 stops by PWM1 circuit of inside. The channel 2 stops
output 2 by oscillator high-level detection comparator.
And then, the IC-1 becomes short-circuit state and enters latch mode after a certain time.
It becomes the same operation in case of the IC-1 enters latch mode previously.
Channel 2 goes off
at high
IC-1
Oscillator high-level
detection comparator
16
1
0.9 V
IC-2
The IC entering to the lach mode,
Q1 turns on and,
VOSC = VREF − VCE(sat)
= becomes approximately 1.1 V
1
Q1
IC-2 side
output short-circuited
IC-2 latch
IC-1 latch
1.19 V
S.C.P.
OSC
DT1
FB1
Since the OSC terminal voltage
becomes higher than
the DT1 terminal voltage,
the Out1 becomes fully off state.
Out1
OSC
FB2
DT2
Forced to be in off state
inside the IC
Out2
1.19 V
S.C.P.
Figure 8. Operation of short-circuit protection at parallel synchronous operation
18
Voltage Regulators
AN8018SA
■ Application Notes (continued)
[8] Setting of Off-terminal connection resistor
The start circuit starts its operation when Q1 is turned
on. In case of the resistor ROFF is connected externally as
shown in figure 9, the input voltage VCTL at which the start
circuit operates is obtained by the equation:
VCTL > VBEQ1 × (ROFF + R1 + R2) / R2
Therefore, ROFF can be set by:
CTL
ROFF
Off 15
Start circuit
R1
30 kΩ
Q1
R2
60 kΩ
ROFF < R2 · VCTL / VBEQ1 − R1 − R2
Set the value of ROFF according to above equations.
(Typical value)
ROFF < 25 kΩ including temperature characteristics
Figure 9. Off terminal peripheral circuit
and sample to sample variations at VCTL = 3 V.
[9] Sequential operation
In the case of sequential operation is necessary for each channel at IC operation, it is possible to turn on/off the
output of DC-DC converter individually by turning on/off Q1 and Q2 as shown in figure 10.
In the channel 1 side, if Q1 turns on and the DT1 terminal (pin 6) becomes 0.2 V or less, the output transistor turns
off due to lower voltage than the OSC terminal (pin 1). Simultaneously, unlatch circuit 1 block operates, and the timer
latch short-circuit protection does not operate because the FB1 terminal (pin 5) becomes fixed to low even if output
of channel 1 downs.
In the channel 2 side, if Q1 turns on and the DT2 terminal (pin 12) becomes 0.9 V or more, the output transistor
turns off due to higher voltage than the OSC terminal (pin 1). Simultaneously, unlatch circuit 2 block operates, and
the timer latch short-circuit protection does not operate because the FB2 terminal (pin 13) becomes fixed to high even
if output of channel 2 downs.
10 Out2
9 VCC
Out1 7
GND 8
11 RB2
Unlatch2
0.9 V
12 DT2
13 FB2
16 VREF
Q2
0.9 V
Unlatch1
DT1 6
1.19 V
FB1 5
0.2 V
V2
Control block
Q1
V1
Figure 10
19
AN8018SA
Voltage Regulators
■ Application Notes (continued)
[9] About sequential operation (continued)
V1
V2
DT1
Out1
DT2
Out2
Out1 operation
Out2 operation
Operation when each channel single on/off
[10] Error amplifier phase-compensation setting method
The equivalent circuit of error amplifier is as shown in figure 11.
The transfer function is:
1 / {S (CE1 + CO1)}
1
=
RE1 + 1 / {S (CE1 + CO1)}
SCO1 · RE1 + 1 (from CE1 << CO1)
The cut-off frequency is variable by changing the externally attached phase compensation capacitor CO1 .
Adjust by inserting a resistor RO1 between the FB1 terminal and CO1 in series as shown in figure 12 when it is
required to have a gain on the high frequency side or desired to lead a phase.
The transfer function is:
H=
SCO1 · RO1 + 1
SCO1 (RO1 + RE1) + 1 (from CE1 << CO1)
IN−1
RE1
1 MΩ
To PWM
57dB
CE1
5 pF
CO1
To PWM
57dB
1.19 V
FB1
1.19 V
IN−1
RE1
1 MΩ
CE1
5 pF
FB1
H=
RO1
CO1
Figure 11. Error amplifier equivalent circuit
20
Figure 12. Error amplifier equivalent circuit (RO1 inserted)
Voltage Regulators
AN8018SA
■ AC Analysis Result
• Simulation circuit
IN−1
FB1
AC
1.19 V
RO1
CO1
f  VPh
f  VPh
180
180
RO1 = 10 kΩ
160
160
1 kΩ
140
100 Ω
10 Ω
1Ω
100
80
100 Ω
10 Ω
100
80
1Ω
60
60
1 kΩ
120
VPh ( ° )
VPh ( ° )
120
RO1 = 10 kΩ
140
CO1 = 1 000 pF
CO1 = 0.01 µF
40
40
20
20
0
0
1
10
100
1k
10k
100k
1M
1
10M 100M
10
100
1k
10k
100k
f (Hz)
f  VBD
10M 100M
f  VBD
60
60
CO1 = 0.01 µF
CO1 = 1 000 pF
40
40
RO1 = 10 kΩ
20
RO1 = 10 kΩ
20
1 kΩ
0
VBD (dB)
VDB (dB)
1M
f (Hz)
100 Ω
−20
10 Ω
−40
−80
1
10
100
1k
10k
f (Hz)
100k
1M
100 Ω
−20
10 Ω
−40
1Ω
−60
1 kΩ
0
10M 100M
1Ω
−60
−80
1
10
100
1k
10k
100k
1M
10M 100M
f (Hz)
21
AN8018SA
Voltage Regulators
■ AC Analysis Result (continued)
f  Phase
f  Phase
180
180
RO1 = 0
160
160
RO1 = 10 kΩ
0.001 µF
140
120
0.1µF
100
CO1 = 1 µF
80
1 kΩ
120
Phase ( ° )
Phase ( ° )
140
0.01
µF
100 Ω
10 Ω
1Ω
100
80
60
60
40
40
20
20
CO1 = 0.1 µF
0
0
1
10
100
1k
10k
100k
1M
1
10M 100M
10
100
1k
10k
100k
1M
f  Gain
f  Gain
60
60
RO1 = 0
CO1 = 0.1 µF
40
40
0.001 µF
CO1 = 1 µF
0
−20
−60
−60
10
100
1k
10k
f (Hz)
100k
1M
10M 100M
100 Ω
−20
−40
−80
1 kΩ
0
−40
1
RO1 = 10 kΩ
20
0.01
0.1 µF
µF
Gain (dB)
Gain (dB)
20
22
10M 100M
f (Hz)
f (Hz)
10 Ω
1Ω
−80
1
10
100
1k
10k
f (Hz)
100k
1M
10M 100M
Voltage Regulators
AN8018SA
■ Application Circuit Examples
• Circuit construction for evaluation board
Input
VOUT2 +
ISO(OUT)
R17
10 Out2
Out1 7
C10
R18
−
9 VCC
11 RB2
DT1 6
Q3
12 DT2
13 FB2
14 IN+2
15 Off
16 VREF
C12 C11
C9
C8
R13
CTL
C7
L2
SBD
R15
R14
C1
R6
C3
C2
R1
GND 8
FB1 5
IN−1 4
IN+1 3
S.C.P. 2
OSC 1
AN8018SA
R11
R12
R7
R2
Q1
R4
R8
C4
VOUT1
L1
R3
−
IOUT1
SBD
R5
C6
+
• Evaluation board
C10
VO2
GND
VO1
VIN
R16 R14 R13 C8
R18
SBD2 R17
On
SW1
Off
C9
Q3
Q2
C6
C5
R10
SBD1
R15
C12
L2
C7
C11
R8R7
R9
L1
C4
Q1
R11
C2
C3
R12
R6 R4
R5
C1
R3 R2 R1
AN8018SA
23
AN8018SA
Voltage Regulators
■ Application Circuit Examples (continued)
• Application circuit example 1 (Input 5 V, output 15 V/−8 V)
Input 5 V
22 kΩ
68 kΩ
0.1 µF
11 RB2
10 Out2
DT1 6
Out1 7
Output 2
+15 V, 50 mA
MA3X720
(MA720*)
10 µF
1 kΩ
12 DT2
13 FB2
14 IN+2
15 Off
16 VREF
0.1 µF 10 µF
0.01
µF
1 kΩ
SW
100 µH
150 kΩ
13 kΩ
9 VCC
0.01 µF
to 0.1 µF
GND
2SD0602
(2SD602*)
1 kΩ
200 Ω
0.01
µF
0.01
12 kΩ µF
330 pF
GND 8
FB1 5
IN−1 4
IN+1 3
S.C.P. 2
OSC 1
AN8018SA
510 Ω
Output 1
−8 V, 10 mA
68 kΩ
51 kΩ 68 kΩ 0.1 µF
6.2 kΩ
82 kΩ
200 µH
MA3X720
(MA720*)
10 µF
51 kΩ
Note) *: Former part number
GND
• Application circuit example 2 (Input 2.5 V to 6.5 V, output 5 V/12 V)
Input
68 kΩ
0.01 µF
to 0.1µF
0.1 µF
10 Out2
Out1 7
9 VCC
11 RB2
Output 2
+12 V
110 kΩ
200 µF
1 kΩ
DT1 6
12 DT2
0.01
µF
1 kΩ
13 FB2
14 IN+2
15 Off
10 µH
0.1 µF
10 µF
H
L
16 VREF
51 kΩ
12 Ω
330 pF
0.01
12 kΩ µF
1 kΩ
0.01
µF 560 Ω
68 kΩ
750 Ω
10 µH
68 kΩ
50 kΩ
GND 8
FB1 5
IN−1 4
IN+1 3
S.C.P. 2
OSC 1
AN8018SA
0.1 µF
100 µF
Output 1
+5 V
39 kΩ
82 kΩ
9.1 kΩ
24
Voltage Regulators
AN8018SA
■ Application Circuit Examples (continued)
• Application circuit example 3 (Input 12 V, Output 5 V/15 V)
Input 12 V
100 µH
MA3X720
(MA720*)
Q1 10 µF
10 kΩ
Out1 7
0.01
µF 560 Ω
GND 8
1 kΩ
f ≈ 200 kHz
DT1 6
FB1 5
IN−1 4
IN+1 3
OSC 1
S.C.P. 2
0.01
12 kΩ µF
750 Ω
68 kΩ
50 kΩ
39 kΩ
68 kΩ
150 kΩ
2SD0602
(2SD602*)
AN8018SA
330 pF
VOUT2
+15 V
13 kΩ
−
9 VCC
13 FB2
14 IN+2
15 Off
16 VREF
0.1 µF
12 DT2
0.01
µF
1 kΩ
SW
CTL
10 µF
10 Out2
0.1 µF
1.19 V(typ.)
22 kΩ
0.1 µF
11 RB2
68 kΩ
0.1 µF MA3X720
(MA720*)
2SA1022
10 µH
82 kΩ
R3
9.1 kΩ
R4
VOUT1
+5 V
(0.1 A to 0.3 A)
Note) *: Former part number
25
AN8018SA
Voltage Regulators
■ Application Circuit Examples (continued)
• Application circuit example 4 (Circuit using the AN8017SA/AN8018SA)
Input voltage range: 1.8 V to 3.2 V
Oscillation frequency: 450 kHz
22 kΩ
68 kΩ
10 µH
MA2Q738
(MA738*)
0.1 µF
0.1 µF
Input 1.8 V to 3.2 V
5 V (STBY)
300 mA
(max.)
9 VCC
12 DT2
11 RB2
10 Out2
820 Ω
10 kΩ
13 FB2
14 IN+2
15 Off
16 VREF
0.1 µF
12 kΩ
10 µF
10 kΩ
5.1 kΩ
GND 8
Out1 7
DT1 6
FB1 5
IN+1 3
S.C.P. 2
OSC 1
IN−1 4
AN8018SA
1.19 V
−10 V
MA2Q738 10 mA
(MA738*)
(max.)
2SB1440
300 Ω
0.1 µF
68 µH 10 µF
330 pF
68 kΩ
75 kΩ
1.5 kΩ
22 kΩ
47 kΩ
0.1 µF
75 kΩ
68 kΩ
1.19 V
39 kΩ
2SD0874
(2SD874*)
22 kΩ
0.1 µF
0.1 µF
MA2Q738
10 µH (MA738*)
5V
140 mA
(max.)
9 VCC
10 Out2
11 RB2
12 DT2
13 FB2
14 IN+2
820 Ω
10 kΩ
51 kΩ
2SD0602
(2SD602*)
15 kΩ
10 µF
10 kΩ
0.1 µF
820 Ω
GND 8
Out1 7
RB1 6
DT1 5
FB1 4
IN−1 3
S.C.P. 2
AN8017SA
OSC 1
Remote on/off
control pin
−10 V, 5 V, 18 V
stop with high-level
input.
15 Off
16 VREF
0.1 µF
MA2Q738
18 µH (MA738 *)
18 V
35 mA
(max.)
56 kΩ
2SD0602
(2SD602*)
10 µF
56 kΩ
68 kΩ
0.1 µF
Note) *: Former part number
26
3.9 kΩ