APA2010B 3W Mono Class-D Audio Power Amplifier Features • • • General Description Operating Voltage: 2.4V-5.5V High Efficiency up to 90% The APA2010B is a mono, filter-free Class-D audio amplifier available in WLCSP-9 packages. The gain can be Low Supply Current – IDD=2mA at VDD=5V set by an external input resistance. High PSRR and differential architecture provide increased immunity to noise • – IDD=1.6mA at VDD=3.6V Low Shutdown Current and RF rectification. In addition to these features, a fast startup time and small package size make the APA2010B • – IDD=1µA at VDD=5V Output Power an ideal choice for both cellular handsets and PDAs. The APA2010B is capable of driving 1.5W at 5V or 730mW at 1% THD+N – 2.4W, at VDD=5V, RL=4Ω (WLCSP-9) at 3.6V into 8Ω. It is also capable of driving 4Ω. The APA2010B is designed with a Class-D architecture and – 2.1W, at VDD=5V, RL=4Ω – 1.2W, at VDD=3.6V, RL=4Ω operating with highly efficiency compared with Class-AB amplifier. It's suitable for power sensitive application, such at 10% THD+N – 3.1W, at VDD=5V, RL=4Ω (WLCSP-9) as battery powered devices. The filter-free architecture eliminates the output filter, reduces the external compo- – 2.65W, at VDD=5V, RL=4Ω – 1.3W, at VDD=3.6V, RL=4Ω nent count, board area, and system costs, and simplifies the design. Less External Components Required Fast Startup Time (4ms) Moreover, the APA2010B provides thermal and over-current protections. • • • • • • High PSRR: 80 dB at 217 Hz Thermal and Over-Current Protections Applications Space Saving Packages WLCSP-9 Bump • • • • Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration VON (A3) PGND (B3) VOP (C3) GND (A2) PVDD (B2) SD (C2) INP (A1) VDD (B1) INN (C1) PIN A1 Mobile Phones Handsets PDAs Portable multimedia devices (Note 1) A20 X Date Code Marking WLCSP1.5x1.5-9A (Top View) Note 1: The marking for APA2010B is “A20” ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 1 www.anpec.com.tw APA2010B Ordering and Marking Information Package Code HA : WLCSP1.5x1.5-9A Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2010B Assembly Material Handling Code Temperature Range Package Code APA2010B HA: A20 X X - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 2) (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter Rating Unit VDD Supply Voltage (VDD, PVDD) -0.3 to 6 V VIN, VSD Input Voltage (SD, INP, INN) -0.3 to 6 V TA Operating Ambient Temperature Range -40 to 85 ο TJ Maximum Junction Temperature 150 ο -65 to +150 ο 260 ο TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds PD Power Dissipation C C C C Internally Limited W Note2: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics Symbol θJA Parameter Typical Value Thermal Resistance -Junction to Ambient (Note 3) Unit ο WLCSP1.5x1.5-9A 165 C/W Note 3 : Please refer to “ Layout Recommendation”, the ThermalPad on the bottom of the IC should soldered directly to the PCB's ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 2 www.anpec.com.tw APA2010B Recommended Operating Conditions Symbol Range Parameter Min. Max. Unit VDD Supply Voltage 2.4 5.5 V VIH High Level Threshold Voltage SD 1 - V VIL Low Level Threshold Voltage SD - 0.35 V Electrical Characteristics VDD=5V, GND=0V, TA= 25οC (unless otherwise noted) Symbol Parameter Test Conditions IDD Supply Current ISD Shutdown Current SD = 0V Input current SD Ii Fosc RDSCON Static drain-source on-state resistance VDD = 3.6V VDD = 2.4V Unit Min. Typ. Max. - 2 - mA - 1 - µA - 0.1 - µA 200 250 300 kHz P-Channel MOSFET (WLCSP1.5X1.5-9A) - 340 - N-Channel MOSFET (WLCSP1.5X1.5-9A) - 195 - P-Channel MOSFET (WLCSP1.5X1.5-9A) - 400 - N-Channel MOSFET (WLCSP1.5X1.5-9A) - 215 - P-Channel MOSFET (WLCSP1.5X1.5-9A) - 550 - N-Channel MOSFET (WLCSP1.5X1.5-9A) - 260 - - 2.45 - Oscillator Frequency VDD = 5V APA2010B mΩ VDD=5V, TA=25° C RL = 4Ω PO THD+N = 1%, (WLCSP1.5X1.5-9A) fin = 1kHz RL = 4Ω - 2.1 - RL = 8Ω 1 1.3 - - 3.1 - Output Power RL = 4Ω THD+N PSRR VOS Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio Output Offset Voltage S/N Vn Noise Output Voltage Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 THD+N = 10%, (WLCSP1.5X1.5-9A) fin = 1kHz RL = 4Ω - 2.65 - fin = 1kHz RL = 8Ω - 1.6 - RL = 4Ω PO= 1.6W - 0.3 - RL = 8Ω PO= 0.96W - 0.1 - - 80 RL = 8Ω, fin = 217Hz W % RL = 8Ω - dB 25 mV With A-weighting Filter PO = 0.96W, RL = 8Ω - 90 - dB With A-weighting Filter - 100 - µV (rms) 3 www.anpec.com.tw APA2010B Electrical Characteristics (Cont.) VDD=5V, GND=0V, TA= 25οC (unless otherwise noted) Symbol Parameter Test Conditions APA2010B Unit Min. Typ. Max. RL = 4Ω (WLCSP1.5X1.5-9A) - 1.2 - RL = 4Ω - 1.1 - RL = 8Ω - 0.6 - RL = 4Ω (WLCSP1.5X1.5-9A) - 1.5 - RL = 4Ω - 1.35 - RL = 8Ω - 0.8 - - 0.35 - - 0.1 - RL = 8Ω, fin = 217Hz - 75 - dB RL = 8Ω With A-weighting Filter PO= 0.43W, RL = 8Ω, - - 25 mV - 85 - dB With A-weighting Filter - 105 - µV (rms) VDD=3.6V, TA=25° C THD+N = 1%, fin = 1kHz PO Output Power THD+N = 10%, fin = 1kHz THD+N PSRR VOS Power Supply Rejection Ratio Output Offset Voltage S/N Vn RL = 4Ω PO = 0.82W, RL = 8Ω PO= 0.45W Total Harmonic Distortion Pulse fin = 1kHz Noise Noise Output Voltage W % VDD=2.5V, TA=25° C PO THD+N PSRR VOS RL = 4Ω - 0.45 - RL = 8Ω - 0.3 - THD+N =10%, fin = 1kHz RL = 4Ω - 0.55 - RL = 8Ω - 0.35 - PO = 0.34W, RL = 4Ω - 0.35 - PO = 0.22W, RL = 8Ω - 0.2 - Output Power W Total Harmonic Distortion Pulse Noise fin = 1kHz Power Supply Rejection Ratio RL = 8Ω, fin = 217Hz - 70 - dB Output Offset Voltage RL = 8Ω With A-weighting Filter PO = 0.2W, RL = 8Ω - - 25 mV - 83 - dB - 120 - µV (rms) S/N Vn THD+N = 1%, fin = 1kHz Noise Output Voltage Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 With A-weighting Filter 4 % www.anpec.com.tw APA2010B Typical Operating Characteristics Efficiency vs. Output Power Efficiency vs. Output Power (4Ω) 100 90 90 80 80 Efficiency (%) Efficiency (%) 70 VDD=5V VDD=3.6V 70 VDD=2.4V 60 50 40 RL=8Ω&33µH fin=1kHz Cin=0.47µF Rin=150kΩ AUX-0025 AES-17 (20kHz) 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 60 50 40 RL=4Ω&33µH fin=1kHz Cin=0.47µF Rin=150kΩ AUX-0025 AES-17 (20kHz) 30 20 10 0 1.2 0 0.4 0.8 Output Power vs. Load Resistance 2.4 THD+N=10% fin=1kHz Cin=0.22µF Rin=150kΩ AUX-0025 AES-17(20kHz) VDD=5V,WLCSP-9 VDD=5V 2 VDD=3.6V,WLCSP-9 1.6 2.0 THD+N=1% fin=1kHz Cin=0.22µF Rin=150kΩ AUX-0025 AES-17(20kHz) VDD=5V,WLCSP-9 2 VDD=5V VDD=3.6V,WLCSP-9 1.5 VDD=2.4V,WLCSP-9 1.2 1.6 Output Power vs. Load Resistance 2.5 Output Power (W) Output Power (W) 2.8 1.2 Output Power (W) Output Power (W) 3.2 VDD=5V VDD=3.6V VDD=2.4V VDD=3.6V 0.8 VDD=2.4V,WLCSP-9 1 VDD=3.6V 0.5 0.4 0 VDD=2.4V 4 VDD=2.4V 8 12 16 20 24 28 0 32 4 8 Load Resistance (Ω) Output Power vs. Supply Voltage 24 RL=4Ω,WLCSP-9, THD+N=10% RL=4Ω,WLCSP-9, THD+N=1% VDD=2.4V 1 RL=4Ω, THD+N=10% RL=4Ω, THD+N=1% 1.6 RL=8Ω, THD+N=10% 1.2 0.8 fin=1kHz Cin=0.22µF Rin=150kΩ RL=4Ω AUX-0025 AES-17(20kHz) WLCSP-9 RL=8Ω,WLCSP-9, THD+N=10% 0.4 RL=8Ω, THD+N=1% RL=8Ω,WLCSP-9, THD+N=1% 0.01 3.2 32 VDD=5V 0.1 2.8 28 VDD=3.6V THD+N (%) Output Power (W) 20 10 fin=1kHz Cin=0.22µF 2.8 Rin=150kΩ AUX-0025 2.4 AES-17(20kHz) 0 2.4 16 THD+N vs. Output Power 3.2 2 12 Load Resistance (Ω) 3.6 4 4.4 Supply Voltage (Volt) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 4.8 5 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 Output Power (W) 5 www.anpec.com.tw APA2010B Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Output Power 10 10 VDD=2.4V VDD=3.6V VDD=5V fin=1kHz Cin=0.22µF Rin=150kΩ RL=4Ω AUX-0025 AES-17(20kHz) 0.1 0.01 0 1 THD+N (%) THD+N (%) 1 0.4 0.8 1.2 1.6 2 2.4 Output Power (W) VDD=5V Cin=0.47µF Rin=150kΩ RL=4Ω AUX-0025 AES-17 (20kHz) PO=1.6W 0.1 PO=0.8W 2.8 0.01 20 THD+N vs. Frequency 10 VDD=3.6V Cin=0.47µF Rin=150kΩ RL=4Ω AUX-0025 AES-17 (20kHz) 1 THD+N (%) THD+N (%) 1 10k 20k Frequency (Hz) THD+N vs. Frequency 10 1k 100 PO=0.82W 0.1 PO=0.41W VDD=2.4V Cin=0.47µF Rin=150kΩ RL=4Ω AUX-0025 AES-17 (20kHz) PO=0.34W 0.1 PO=0.17W 0.01 20 1k 100 0.01 20 10k 20k 100 Frequency (Hz) 10 VDD=2.4V VDD=3.6V 1 THD+N (%) THD+N (%) 1 VDD=5V 0.01 0 fin=1kHz Cin=0.22µF Rin=150kΩ RL=8Ω AUX-0025 AES-17(20kHz) 0.2 0.4 0.6 0.8 1 1.2 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 10k 20k THD+N vs. Frequency THD+N vs. Output Power 10 0.1 1k Frequency (Hz) 1.4 1.6 VDD=5V Cin=0.47µF Rin=150kΩ RL=8Ω AUX-0025 AES-17 (20kHz) PO=0.96W 0.1 PO=0.48W 0.01 0.005 20 1.8 6 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2010B Typical Operating Characteristics (Cont.) THD+N vs. Frequency VDD=3.6V Cin=0.47µF Rin=150kΩ RL=8Ω AUX-0025 AES-17 (20kHz) 1 THD+N (%) 1 THD+N (%) THD+N vs. Frequency 10 10 PO=0.45W 0.1 VDD=2.4V Cin=0.47µF Rin=150kΩ RL=8Ω AUX-0025 AES-17 (20kHz) PO=0.22W 0.1 PO=0.11W PO=0.23W 0.01 0.01 0.005 20 0.005 20 100 10k 20k 1k 100 Frequency (Hz) CMRR vs. Frequency Frequency Response +0 +20 Phase +0 +8 -20 +7 -40 Gain -60 +5 -80 VDD=5V Cin=0.47µF Rin=150kΩ PO=0.156W RL=8Ω AUX-0025 AES-17 (20kHz) +4 +3 +2 +1 +0 10 20 -100 -120 Phase (Deg) Gain (dB) +9 -140 -160 50 100 200 500 1k 2k 5k 10k 20k Common Mode Rejection Ratio (dB) +10 +6 -10 -20 -30 VDD=3.6V -40 VDD=2.4V 50 100 200 Power Supply Rejection Ratio (dB) Common Mode Rejection Ratio (dB) 2k 5k 10k 20k +0 Cin=0.47µF Rin=150kΩ RL=8Ω Inputs Short AUX-0025 AES-17 (20kHz) -30 VDD=3.6V VDD=2.4V VDD=5V -50 -60 20 1k PSRR vs. Frequency CMRR vs. Frequency -40 500 Frequency (Hz) +0 -20 VDD=5V -50 -60 20 -180 50k Cin=0.47µF Rin=150kΩ RL=4Ω Inputs Short AUX-0025 AES-17 (20kHz) Frequency (Hz) -10 10k 20k 1k Frequency (Hz) 50 100 200 500 1k 2k 5k -40 -50 -60 VDD=3.6V VDD=2.4V -70 -80 -90 -100 20 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 TC =0.47µF in Rin=150kΩ RL=4Ω -20 AUX-0025 -30 AES-17 (20kHz) -10 VDD=5V 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) 7 www.anpec.com.tw APA2010B Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency PSRR vs. Frequency 200µ TT CinT =0.47µF Rin=150kΩ RL=8Ω Inputs Short AUX-0025 AES-17 (20kHz) -20 -30 VDD=2.4V Output Noise Voltage (µV) Power Supply Rejection Ratio (dB) +0 -10 -40 -50 VDD=3.6V -60 VDD=2.4V -70 -80 -90 100µ 70µ VDD=3.6V 50µ Cin=0.47µF Rin=150kΩ RL=4Ω Inputs Short to Gnd AUX-0025 LPF=22kHz A-weighting 30µ 20µ VDD=5V -100 20 10µ 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 Frequency (Hz) Output Noise Voltage vs. Frequency 1k 2k 5k 10k 20k Supply Current vs. Output Power 0.3 VDD=2.4V VDD=3.6V 0.25 100µ Supply Current (A) Output Noise Voltage (µV) 500 Frequency (Hz) 200µ 70µ VDD=3.6V 50µ VDD=5V 40µ Cin=0.47µF 30µ R =150kΩ in RL=8Ω 20µ Inputs Short to Gnd AUX-0025 LPF=22kHz A-weighting 50 100 200 RL=8Ω&33µH fin=1kHz Cin=0.47µF Rin=150kΩ AUX-0025 AES-17 (20kHz) 0.1 0.05 500 1k 2k 5k 10k 20k 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Output Power (W) Frequency (Hz) Supply Current vs. Output Power Supply Current vs. Supply Voltage 0.6 2.5 No Load 0.5 VDD=3.6V Supply Current (mA) 2 0.4 VDD=5V VDD=2.4V 0.3 RL=4Ω&33µH fin=1kHz Cin=0.47µF Rin=150kΩ AUX-0025 AES-17 (20kHz) 0.2 0.1 0 VDD=5V 0.15 0 20 VDD=2.4V 0.2 10µ Supply Current (A) VDD=5V 40µ 0 0.5 1 1.5 2 1 0.5 0 2.5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 1.5 0 1 2 3 4 5 6 Supply Voltage (Volt) 8 www.anpec.com.tw APA2010B Typical Operating Characteristics (Cont.) GSM Power Supply Rejection vs. Time Shutdown Current vs. Supply Voltage 1 Shutdown Current (µA) No Load VDD 200mV/div High 3.6V Low 3.088V 0.8 0.6 0.4 Vout 10mV/div 0.2 0 0 1 2 3 4 5 6 2ms/div Supply Voltage (Volt) Common Mode Rejection ratio vs. Common Mode Input Voltage GSM Power Supply Rejection vs. Frequency +0 -100 -150 +0 VOUT (dBV) VDD (dBV) -50 Common Mode Rejection Ratio (dB) +0 -50 -100 -150 0 400 800 1.2k 1.6k -20 -30 VDD=3.6V -40 VDD=2.4V VDD=5V -50 -60 2k 0 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 -10 1 2 3 4 5 Common Mode Input Voltage (Volt) 9 www.anpec.com.tw APA2010B Pin Description PIN (WLCSP1.5X1.5-9A) NO. NAME A1 INP A2 A3 B1 I/O FUNCTION I The non-inverting input of amplifier. INP is connected to Gnd via a capacitor for single-end (SE) input signal. GND - Ground connection for circuitry. VON O The negative output terminal of Class-D amplifier. VDD - Supply voltage input pin. B2 PVDD - Supply voltage only for power stage. B3 PGND - Ground connection for power stage C1 INN I The inverting input of amplifier. INN is used as audio input terminal, typically. C2 SD I Shutdown mode control signal input, place entire IC in shutdown mode when held low. C3 VOP O The positive output terminal of Class-D amplifier. Block Diagram PVDD Av=2 (150kΩ/Rin) * 150/125kΩ∗ VON Gate Drive INN De-glitch & Modulation Logic INP VOP Gate Drive 150/125kΩ∗ PGND SD TTL Input Buffer RAMP GEN, Biases & Reference Startup protection logic Over-Current Protection Thermal Protection * APA2010B : 150kΩ Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 10 www.anpec.com.tw APA2010B Typical Application Circuit Differential input mode (WLCSP1.5x1.5-9A) VDD 0.1µF Negative input signal Positive input signal 0.1µF Rinn 10µF VDD PVDD (B1) (B2) INN (C1) VON 150kΩ Cinn- (A3) INP 0.1µF Rinp (A1) APA2010/2010A 150kΩ Cinp+ 4Ω VOP SD Shutdown signal (C3) (C2) GND (A2) PGND Gnd (B3) Single-ended input mode (WLCSP1.5x1.5-9A) VDD 0.1µF Singal-ended signal VDD PVDD (B1) (B2) 0.1µF Rinn INN (C1) Cinn- VON 150kΩ (A3) Rinp Cinn+ 0.1µF 10µF INP (A1) APA2010/2010A 150kΩ Gnd Shutdown signal 4Ω VOP SD (C3) (C2) GND (A2) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 11 PGND Gnd (B3) www.anpec.com.tw APA2010B Application Information Fully Differential Amplifier The APA2010B modulation scheme is shown in figure 1. The outputs VOP and VON are in phase with each other The APA2010B is a fully distinctive amplifier with differential inputs and outputs. Compare with the traditional when no input signals. When output > 0V, the duty cycle of VOP is greater than 50% and VON is less than 50%; on amplifiers, the fully differential amplifier has some advantages. Firstly, there is no need for the input cou- the contrary, when output <0V, the duty cycle of VOP is less than 50% and VON is greater than 50%. This method pling capacitors because the common-mode feedback will compensate the input bias. The inputs can be biased reduces the switching current across the load and the I2R losses in the load which can improve the amplifier’s from 0.5V to VDD-0.5V, and the outputs still be biased at mid-supply of APA2010B. If the inputs are biased out of efficiency. This modulation scheme has very short pulses across the input range, the coupling capacitors are required. Secondly, there is no need for the mid-supply capacitor the load which results in the small ripple current and very little loss on the load. Meanwhile, the LC filter can be (C ) either because any shift of the mid-supply of B APA2010B will have the same affection on both positive & eliminated in most applications. Adding the LC filter can increase the efficiency by filtering the ripple current. negative channel, and will cancel at the differential outputs. Thirdly, the fully differential amplifier will cancel the GSM Square Wave Into the Speaker RF transmitter’s signal (217Hz). Applying the square wave into the speaker may cause the voice coil of speaker jumping out the air gap and de- Class-D Operation VOP facing the voice coil. However, this depends on if the amplitude of square wave is high enough and the bandwidth VON of speaker is higher than the square wave’s frequency. For 250kHz switching frequency, this is not an issue for Output = 0V the speaker because the frequency is beyond the audio band and can’t significantly move the voice coil, as cone VOUT (VOP-VON) movement is proportional to 1/f2 for frequency out of audio band. IOUT Output > 0V Input Resistance, Rin VOP The gain of the APA2010B has been set by the external resistors (Rin ). VON Gain(Av) = VOUT (VOP-VON) IOUT (1) For fully differential operating, the Rin match is very important for CMRR, PSRR and harm onic distortion performance. It’s recommended to use 1% tolerance re- Output < 0V VOP sistor or better. Keeping the input trace as short as possible to limit the noise injection. VON The gain is recommended to set as 2V/V or lower for APA2010B’s optimal performance. VOUT (VOP-VON) Input Capacitor, Cin IOUT In the typical application, an input capacitor, Cin, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Cin and the Figure 1. The Class-D Power Amplifier Output Waveform (Voltage & Current) Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 2X150kΩ (or 125k Ω ) Rin 12 www.anpec.com.tw APA2010B Application Information (Cont.) Input Capacitor, Ci (Cont.) ent types of capacitors that target on different types of noise on the power supply leads. For higher frequency minimum input impedance Rin from a high-pass filter with the corner frequency are determined in the following transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, equation: FC(highpass ) = 1 2πRinCin typically 0.1µF, is placed as close as possible to the device VDD pin for the best operation. For filtering lower (2) frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater is placed near the audio power The value of Cin must be considered carefully because it directly affects the low frequency performance of the circuit. For example, when Rin is 150kΩ and the specification amplifier is recommended. calls for a flat bass response are down to 20Hz. The equation is reconfigured as below: Cin = 1 2πRinFc Shutdown Function In order to reduce power consumption while not in use, the APA2010B contains a shutdown function to externally (3) turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SD When input resistance is considered, the Cin is 0.05µF. Therefoe, a value in the range of 0.068µF to 0.1µF would pin for APA2010B. The trigger point between a logic high and logic low level is typically 0.4VDD. It suggests to be chosen. A further consideration for this capacitor is the leakage path from the input source through the input net- switch to either ground or the supply voltage VDD to provide maximum device performance. By switching the SD work (Rin + Rf, Cin) to the load. This leakage current creates a DC offset voltage at the pin to a low level, the amplifier enters a low-consumption-current state, and then the APA2010B is in shutdown input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low- mode. In normal operating, APA2010B’s SD pin should be pulled to a high level to keep the IC out of the shut- leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of down mode. The SD pin should be tied to a definite voltage to avoid unwanted state changes. the capacitor should face the amplifier input in most applications because the DC level of the amplifiers’inputs are held at VDD/2. Please note that it is important to confirm the capacitor polarity in the application. Output LC Filter Output Capacitor, CO If the traces from the APA2010B to speaker are short, the APA2010B doesn’t require output filter for FCC & CE If the user wants to add capacitor at output without ferrite standard. A ferrite bead may be needed if it’s failing the test for FCC bead and inductor, please note the output capacitor should not be greater than 1nf (VDD=4.2V). The high value of out- or CE is tested without the LC filter. The Figure 2 is the sample for adding ferrite bead; the ferrite shows when put capacitor maybe trigger the OCP (Over-Current Protection) of APA2010B. choosing high impedance in high frequency. Power Supply Decoupling, Cs VON The APA2010B is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is 1nF Ferrite Bead as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length VOP between the amplifier and the speaker. The optimum decoupling is achieved by using two differCopyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 Ferrite Bead 4Ω 1nF Figure 2. Ferrite bead output filter 13 www.anpec.com.tw APA2010B Application Information (Cont.) Layout Recommendation Output LC Filter (Cont.) 9 X Φ 0.275mm Figure 3 is an example for adding the LC filter. It’s recommended to eliminate the radiated emission or EMI when the trace from amplifier to speaker is too long. VON 47µH 1µF 47µH 0.5mm VOP 4Ω 1µF Figure 3. LC output filter Figure 3’s low pass filter cut-off frequency is FC FC(lowpass) = 1 0.5mm (4) 2π LC Figure 5. WLCSP-9 land pattern recommendation Mixing Two Single-Ended Input Signals C1 R1 C2 R2 1. All components should be placed close to the APA2010B. For example, the input resistor (Rin) should be close to APA2010B’s input pins to avoid causing noise INP CP coupling to APA2010B’s high impedance inputs; the decoupling capacitor (C s ) should be placed by the RP APA2010B’s power pin to decouple the power rail noise. 2. The output traces should be short, wide (>50mil), and INN symmetric. 3. The input trace should be short and symmetric. Figure 4. Mixing Two Single-Ended Input Signals 4. The power trace width should greater than 50mil. For mixing two Single-Ended (SE) input signals, please refer to Figure 4. The gains of each input can be set difference: A V (1) = 2 × 150k Ω (or 125k Ω ) R1 (5) A V (2) = 2 × 150k Ω (or 125k Ω ) R2 (6) The corner frequency of each input high- pass-filter also can be set by R1&C1, and R2&C2. The non-inverting input’s resistor (RP) and capacitor (CP) need to match the impedances of invert inputs. CP = C1//C2 = C1 + C2 (7) R1 × R2 R1 + R2 (8) RP = R1//R 2 = Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 14 www.anpec.com.tw APA2010B Package Information E WLCSP1.5x1.5-9A PIN 1 A2 D A1 e b A e S Y M B O L WLCSP1.5x1.5-9A INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.53 0.67 0.021 0.026 A1 0.20 0.24 0.008 0.009 A2 0.33 0.43 0.013 0.017 b 0.29 0.31 0.011 0.012 D 1.42 1.50 0.056 0.059 E 1.42 1.50 0.056 0.059 e Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 0.50 BSC 0.020 BSC 15 www.anpec.com.tw APA2010B Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application WLCSP1.5X1.5-9A A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 1.70±0.20 1.70±0.20 0.90±0.20 (mm) Devices Per Unit Package Type Unit Quantity WLCSP1.5X1.5-9A Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 16 www.anpec.com.tw APA2010B Taping Dircetion Information WLCSP1.5x1.5-9A USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 17 www.anpec.com.tw APA2010B Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 18 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2010B Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2011 19 www.anpec.com.tw