ANPEC APA2175

APA2175
Stereo Cap-Free Line Driver
Features
General Description
•
•
The APA2175 is a stereo, fixed gain, single supply, and
cap-free line driver, which is available in TQFN4x4-20B
•
•
Operating Voltage: 2.3V-4.5V
Supply Current
and TSSOP-16 packages.
The APA2175 is ground-reference output, and no need
- IDD=5mA at VDD=3.3V
Low Shutdown Current
the output capacitors for DC blocking. The advantages of
eliminating the output capacitor are saving the cost, elimi-
- IDD=1µA at VDD=3.3V
Ground Reference Output
nating component height, and improving the low frequency
response.
- No Output Capacitor Required (for DC Blocking)
- Save the PCB Space
The internal fixed gain setting (-1.5V/V) can minimize the
external component counts and save the PCB space.
- Reduce the BOM Costs
•
•
•
•
•
•
•
- Improve the Low Frequency Response
High PSRR provides increased immunity to noise and
RF rectification. The independent shutdown control of
Output Voltage Swing Can Reach 2Vrms/Ch into
600Ω at VDD=3.3V
High PSRR: 78dB at 217Hz
APA2175 is for right channel and left channel.
The APA2175 is capable of driving 2Vrms at 3.3V into
Fast Start-Up Time: 16ms
600Ω load, and provides thermal protection.
Integrate the De-pop Circuitry
Simplified Application Circuit
Separate Shutdown Function for Flexible Application
Thermal Protection
Surface-Mount Packaging
- TQFN4x4-20B (with Enhanced Thermal Pad)
•
- TSSOP-16
Lead Free and Green Devices Available
Stereo
Input
Signal
RIN
Shutdown
Control
RSD
LSD
ROUT
LIN
APA2175
Stereo
LOUT Line-Out
Signal
(RoHS Compliant)
Applications
•
•
•
•
Set-Top Boxes
CD / DVD Players
LCD TVs
HTIBs (Home Theater in Box)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
1
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APA2175
11 ROUT
12 NC
13 LIN
14 RSD
15 RIN
Pin Configuration
NC 1
NC 16
10 VDD
12 LIN
11 ROUT
CPN 6
10 VDD
CVSS 7
6 NC
NC 20
13 RSD
APA2175
PGND 5
7 VSS
PVDD 19
14 RIN
CPP 4
8 NC
APA2175
LSD 18
15 GND
NC 3
9 LOUT
GND 17
16 LSD
PVDD 2
9 LOUT
CVSS 5
NC 4
CPN 3
PGND 2
CPP 1
VSS 8
TQFN4x4-20B
(Top View)
TSSOP-16
(Top View)
=ThermalPad (connected the ThermalPad
to GND plane for better heat dissipation)
Ordering and Marking Information
Package Code
QB : TQFN4x4-20B O : TSSOP-16
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APA2175
Assembly Material
Handling Code
Temperature Range
Package Code
APA2175 QB :
APA2175
XXXXX
XXXXX - Date Code
APA2175 O :
APA2175
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
VPVDD_VDD
PVDD to VDD Voltage
-0.3 to 0.3
VPGND_GND
PGND to GND Voltage
-0.3 to 0.3
Supply Voltage (VDD and PVDD to GND and PGND)
-0.3 to 5.5
VDD
VRSD, VLSD
VSS
Input Voltage (RSD and LSD to GND)
V
GND-0.3 to VDD+0.3
VSS and CVSS to GND and PGND Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
Unit
2
-5.5 to 0.3
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APA2175
Absolute Maximum Ratings (Cont.) (Note 1)
Symbol
Parameter
Rating
Unit
VOUT
ROUT and LOUT to GND Voltage
VCPP
CPP to PGND Voltage
PGND-0.3 to PVDD+0.3
VCPN
CPN to PGND Voltage
PVSS-0.3 to PGND+0.3
TJ
VSS-0.3 to VDD+0.3
Maximum Junction Temperature
150
TSTG
Storage Temperature Range
TSDR
Maximum Soldering Temperature Range, 10 Seconds
PD
V
ο
-65 to +150
C
260
Power Dissipation
Internally Limited
W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Typical Value
Thermal Resistance - Junction to Ambient
Unit
(Note 2)
TQFN4x4-20B
TSSOP-16
45
100
TQFN4x4-20B
8
o
C/W
Thermal Resistance - Junction to Case (Note 3)
o
C/W
Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s
Thermal Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz
copper thickness.
Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the TQFN4x4-20B package.
Recommended Operating Conditions
Symbol
VDD
Range
Parameter
Supply Voltage
Min.
Max.
2.3
4.5
VIH
High Level Threshold Voltage
RSD, LSD
1
-
VIL
Low Level Threshold Voltage
RSD, LSD
-
0.35
TA
Operating Ambient Temperature Range
-40
85
TJ
Operating Junction Temperature Range
-40
125
Unit
V
ο
C
Electrical Characteristics
VDD=3.3V, VRSD=VLSD=VDD, CCPF=CCPO=2.2µF, Ci=1µF, TA=25oC (unless otherwise noted)
Symbol
Parameter
Test Conditions
APA2175
Unit
Min.
Typ.
Max.
-
5
10
mA
IDD
VDD Supply Current
ISD
VDD Shutdown Current
VRSD=VLSD=0V
-
1
5
µA
Input current
RSD, LSD
-
0.1
-
µA
Ii
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
3
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APA2175
Electrical Characteristics (Cont.)
VDD=3.3V, VRSD=VLSD=VDD, CCPF=CCPO=2.2µF, Ci=1µF, TA=25oC (unless otherwise noted)
Symbol
Parameter
Test Conditions
APA2175
Min.
Typ.
Max.
Unit
CHARGE PUMP
fOSC
Switching Frequency
400
500
600
kHz
Req
Equivalent Resistance
-
21
25
Ω
Rdis
Discharge Resistor at Output
-
4
5
kΩ
-1.55
-1.5
-1.45
V/V
-
1
2
%
DRIVERS
AV
∆AV
Internal Voltage Gain
No Load
Gain Matching
Ri
Input Resistance
15
18
21
Rf
Feedback Resistance
23
27
31
-
-
100
Ω
-
2.5
-
V/µs
-8
-
8
mV
-
15
30
µVrms
-80
-60
-80
-60
-55
-45
Ro
Output Resistance
VSR
Slew Rate
VOS
Output Offset Voltage
VN
Output Noise
IO=10mA
VDD=2.3V to 4.5V, RL = 600Ω
kΩ
VDD=2.3V to 4.5V, Vrr=200mVrms
PSRR
Power Supply Rejection Ratio
fin= 217Hz
-
fin= 1kHz
fin= 20kHz
CL
Tstart-up
VESD
dB
Maximum Capacitive Load
-
400
-
pF
Start-up Time
-
16
-
ms
-
8
-
kV
2
2.1
-
Vrms
-
Vrms
-
%
ESD Protection
OUTR, OUTL
THD+N=1%, fin=1kHz
VO
Output Voltage
(Stereo, in Phase)
RL=600Ω
2.3
RL=100kΩ
VDD=4.5V, THD+N=1%, fin=1kHz
VO
Output Voltage
(Stereo, in Phase)
-
RL=600Ω
2.7
2.8
RL=100kΩ
VO=2Vrms, RL=600Ω
THD+N
Total Harmonic Distortion
Pulse Noise
fin=20Hz
-
fin=1kHz
fin=20kHz
0.020
0.003
0.020
VO=2Vrms, RL=600Ω
Crosstalk
Channel Separation
fin=20Hz
-
fin=1kHz
fin=20kHz
S/N
Signal to Noise Ratio
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
105
105
dB
100
VO=2Vrms, RL=600Ω
With A-weighting Filter
4
-
102
-
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APA2175
Typical Operating Characteristics
THD+N vs. Output Voltage
THD+N vs. Output Voltage
10
RL=600Ω
fin=1kHz
AV=-1.5V/V
1
THD+N (%)
THD+N (%)
1
10
VDD=4.5V
0.1
VDD=3.3V
0.01
RL=100kΩ
fin=1kHz
AV=-1.5V/V
VDD=4.5V
0.1
VDD=3.3V
0.01
VDD=2.3V
VDD=2.3V
0.001
10m
100m
1
0.001
10m
5
100m
Output Voltage (V)
VDD=3.3V
RL=600Ω
Ci=1µF
AV=-1.5V/V
BW<80kHz
THD+N (%)
THD+N (%)
1
VO=0.1Vrms
0.01
0.1
VDD=3.3V
RL=100kΩ
Ci=1µF
AV=-1.5V/V
BW<80kHz
VO=0.1Vrms
0.01
VO=1Vrms
VO=1Vrms
VO=2Vrms
0.001
20
100
1k
Frequency (Hz)
0.001
20
10k 20k
Crosstalk vs. Frequency
1k
10k 20k
Crosstalk vs. Frequency
+0
VDD=3.3V
RL=600Ω
AV=-1.5V/V
Ci=1µF
VO=2Vrms
-20
Crosstalk (dB)
Crosstalk (dB)
-40
VO=2Vrms
100
Frequency (Hz)
+0
-20
5
THD+N vs. Frequency
THD+N vs. Frequency
1
0.1
1
Output Voltage (V)
-60
-80
-40
VDD=3.3V
RL=100kΩ
AV=-1.5V/V
Ci=1µF
VO=2Vrms
-60
-80
Left to Right
-100
Left to Right
-100
Right to Left
-120
20
100
1k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
Right to Left
-120
20
10k 20k
5
100
1k
Frequency (Hz)
10k 20k
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APA2175
Typical Operating Characteristics (Cont.)
Output Noise Voltage vs. Frequency
50µ
30µ
30µ
Left channel
10µ
Right channel
7µ
5µ
VDD=3.3V
RL=600Ω
AV=-1.5V/V
Ci=1µF
A-Weighting
3µ
2µ
20µ
20
100
1k
Frequency (Hz)
10k 20k
Right channel
10µ
7µ
5µ
VDD=3.3V
RL=100kΩ
AV=-1.5V/V
Ci=1µF
A-Weighting
3µ
2µ
1µ
1µ
Left channel
20
Frequency Response
+200
+3
VDD=3.3V
Av=-1.5V/V
RL=600Ω
Ci=1µF
100
1k
10k
Frequency (Hz)
Gain (dB)
+180
Phase (deg)
Gain (dB)
+4
Phase
+2
+0
10
+220
Gain
Phase
+160
+1
+140
200k
+0
+180
VDD=3.3V
Av=-1.5V/V
RL=100kΩ
Ci=1µF
10
-40
-50
VDD=3.3V
RL=600Ω
AV=-1.5V/V
Ci=1µF
Vrr=0.1Vrms
Right channel
-90
-100
-110
-120
20
1k
10k
Frequency (Hz)
+140
200k
PSRR vs. Frequency
-60
-70
-80
100
+160
-20
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
-30
+200
+2
PSRR vs. Frequency
+0
-10
-20
10k 20k
Frequency Response
+220
Gain
+1
1k
Frequency (Hz)
+4
+3
100
Phase (deg)
20µ
Output Noise Voltage (Vrms)
Output Noise Voltage (Vrms)
Output Noise Voltage vs. Frequency
50µ
Left channel
100
1k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
-30
-40
-50
-60
-70
6
Right channel
-80
-90
Left channel
-100
-110
-120
20
10k 20k
VDD=3.3V
RL=100kΩ
AV=-1.5V/V
Ci=1µF
Vrr=0.1Vrms
100
1k
Frequency (Hz)
10k 20k
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APA2175
Typical Operating Characteristics (Cont.)
Output Voltage FFT vs. Frequency
Supply Current vs. Supply Voltage
6
+0
VDD=3.3V
RL=600Ω
AV=-1V/V
VO=-60dB to 2Vrms
-40
5
Supply Current (mA)
Output Voltage FFT (dBr)
-20
-60
-80
-100
4
3
2
-120
1
-140
0
0
5k
10k
15k
Frequency (Hz)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Supply Voltage (V)
20k
GSM Power Supply Rejection vs.
Frequency
-60
-90
-120
-150
Supply Voltage (dBV)
+0
Output Voltage (dBV)
3.5 4.0 4.5
GSM Power Supply Rejection vs. Time
-30
+0
Av=-1.5V/V
No Load
1
-30
2
V DD
VLOUT
-60
-90
3
-120
-150
0
400
800
1.2k
1.6k
2k
CH1: VDD, 500mV/Div, DC, Offset=3.0V
CH2: VLOUT, 20mV/Div, DC
CH3: VROUT, 20mV/Div, DC
TIME:2ms/Div
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
VROUT
7
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APA2175
Operating Waveforms
Output Transient at Power On
Output Transient at Power Off
V DD
V DD
1
1
VLOUT
2
VLOUT
2
VROUT
VROUT
3
3
CH1: VDD, 1V/Div, DC
CH2: VLOUT, 20mV/Div, DC
CH3: VROUT, 20mV/Div, DC
TIME:10ms/Div
CH1: VDD, 1V/Div, DC
CH2: VLOUT, 20mV/Div, DC
CH3: VROUT, 20mV/Div, DC
TIME:2ms/Div
Shutdown Release
Shutdown
VS D
VSD
1
1
2
2
VLOUT
VLOUT
3
3
VROUT
VROUT
CH1: VSD, 1V/Div, DC
CH2: VLOUT, 1V/Div, DC
CH3: VROUT, 1V/Div, DC
TIME:10ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
CH1: VSD, 1V/Div, DC
CH2: VLOUT, 1V/Div, DC
CH3: VROUT, 1V/Div, DC
TIME:2ms/Div
8
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APA2175
Pin Description
PIN
NO.
NAME
I/O/P
FUNCTION
TQFN4x4-20B
TSSOP-16
1
4
CPP
I/O
2
5
PGND
P
3
6
CPN
I/O
4,6,8,12,
16,20
1,3
NC
-
No Connection.
5
7
CVSS
O
Charge pump output, connect to the “VSS”.
7
8
VSS
P
Line Driver negative power supply.
Charge pump flying capacitor positive connection.
Charge pump’s ground.
Charge pump flying capacitor negative connection.
9
9
LOUT
O
Left channel output for Line Driver.
10
10
VDD
P
Power supply.
11
11
ROUT
O
Right channel output for Line Driver.
13
12
LIN
I
Left channel input terminal.
14
13
RSD
I
Right channel shutdown mod control input signal, pull low for shutdown
the right channel line driver.
15
14
RIN
I
Right channel input terminal.
17
15
GND
P
Ground connection for circuitry.
18
16
LSD
I
Left channel shutdown mod control input signal, pull low for shutdown
the right channel line driver.
19
2
PVDD
P
Charge pump power supply.
Block Diagram
RIN
ROUT
GND
LIN
LOUT
PVDD
RSD
LSD
Shutdown
Circuit
PGND
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
Power and
Depop
Circuit
VDD VSS
9
CPP
Charge
Pump
CPN
CVSS
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APA2175
Typical Application Circuit
1. Inverting Amplifier
Ci1
ROUT
1µF
RIN
Right
Channel
Output
ROUT
AUDIO
GND
DAC
LIN
LOUT
LOUT
Ci2 1µF
PVDD
Shutdown
Control
RSD
LSD
Power
and
Depop
Circuit
Shutdown
ckt
VDD
PGND
CS
10µF
Charge
Pump
VDD VSS
VSS
VDD
Left
Channel
Output
CCPB
10µF
CPP
CCPF
CPN
2.2µF
CVSS
CCPO
2.2µF
0.1µF
2. Inverting Amplifier with First-Order Passive Low-Pass Filter
ROUT
R1 220Ω
C1
22nF
AUDIO
Ci1
1µF
RIN
R2
7.5kΩ
ROUT
GND
DAC
LOUT
C2
22nF
R4
7.5kΩ
R3 220Ω
Ci2 1µF
Shutdown
Control
RSD
LSD
LIN
Power
and
Depop
Circuit
VDD
CS
10µF
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
10
Left
Channel
V D Output
PVDD D
CCPB
2.2µF
CPP
CCPF
CPN 2.2µF
LOUT
Shutdown
ckt
PGND
Right
Channel
Output
Charge
Pump
VDD VSS
VSS
0.1µF
CVSS
CCPO
2.2µF
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APA2175
Function Description
Line Driver Operation
Shutdown Function
In order to reduce power consumption while not in use,
the APA2175 contains two shutdown controllers to allow
VDD
either channel being independent and externally turns off
the amplifier bias circuitry. LSD controls the left channel
VOUT
VDD/2
and RSD controls the right channel. This shutdown feature turns the amplifier off when logic low is placed on the
0
RSD and LSD pins for the APA2175. The trigger point between a logic high is 1.0V and logic low level is 0.35V. It is
Conventional Line Driver
VDD
recommended to switch between ground and the supply
voltage VDD to provide maximum device performance. By
0
charge pump is disabled, and IDD for the APA2175 is in
shutdown mode. The charge pump is enabled once ei-
switching the both RSD and LSD pins to the low level, the
amplifier enters a low-consumption current circumstance,
VOUT
ther RSD or LSD pin is pulled to high. In normal operating,
the APA2175’s RSD and LSD pins should be pulled to a
high level to keep the IC out of the shutdown mode. The
RSD and LSD pins should be tied to a definite voltage to
VSS
avoid unwanted circumstance changes.
Cap-free Line Driver
Figure 1. Cap-free Line Driver’s Operation
The APA2175’s line drivers use a charge pump to invert
the positive power supply (VDD) to negative power supply
(VSS), see figure1. The line drivers operate at this bipolar
power supply (VDD and VSS) and the outputs reference refers to the ground. This feature eliminates the output capacitor that is using in conventional single-ended line
drive amplifier. Compare with the single power supply
amplifier, the power supply range has almost doubled.
Thermal Protection
The thermal protection circuit limits the junction temperature of the APA2175. When the junction temperature exceeds TJ=+150OC, a thermal sensor turns off the driver,
allowing the devices to cool. The thermal sensor allows
the driver to start-up after the junction temperature down
about 125OC. The thermal protection is designed with a
25OC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of
the ICs.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
11
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APA2175
Application Information
equivalent-series- resistance (ESR) ceramic capacitor,
typically 0.1µF, is placed as close as possible to the de-
Input Capacitor, Ci
In the typical application, an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
vice VDD lead for the best performance. For filtering lower
frequency noise signals, a large aluminum electrolytic
DC level for optimum operation. In this case, Ci and the
minimum input impedance Ri from a high-pass filter with
capacitor of 10µF or greater placed near the audio power
amplifier is recommended.
the corner frequency are determined in the following
equation:
1
2πRiCi
Charge Pump Bypass Capacitor, C CPB
(1)
The bypass capacitor (CCPB) relates with the charge pump
switching transient. The capacitor’s value is same as fly-
The value of Ci must be considered carefully because it
ing capacitor (2.2µF). Place it close to the PVDD and PGND.
fC(highpass ) =
directly affects the low frequency performance of the circuit.
Charge Pump Flying Capacitor, CCPF
Ri is the internal input resistance that typical value is 18kΩ
The flying capacitor affects the load transient of the charge
pump. If the capacitor’s value is too small, then that will
and the specification calls for a flat bass response down
to 20Hz. Equation is reconfigured as below:
1
Ci =
2πRifc
degrade the charge pump’s current driver capability and
the performance of line drive amplifier.
(2)
Increasing the flying capacitor’s value will improve the
load transient of charge pump. It is recommended using
When the input resistance variation is considered, the Ci
is 0.44µF, so a value in the range of 0.47µF to 1µF would
be chosen. A further consideration for this capacitor is the
t he l o w ES R c er am i c cap ac it o rs ( X7R t ype i s
recommended) above 2.2µF.
leakage path from the input source through the input network (Ri + Rf, Ci) to the load.
Charge Pump Output Capacitor, CCPO
The output capacitor’s value affects the power ripple di-
This leakage current creates a DC offset voltage at the
input to the amplifier that reduces useful headroom, es-
rectly at CVSS (VSS). Increasing the value of output capacitor
reduces the power ripple. The ESR of output capacitor af-
pecially in high gain applications. For this reason, a low
leakage tantalum or ceramic capacitor is the best choice.
fects the load transient of CVSS (VSS). Lower ESR and greater
than 2.2µF ceramic capacitor is a recommendation.
When polarized capacitors are used, the negative side of
the capacitor should face the amplifiers’ input in most
Layout Consideration
applications because the DC level of the amplifiers’ input is held at GND. Please note that it is important to
ThermalVia
Diameter
0.3mm X 5
confirm the capacitor polarity in the application.
0.8mm
Power Supply Decoupling, CS
0.35mm
ensure the output total harmonic distortion (THD+N) is
as low as possible. Power supply decoupling also pre-
0.5mm
vents the oscillations being caused by long lead length
between the amplifier and the speaker.
2.2mm
Ground
Plane for
ThermalPAD
The optimum decoupling is achieved by using two different types of capacitors that target on different types of
noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jul., 2010
4.9mm
2.2mm
The APA2175 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
Figure 2. TQFN4x4-20B Layout Recommendation
12
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APA2175
Application Information (Cont.)
Layout Consideration (Cont.)
1. All components should be placed close to the APA2175.
For example, the input capacitor (Ci) should be close to
APA2175’s input pins to avoid causing noise coupling
to APA2175’s high impedance inputs; the decoupling
capacitor (CS) should be placed by the APA2175’s power
pin to decouple the power rail noise.
2. The output traces should be short and wide (>20mil).
3. The input trace should be short and symmetric.
4. The power trace width should be greater than 20mil.
5. The TQFN Thermal PAD should be soldered on PCB,
and the ground plane needs soldered mask (to avoid
short circuit) except the Thermal PAD area.
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APA2175
Package Information
TQFN4x4-20B
D
b
E
A
Pin 1
D2
A1
A3
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TQFN4x4-20B
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.30
0.008
0.012
0.161
A3
b
0.20 REF
0.18
0.008 REF
D
3.90
4.10
0.154
D2
2.00
2.70
0.079
0.106
E
3.90
4.10
0.154
0.161
E2
2.00
2.70
0.079
0.106
0.45
0.014
e
0.50 BSC
L
0.35
K
0.20
0.020 BSC
0.018
0.008
Note : 1. Followed from JEDEC MO-220 VGGD-5.
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APA2175
Package Information
TSSOP-16
D
e
E
E1
SEE VIEW A
C
0.25
A
A2
b
GAUGE PLANE
A1
SEATING PLANE
VIEW A
S
Y
M
B
O
L
L
TSSOP-16
MILLIMETERS
MIN.
INCHES
MIN.
MAX.
A
MAX.
0.047
1.20
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.031
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.008
D
4.90
5.10
0.193
0.201
E
6.20
6.60
0.244
0.260
E1
4.30
4.50
0.169
0.177
e
L
0
0.65 BSC
0.45
0o
0.026 BSC
0.018
0.75
8o
0o
0.030
8o
Note : 1. Follow from JEDEC MO-153 AB.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
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APA2175
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
330.0±2.00
50 MIN.
P0
P1
TQFN4x4-20B
4.0±0.10
8.0±0.10
A
H
Application
330.0±2.00
50 MIN.
P0
P1
TSSOP-16
4.00±0.10
8.00±0.10
T1
C
12.4+2.00 13.0+0.50
-0.00
-0.20
d
D
W
E1
F
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±0.20
1.30±0.20
T1
C
d
D
W
E1
F
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.50±0.05
D1
T
A0
B0
K0
1.5 MIN.
0.6+0.00
-0.40
6.90±0.20
5.40±0.20
1.60±0.20
12.4+2.00 13.0+0.50
-0.00
-0.20
P2
D0
2.00±0.05
1.5+0.10
-0.00
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TQFN4x4-20B
Tape & Reel
3000
TSSOP-16
Tape & Reel
2500
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APA2175
Taping Direction Information
TQFN4x4-20B
USER DIRECTION OF FEED
TSSOP-16
USER DIRECTION OF FEED
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APA2175
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
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APA2175
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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