AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY DRAM 1 MEG x 16 DRAM 3.3V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT (Top View) • MIL-STD 883 • SMD Planned 44/50-Pin SOJ/LCC/Gull Wing 450mil FEATURES • JEDEC- and industry-standard x16 timing, functions, pinouts and packages • High-performance CMOS silicon-gate process • Single +3.3V ±0.3V power supply • All device pins are TTL-compatible • Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR), HIDDEN • BYTE WRITE access cycles • 1,024-cycle refresh (10 row-, 10 column-addresses) • Low power, 0.3mW standby; 180mW active, typical • Extended Data-Out (EDO) PAGE access cycle • 5V-tolerant I/Os (5.5V maximum VIH level) OPTIONS MARKING • Timing 60ns access (Contact Factory) 70ns access 80ns access -6 -7 -8 • Refresh Rate Standard 16ms period ECJ No. 506 ECG No. 604 EC No. 213 tRAC 60ns 70ns 80ns tPC 25ns 30ns 40ns tAA 30ns 35ns 40ns tCAC 15ns 20ns 20ns tCAS 12ns 12ns 20ns GENERAL DESCRIPTION The AS4LC1M16 is a randomly accessed solid-state memory containing 16,777,216 bits organized in a x16 configuration. The AS4LC1M16 has both BYTE WRITE and WORD WRITE access cycles via two ?C?A/S pins (?C?A?S/L and ?C?A?S?H). These function in a similar manner to a single ?C?AS of other DRAMs in that either ?C?A?S/L or C ? ?A?S?H will generate AS4LC1M16 REV. 3/97 DS000020 50 49 48 47 46 45 44 43 42 41 40 Vss DQ16 DQ15 DQ14 DQ13 Vss DQ12 DQ11 DQ10 DQ9 NC NC NC WE RAS NC NC A0 A1 A2 A3 Vcc 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC CASL CASH OE A9 A8 A7 A6 A5 A4 Vss an internal ?C?A/S. The AS4LC1M16 ?C?A/S function and timing are determined by the first ?C?A/S (?C?A?S/L or ?C?A?S?H) to transition LOW and the last ?C?A/S to transition back HIGH. Use of only one of the two results in a BYTE WRITE cycle. ?CA ? S ? L / transitioning LOW selects an access cycle for the lower byte (DQ1-DQ8) and ?C?A?S?H transitioning LOW selects an access cycle for the upper byte (DQ9-DQ16). Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered 10 bits (A0 -A9) at a time. ?R?A/S is used to latch the first 10 bits and ?C?A/S the latter 10 bits. The ?C?A/S function also determines whether the cycle will be a refresh cycle (?R?A/S ONLY) or an active cycle (READ, WRITE or READ WRITE) once ?R?A/S goes LOW. KEY TIMING PARAMETERS tRC 105ns 125ns 150ns 1 2 3 4 5 6 7 8 9 10 11 None • Packages Ceramic SOJ Ceramic Gull Wing Ceramic LCC SPEED -6 -7 -8 Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC 2-93 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY GENERAL DESCRIPTION (continued) PAGE ACCESS The ?C?A/S/L and ?C?A/S?H inputs internally generate a ?C?A/S signal functioning in a similar manner to the single ?C?A/S input of other DRAMs. The key difference is each ?C?A/S input ( ?C?A/S/L and ?C?A/S?H ) controls its corresponding 8 DQ inputs during WRITE accesses. ?C?A/S/L controls DQ1 through DQ8 and ?C?A/S?H controls DQ9 through DQ16. The two ?C?A/S controls give the MT4LC1M16E5(S) both BYTE READ and BYTE WRITE cycle capabilities. A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or ?C?A/S (?C?AS / /L or ?C?A/S/H), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either ?C?A/S falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE falls after ?C?A/S (?C?A/S/L or ?C?A/S/H) was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of ?O/E. During LATE WRITE or READ-MODIFY-WRITE cycles, ?O/E must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping ?O/E LOW, no write will occur, and the data-outputs will drive read data from the accessed location. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direction is controlled by ?O/E and ?W/E. PAGE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row-addressdefined page boundary. The PAGE cycle is always initiated with a row-address strobed-in by ?R?A/S followed by a column-address strobed-in by C ? ?A/S. ?C?A/S may be toggled-in by holding ?R?A/S LOW and strobing-in different columnaddresses, thus executing faster memory cycles. Returning ?R?A/S HIGH terminates the PAGE MODE of operation. RAS EDO PAGE MODE The AS4LC1M16 provides EDO PAGE MODE which is an accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after ?C?A/S returns HIGH. EDO provides for ?C?A/S precharge time (tCP) to occur without the output data going invalid. This elimination of ?C?A/S output control provides for pipeline READs. FAST-PAGE-MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of ?C?A /S. EDO-PAGE-MODE DRAMs operate similar to FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after ?C?A/S goes HIGH during READs, provided ?R?A/S and ?O/E are held LOW. If ?O/E is pulsed while ?R?A/S and ?C?A/S are LOW, data will toggle from valid data to High-Z and back to the same valid data. If ?O/E is toggled or pulsed after ?C?A/S goes HIGH while ?R?A/S remains LOW, data will transition to and remain High-Z (refer to Figure 1). V IH V IL ,, ,,, ,,,,,, ,,,,, ,,,,,, ,,,, , , , , CASL/CASH ADDR V IH V IL V IH V IL DQ V IOH V IOL ROW COLUMN (A) OPEN COLUMN (B) ,, VALID DATA (A) VALID DATA (A) t OD OE V IH V IL COLUMN (C) ,,, ,, VALID DATA (C) VALID DATA (B) t OD t OES t OE COLUMN (D) t OEHC t OEP The DQs go back to Low-Z if tOES is met. The DQs remain High-Z until the next CAS cycle if tOEHC is met. , VALID DATA (D) t OD , ,,, The DQs remain High-Z until the next CAS cycle if tOEP is met. DON’T CARE ,, UNDEFINED Figure 1 OUTPUT ENABLE AND DISABLE AS4LC1M16 REV. 3/97 DS000020 2-94 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY EDO PAGE MODE (continued) tively, pulsing ?W/E to the idle banks during ?C?A/S HIGH time will also High-Z the outputs. Independent of ?O/E control, the outputs will disable after tOFF, which is referenced from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last. ?W/E can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 2. During an application, if the DQ outputs are wire OR’d, ?O/E must be used to disable idle banks of DRAMs. Alterna- ,, ,,, ,,,,,,, ,,,,, ,,,,, ,,, ,,, ,, RAS V IH V IL CASL/CASH V IH V IL ADDR V IH V IL DQ V IOH V IOL WE V IH V IL OE V IH V IL ROW COLUMN (A) OPEN COLUMN (B) ,, COLUMN (C) , VALID DATA (A) t WHZ t WPZ The DQs go to High-Z if WE falls, and if tWPZ is met, will remain High-Z until CAS goes LOW with WE HIGH (i.e., until a READ cycle is initiated). VALID DATA (B) COLUMN (D) ,, INPUT DATA (C) t WHZ ,, ,, ,,, WE may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS goes LOW with WE HIGH (i.e., until a READ cycle is initiated). DON’T CARE UNDEFINED Figure 2 ?W/E CONTROL OF DQs AS4LC1M16 REV. 3/97 DS000020 2-95 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY BYTE ACCESS CYCLE WRITE on one byte and a LATE WRITE on the other byte is not allowed during the same cycle. However, an EARLY WRITE on one byte and, after a ?C?A/S precharge has been satisfied, a LATE WRITE on the other byte is permissable. The BYTE WRITEs and BYTE READs are determined by the use of ?C?A/S/L and ?C?A/S?H. Enabling ?C?A/S/L will select a lower BYTE access (DQ1-DQ8). Enabling ?C?A/S?H will select an upper BYTE access (DQ9-DQ16). Enabling both ?C?A/S/L and ?C?A/S?H selects a WORD WRITE cycle. The AS4LC1M16 may be viewed as two 1 Meg x 8 DRAMs that have common input controls, with the exception of the / ?C?A/S inputs. Figure 3 illustrates the BYTE WRITE and WORD WRITE cycles. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A ?C?A/S precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY REFRESH Preserve correct memory cell data by maintaining power and executing a ?R?A/S cycle (READ, WRITE) or ?R?A/S refresh cycle (?R?A/S ONLY, CBR, or HIDDEN) so that all 1,024 combinations of R ? A ? S / addresses are executed at least every 16ms, regardless of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic ?R?A/S addressing. WORD WRITE LOWER BYTE WRITE RAS CASL CASH WE LOWER BYTE (DQ1-DQ8) OF WORD UPPER BYTE (DQ9-DQ16) OF WORD STORED DATA 1 1 0 1 1 1 1 1 INPUT DATA 0 0 1 0 0 0 0 0 INPUT DATA 0 1 0 1 0 0 X X X X X X 1 0 1 0 1 1 0 0 X X 1 1 STORED STORED DATA DATA 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 INPUT DATA 1 1 0 1 1 1 1 1 INPUT DATA STORED DATA 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 X X X X X X X 1 0 1 0 1 1 1 1 1 X 1 ADDRESS 0 ADDRESS 1 X = NOT EFFECTIVE (DON'T CARE) Figure 3 WORD AND BYTE WRITE EXAMPLE AS4LC1M16 REV. 3/97 DS000020 2-96 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY FUNCTIONAL BLOCK DIAGRAM WE CASL DATA-IN BUFFER CAS CASH DQ1 16 NO. 2 CLOCK GENERATOR 10 DQ16 DATA-OUT BUFFER COLUMNADDRESS BUFFER 10 COLUMN DECODER OE 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 REFRESH CONTROLLER 16 SENSE AMPLIFIERS I/O GATING REFRESH COUNTER 1024 x 16 ROWADDRESS BUFFERS (10) 10 ROW DECODER 10 10 RAS 1024 NO. 1 CLOCK GENERATOR 1024 1024 x 1024 x 16 MEMORY ARRAY Vcc Vss AS4LC1M16 REV. 3/97 DS000020 2-97 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY TRUTH TABLE ADDRESSES ?R?A/S ?C?A/S/L ?C?A/S/H ?W/E ?O/E tR tC DQs Standby H H>X H>X X X X X High-Z READ: WORD L L L H L ROW COL Data-Out READ: LOWER BYTE L L H H L ROW COL Lower Byte, Upper Byte, Data-Out READ: UPPER BYTE L H L H L ROW COL Lower Byte, Data-Out Upper Byte WRITE: WORD (EARLY WRITE) L L L L X ROW COL Data-In WRITE: LOWER BYTE (EARLY) L L H L X ROW COL Lower Byte, Data-In Upper Byte, High-Z WRITE: UPPER BYTE (EARLY) L H L L X ROW COL Lower Byte, High-Z Upper Byte, Data-In READ WRITE L L L H>L L>H ROW COL Data-Out, Data-In 1, 2 EDO-PAGE-MODE 1st Cycle L H>L H>L H L ROW COL Data-Out 2 READ 2nd Cycle L H>L H>L H L n/a COL Data-Out 2 Any Cycle L L>H L>H H L n/a n/a Data-Out 2 L H>L H>L L X ROW COL Data-In 1 FUNCTION EDO-PAGE-MODE 1st Cycle WRITE 2nd Cycle EDO-PAGE-MODE 1st Cycle NOTES L H>L H>L L X n/a COL Data-In 1 L H>L H>L H>L L>H ROW COL Data-Out, Data-In 1, 2 1, 2 READ-WRITE 2nd Cycle L H>L H>L H>L L>H n/a COL Data-Out, Data-In HIDDEN READ L>H>L L L H L ROW COL Data-Out 2 REFRESH WRITE L>H>L L L L X ROW COL Data-In 1, 3 L H H X X ROW n/a High-Z H>L L L H X X X High-Z ?R?A/S-ONLY REFRESH CBR REFRESH NOTE: AS4LC1M16 REV. 3/97 DS000020 4 1. These WRITE cycles may also be BYTE WRITE cycles (either ?C?A/S/L or ?C?A/S/H active). 2. These READ cycles may also be BYTE READ cycles (either ?C?A/S/L or ?C?A/S/H active). 3. EARLY WRITE only. 4. Only one ?C?A/S must be active (?C?A/S/L or ?C?A/S/H). 2-98 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on VCC pin Relative to VSS .............. -1.0V to +4.6V Voltage on NC, Inputs or I/O pins Relative to Vss ................................................. -1.0V to +5.5V Operating Temperature, TA (ambient) ..... TA(MIN)=-55°C ...................................................................... TC(MAX)=125°C Storage Temperature ................................... -55°C to +150°C Power Dissipation ............................................................. 1W Short Circuit Output Current ..................................... 50mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (Notes: 1, 2, 3) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS Supply Voltage VCC 3.0 3.6 V Input High (Logic 1) Voltage, all inputs (including NC pins) VIH 2.0 VCC+1 V Input Low (Logic 0) Voltage, all inputs (including NC pins) VIL -1.0 0.8 V II -2 2 µA OUTPUT LEAKAGE CURRENT (Q is disabled; 0V ≤ VOUT ≤ 5.5V) VCC=3.6V IOZ -10 10 µA OUTPUT LEVELS Output High Voltage (IOUT = -2.0mA) Output Low Voltage (IOUT = 2.0mA) VOH 2.4 INPUT LEAKAGE CURRENT Any input 0V ≤ VIN ≤ 5.5V (All other pins not under test = 0V) VCC = 3.6V NOTES 4 V VOL 0.4 V MAX PARAMETER/CONDITION SYMBOL -6 -7 -8 STANDBY CURRENT: (TTL) (?R?A/S = ?C?A/S = VIH) ICC1 2 2 2 mA STANDBY CURRENT: (CMOS) (?R?A/S = ?C?A/S = other inputs = VCC -0.2V) ICC2 1 1 1 mA OPERATING CURRENT: Random READ/WRITE Average power supply current (?R?A/S, ?C?A/S address cycling: tRC = tRC [MIN]) ICC3 170 155 140 mA 5, 6 OPERATING CURRENT: EDO PAGE MODE Average power supply current (?R?A/S = VIL, ?C?A/S, address cycling: tPC = tPC [MIN]) ICC4 130 120 110 mA 5, 6 REFRESH CURRENT: ?R?A/S ONLY Average power supply current (?R?A/S cycling, ?C?A/S=VIH: tRC = tRC [MIN]) ICC5 160 145 130 mA 5, 6 REFRESH CURRENT: CBR Average power supply current (?R?A/S, ?C?A/S address cycling: tRC = tRC [MIN]) ICC6 150 140 130 mA 5, 7 AS4LC1M16 REV. 3/97 DS000020 2-99 UNITS NOTES Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY CAPACITANCE PARAMETER SYMBOL MAX UNITS NOTES Input Capacitance: Addresses CI 1 7 pF 8 Input Capacitance: ?R?A/S, ?C?A/S/L,?C?A/S/H, ?W/E, ?O/E CI 2 7 pF 8 Input/Output Capacitance: DQ CIO 8 pF 8 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 2, 3, 6, 9, 10, 11, 12,) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Access time from column-address Column-address set-up to ?C?A/S precharge Column-address hold time (referenced to ?R?A/S) Column-address setup time Row-address setup time Column-address to ?W/E delay time Access time from ?C?A/S Column-address hold time ?C?A/S pulse width ?C?A/S hold time (CBR REFRESH) Last ?C?A/S going LOW to first ?C?A/S to return HIGH ?C?A/S to output in Low-Z Data output hold after next ?C?A/S LOW ?C?A/S precharge time Access time from ?C?A/S precharge ?C?A/S to ?R?A/S precharge time ?C?A/S hold time ?C?A/S setup time (CBR REFRESH) ?C?A/S to ?W/E delay time Write command to ?C?A/S lead time Data-in hold time Data-in hold time (referenced to ?R?A/S) Data-in setup time Output disable Output Enable O ? E / hold time from W ? E / during READ-MODIFY-WRITE cycle ?O/E HIGH hold from ?C?A/S HIGH ?O/E HIGH pulse width AS4LC1M16 REV. 3/97 DS000020 -6 SYM tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDHR tDS tOD tOE tOEH tOEHC tOEP MIN -7 MAX 30 MIN 15 45 0 0 55 15 50 0 0 60 15 10 12 10 10 0 3 10 10,000 12 10 10 2-100 15 15 MIN 10,000 20 15 15 15 15 0 3 10 40 5 55 5 40 15 12 55 0 0 12 10 10 MAX 40 25 60 0 0 65 20 12 13 12 10 0 3 10 35 5 50 5 35 15 10 45 0 0 -8 MAX 35 15 20 10,000 40 5 60 10 45 20 15 60 0 0 15 10 10 15 20 UNITS NOTES ns ns ns ns 25 ns 25 ns 13 ns 14, 26 ns 25 ns 27 ns 7, 28 ns 29 ns 26 ns ns 15, 30 ns 26 ns 28 ns 28 ns 7, 25 ns 13, 25 ns 28 ns 16, 26 ns ns 16, 26 ns ns 17, 26 ns 18 ns 18 ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 2, 3, 6, 9, 10, 11, 12, 20) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER ?O/E LOW to ?C?A/S HIGH setup time Output buffer turn-off delay O ? E / setup prior to R ? A ? S / during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from ?R?A/S ?R?A/S to column-address delay time Row-address hold time Column-address to ?R?A/S lead time ?R?A/S pulse width ?R?A/S pulse width (EDO PAGE MODE) Random READ or WRITE cycle time ?R?A/S to ?C?A/S delay time Read command hold time (referenced to ?C?A/S) Read command setup time Refresh period (1,024 cycles) ?R?A/S precharge time ?R?A/S to ?C?A/S precharge time Read command hold time (referenced to ?R?A/S) ?R?A/S hold time READ WRITE cycle time ?R?A/S to ?W/E delay time Write command to ?R?A/S lead time Transition time (rise or fall) Write command hold time Write command hold time (referenced to ?R?A/S) ?W/E command setup time Output disable delay from ?W/E Write command pulse width ?W/E pulse width to disable at ?C?A/S HIGH ?W/E hold time (CBR REFRESH) ?W/E setup time (CBR REFRESH) AS4LC1M16 REV. 3/97 DS000020 -6 SYM tOES tOFF tORD tPC tPRWC tRAC tRAD tRAH tRAL tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP MIN 5 0 0 30 75 12 10 30 60 60 110 14 0 0 -7 MAX 15 60 30 10,000 100,000 45 MIN 5 0 0 35 85 12 10 35 70 70 130 14 0 0 16 40 5 0 13 150 80 15 2 10 45 0 0 10 10 10 10 2-101 50 13 -8 MAX 15 70 35 10,000 100,000 50 MIN 10 0 0 40 90 15 10 40 80 80 150 16 0 0 16 50 5 0 15 180 90 18 2 12 55 0 0 12 12 10 10 50 15 60 5 0 20 200 105 20 2 15 60 0 0 15 15 10 10 MAX UNITS ns 20 ns ns ns ns 80 ns 40 ns ns ns 10,000 ns 100,000 ns ns 60 ns ns ns 16 ms ns ns ns ns ns ns ns 50 ns ns ns ns 20 ns ns ns ns ns NOTES 20, 26 31 31 19 21 22, 25 23, 28 25 23 32 13 32 13, 25 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. AS4LC1M16 883C 1 MEG x 16 DRAM PRELIMINARY NOTES 1. All voltages referenced to VSS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0˚C ≤ TA ≤ 70˚C) is assured. 3. An initial pause of 100µs is required after power-up followed by eight ?R?A/S refresh cycles (?R?A/S ONLY or CBR with ?W/E HIGH) before proper device operation is assured. The eight ?R?A/S cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 4. NC pins are assumed to be left floating and are not tested for leakage. 5. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. Column address changed once each cycle. 7. Enables on-chip refresh and address counters. 8. This parameter is sampled. VCC = +3.0V; f = 1 MHz. 9. AC characteristics assume tT = 2.5ns. 10. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 11. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 12. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2.0V. 13. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. ?O/E held HIGH and ?W/E taken LOW after ?C?A/S goes LOW results in a LATE WRITE (?O/E-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 14. Assumes that tRCD ≥ tRCD (MAX). 15. If ?C?A/S is LOW at the falling edge of ?R?A/S, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, ?C?A/S must be pulsed HIGH for tCP. 16. These parameters are referenced to ?C?A/S leading edge in EARLY WRITE cycles and ?W/E leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. AS4LC1M16 REV. 3/97 DS000020 17. If ?O/E is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, ?W/E must be pulsed during ?C?A/S HIGH time in order to place I/O buffers in High-Z. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (?O/E HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if ?C?A/S remains LOW and ?O/E is taken back LOW after tOEH is met. If ?C?A/S goes HIGH prior to ?O/E going back LOW, the DQs will remain open. 19. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 20. tOFF (MAX) defines the time at which the output achieves the open circuit condition, and is not referenced to VOH or VOL. It is referenced from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last. 21. Operation within the tRAD (MAX) limit ensures that tRAC (MIN) and tCAC (MIN) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, then access time is controlled exclusively by tAA, provided tRCD is not exceeded. 22. Operation within the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, then access time is controlled exclusively by tCAC, provided tRAD is not exceeded. 23. Either tRCH or tRRH must be satisfied for a READ cycle. 24. The first ?C?A/Sx edge to transition LOW. 25. Output parameter (DQx) is referenced to corresponding ?C?A/S input; DQ1-DQ8 by ?C?A/S/L and DQ9-DQ16 by ?C?A/S?H. 26. Each ?C?A/Sx must meet minimum pulse width. 27. The last ?C?A/Sx edge to transition HIGH. 28. Last falling ?C?A/Sx edge to first rising ?C?A/Sx edge. 29. Last rising ?C?A/Sx edge to first falling ?C?A/Sx edge. 30. Last rising ?C?A/Sx edge to next cycle’s last rising ?C?A/Sx edge. 31. Last ?C?A/Sx to go LOW. 32. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, ?W/E = LOW and ?O/E = HIGH. 2-102 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY READ CYCLE tRC tRP tRAS V IH V IL RAS tCSH tRRH tRSH tRCD tCRP tCAS tCLCH , , , , , , , ,, ,, , ,,,,,,,, ,, , ,, , , , , , , ,, , , , ,, ,, ,,,, ,, ,,,, ,, V IH V IL CASL/CASH tAR tRAD tASR tRAL tRAH tASC tCAH tACH V IH V IL ADDR ROW tWRP WE V IH V IL ROW COLUMN tWRH tRCH tRCS NOTE 1 tAA tRAC NOTE 2 tOFF tCAC tCLZ DQ V OH V OL OPEN OE OPEN VALID DATA t OE t OD V IH V IL DON’T CARE UNDEFINED NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. tOFF is referenced from rising edge of ?R?A/S or ?C?A/S, whichever occurs last. TIMING PARAMETERS -6 SYM MIN tAA tACH 15 tAR 45 tASC 0 tASR 0 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCRP 5 tCSH 50 tOD 0 tOE tOFF 0 AS4LC1M16 REV. 3/97 DS000020 -7 MAX 30 MIN 15 50 0 0 15 10,000 15 15 15 MIN 0 MAX 40 20 60 0 0 20 12 13 10 0 5 55 0 -6 -8 MAX 35 10,000 15 20 15 20 15 20 10 0 5 60 0 0 10,000 20 20 20 SYM tRAC tRAD tRAH tRAL tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH tWRH tWRP UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2-103 MIN 12 10 30 60 110 14 0 0 40 0 13 10 10 -7 MAX 60 30 10,000 45 MIN 12 10 35 70 130 14 0 0 50 0 15 10 10 -8 MAX 70 35 10,000 50 MIN 15 10 40 80 150 20 0 0 60 0 15 10 10 MAX 80 40 10,000 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY EARLY WRITE CYCLE tRC tRAS RAS tRP V IH V IL tCSH tRSH , , , , , ,, ,,,,,, ,,,,,,,,, ,,,,,,,,,, , , , , , , ,, , ,,,,,, ,,,,,,,, , , , , , , , ,,, tCRP CASL/CASH tRCD tCAS tCLCH V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tRAL tASC ROW tCAH tACH ROW COLUMN tCWL tRWL tWCR tWCS tWRP WE V IH V IL tWCH tWRH tWP NOTE 1 tDHR tDS V DQ V IOH IOL OE tDH VALID DATA V IH V IL , DON’T CARE UNDEFINED NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. TIMING PARAMETERS -6 SYM MIN tACH 15 tAR 45 tASC 0 tASR 0 tCAH 10 tCAS 12 tCLCH 10 tCRP 5 tCSH 50 tCWL 15 tDH 10 tDHR 45 tDS 0 tRAD 12 AS4LC1M16 REV. 3/97 DS000020 MAX 10,000 30 -7 MIN MAX 15 50 0 0 12 13 10,000 10 5 55 15 12 55 0 12 35 -8 MIN MAX 20 60 0 0 15 20 10,000 10 5 60 20 15 55 0 15 40 -6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tRAH tRAL tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP tWRH tWRP 2-104 MIN 10 30 60 110 14 40 13 15 10 45 0 10 10 10 MAX 10,000 45 -7 MIN MAX 10 35 70 10,000 130 14 50 50 15 15 12 55 0 12 10 10 -8 MIN MAX 10 40 80 10,000 150 20 60 60 0 20 15 60 0 15 10 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS RAS tRP V IH V IL tCSH tRSH , , , , ,, , , , , ,,,,,,,, , , , , , , , ,, , , , ,, , , , ,,,,,,,,,,, ,,,,,, tCRP CASL/CASH tRCD tCAS, tCLCH V IH V IL tAR tRAD tASR ADDR V IH V IL tRAL tASC tRAH ROW tCAH tRCS tWRP WE V IH V IL tACH COLUMN tWRH NOTE 1 ROW tRWD tCWD tCWL tAWD tWP tRWL tAA tRAC tCAC tDS t CLZ V DQ V IOH IOL VALID D OUT OPEN tOE OE tDH VALID D IN tOD OPEN tOEH V IH V IL , DON’T CARE UNDEFINED NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. TIMING PARAMETERS -6 SYM MIN tAA tACH 15 tAR 45 tASC 0 tASR 0 tAWD 55 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCRP 5 tCSH 50 tCWD 35 tCWL 15 tDH 10 tDS 0 tOD 0 AS4LC1M16 REV. 3/97 DS000020 -7 MAX 30 MIN -8 MAX 35 15 50 0 0 60 15 10,000 15 MIN 20 60 0 0 65 20 12 13 10 0 5 55 40 15 12 0 0 -6 MAX 40 10,000 15 20 15 20 10 0 5 60 45 20 15 0 0 10,000 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tOE tOEH tRAC tRAD tRAH tRAL tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP tWRH tWRP 2-105 MIN -7 MAX 15 12 12 10 30 60 14 0 40 13 150 80 15 10 10 10 MIN -8 MAX 20 12 60 30 10,000 45 12 10 35 70 14 0 50 15 180 90 15 12 10 10 MIN MAX 20 15 70 35 10,000 50 15 10 40 80 20 0 60 15 200 105 20 15 10 10 80 40 10,000 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY EDO-PAGE-MODE READ CYCLE tRASP RAS V IH V IL tCSH tCAS, t CLCH tRCD tCAS, t CLCH tCP , , , , ,,, ,,,, ,, , ,, , ,,,,,,,, , V IH V IL tAR tACH tACH tRAD tASR ADDR V IH V IL WE tRAH tASC tWRH tRCS ROW tWRP V IH V IL tCAH COLUMN NOTE 1 NOTE: tCAH COLUMN ROW tRRH tAA tCPA tCPA tCAC tCAC tCLZ VALID DATA tOES tOFF tOEHC tCOH tOE V IH V IL tASC tAA tCLZ OE , , , , , ,, ,, ,, , , ,, , , ,,, , ,,, tCAH tRCH tCAC OPEN tCP tACH COLUMN tAA V OH V OL tCP tRAL tASC tRAC DQ tRSH tCAS, t CLCH tPC tCRP CASL/CASH tRP VALID DATA VALID DATA OPEN tOE tOD tOD tOES tOEP DON’T CARE UNDEFINED 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. TIMING PARAMETERS -6 SYM MIN tAA tACH 15 tAR 45 tASC 0 tASR 0 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCOH 3 tCP 10 tCPA tCRP 5 tCSH 50 tOD 0 tOE tOEHC 10 AS4LC1M16 REV. 3/97 DS000020 -7 MAX 30 MIN -8 MAX 35 15 50 0 0 15 10,000 12 13 10 0 3 10 10,000 20 15 20 10 0 5 10 40 5 55 0 10 -6 MAX 40 20 60 0 0 20 35 15 15 MIN 15 20 10,000 40 5 60 0 10 20 20 SYM tOEP tOES tOFF tPC tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRP tRRH tRSH tWRH tWRP UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2-106 MIN 10 5 3 30 12 10 30 60 14 0 0 40 0 13 10 10 -7 MAX 15 60 30 100,000 45 MIN 10 5 3 35 12 10 35 70 14 0 0 50 0 15 10 10 -8 MAX 15 70 35 100,000 50 MIN 10 5 0 40 15 10 40 80 20 0 0 60 0 15 10 10 MAX UNITS ns ns 20 ns ns 80 ns 40 ns ns ns 100,000 ns 60 ns ns ns ns ns ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY EDO-PAGE-MODE EARLY-WRITE CYCLE tRP tRASP RAS V IH V IL tCSH tPC tRSH tCAS, tCLCH , ,, ,, ,,,, ,,, ,,, , , , , , , , , , , , , ,, , , ,, , ,,, , , , , , , , , , , , , ,,,, ,, ,, ,,,, ,,, , tCRP CASL/CASH tRCD tCAS, tCLCH tCP tCAS, tCLCH tCP tAR tRAD tASR ADDR V IH V IL tRAH tACH tACH tASC ROW tACH tASC tCAH COLUMN tWCS tWRP V IH V IL tWCH tWRH tASC tWCS tRAL tCAH COLUMN tCWL tWP NOTE 1 tCAH COLUMN tCWL WE tCP V IH V IL ROW tCWL tWCH tWCS tWP tWCH tWP tRWL tWCR tDHR tDS V DQ V IOH IOL OE tDH tDS VALID DATA tDH tDS VALID DATA tDH VALID DATA V IH V IL , DON’T CARE UNDEFINED NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. TIMING PARAMETERS -6 SYM MIN tACH 15 tAR 45 tASC 0 tASR 0 tCAH 10 tCAS 12 tCLCH 10 tCP 10 tCRP 5 tCSH 50 tCWL 15 tDH 10 tDHR 45 tDS 0 tPC 25 AS4LC1M16 REV. 3/97 DS000020 -7 MAX 10,000 MIN 15 50 0 0 12 13 10 10 5 55 15 12 55 0 30 -6 -8 MAX 10,000 MIN 20 60 0 0 15 20 10 10 5 60 20 15 55 0 40 MAX 10,000 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYM tRAD tRAH tRAL tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP tWRH tWRP 2-107 MIN 12 10 30 60 14 40 13 15 10 45 0 10 10 10 MAX 30 125,000 45 -7 -8 MIN MAX MIN MAX UNITS 12 35 15 40 ns 10 10 ns 35 40 ns 70 125,000 80 100,000 ns 14 50 20 60 ns 50 60 ns 15 15 ns 15 20 ns 12 15 ns 55 60 ns 0 0 ns 12 15 ns 10 10 ns 10 10 ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP tRP V IH V IL RAS tCSH tCRP tPRWC NOTE 1 t PC tRCD tCP tCAS, tCLCH tRSH , , , , , , , , ,, , , , , , , ,,,, ,, ,, , , , , ,,,,,, CASL/CASH tCP tCAS, tCLCH V IH V IL tAR tRAD tASR V IH V IL ADDR tRAH tASC ROW tCAH tASC COLUMN tWRP WE V IH V IL tWRH tASC COLUMN NOTE 2 tCWL tWP tAWD tCWL tWP tAWD tCWD tCWD tAA tDH tCPA tDS tCAC tCLZ DQ V IOH V IOL VALID D OUT VALID D IN tOE OE NOTE: tCWD tAA tCPA tCAC tCLZ VALID D IN tOD tCWL tWP tAWD tDS tCLZ VALID D OUT OPEN ROW tRWL tDH tCAC tCAH COLUMN tAA tRAC , ,,, ,,,, , , ,, , ,, , tRAL tCAH tRWD tRCS tCP tCAS, tCLCH tOD tOE V IH V IL tDH tDS VALID D OUT VALID D IN OPEN tOD t OEH tOE DON’T CARE UNDEFINED 1. tPC is for LATE WRITE cycles only. 2. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. TIMING PARAMETERS -6 SYM MIN tAA tAR 45 tASC 0 tASR 0 tAWD 55 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCP 10 tCPA tCRP 5 tCSH 50 tCWD 35 tCWL 15 tDH 10 tDS 0 tOD 0 AS4LC1M16 REV. 3/97 DS000020 -7 MAX 30 MIN 50 0 0 60 15 10,000 35 15 MIN 10,000 20 15 20 10 0 10 40 5 55 40 15 12 0 0 MAX 40 60 0 0 65 20 12 13 10 0 10 -6 -8 MAX 35 15 10,000 40 5 60 45 20 15 0 0 20 SYM tOE tOEH tPC tPRWC tRAC tRAD tRAH tRAL tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP tWRH tWRP UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2-108 MIN -7 MAX 15 12 25 75 12 10 30 60 14 0 40 13 80 15 10 10 10 MIN -8 MAX 20 12 30 85 60 30 125,000 45 70 12 35 10 35 70 125,000 14 50 0 50 15 90 15 12 10 10 MIN MAX 20 UNITS ns 15 ns 40 ns 90 ns 80 ns 15 40 ns 10 ns 40 ns 80 100,000 ns 20 60 ns 0 ns 60 ns 15 ns 105 ns 20 ns 15 ns 10 ns 10 ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RP t RASP V IH V IL RAS t CSH t PC t CRP t RCD t CAS, tCLCH t RSH t PC t CP t CP t CAS, tCLCH , , , , , ,, ,,, ,, ,,, ,,,, , , , , , , ,, ,, , t CAS, tCLCH ,,, V IH V IL CASL/CASH t RAL t AR t RAD tASR V IH V IL ADDR t RAH ROW tWRP V IH V IL WE t ASC t CAH COLUMN (A) tWRH t ASC t RCH COLUMN (N) t WCS t CAC t COH OPEN VALID DOUT t WHZ VALID DOUT t OE NOTE: ROW t WCH t AA t CAC V IH V IL OE t CAH t CPA t RAC DQ V IOH V IOL t ASC COLUMN (B) t AA NOTE 1 t ACH t CAH t RCS t CP t DS , ,,,, , t DH VALID DIN DON’T CARE UNDEFINED 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. TIMING PARAMETERS -6 SYM MIN tAA tACH 15 tAR 45 tASC 0 tASR 0 tCAC tCAH 10 tCAS 12 tCLCH 10 tCOH 3 tCP 10 tCPA tCRP 5 tCSH 50 tDH 10 tDS 0 tOE AS4LC1M16 REV. 3/97 DS000020 -7 MAX 30 MIN 15 50 0 0 15 10,000 35 MAX 40 20 60 0 0 10,000 20 15 20 10 5 10 40 5 55 12 0 15 MIN 20 12 13 10 3 10 -6 -8 MAX 35 10,000 40 5 60 15 0 20 20 SYM tPC tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ tWRH tWRP UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2-109 MIN 25 12 10 30 60 14 0 0 40 13 10 0 0 10 10 -7 MAX 60 30 125,000 45 13 MIN 30 -8 MAX 70 12 35 10 35 70 125,000 14 50 0 0 50 15 12 0 0 15 10 10 MIN 40 15 10 40 80 20 0 0 60 15 15 0 0 10 10 MAX UNITS ns 80 ns 40 ns ns ns 100,000 ns 60 ns ns ns ns ns ns ns 20 ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY READ CYCLE (with ?W/E-controlled disable) V IH V IL RAS tCSH , , , , , , , ,, ,,,, , , , , ,, , , , , , , , , , ,, , , , , ,, , , , ,, , , ,, tRCD tCRP tCAS, tCLCH tCP V IH V IL CASL/CASH tAR tRAD tASR V IH V IL ADDR tRAH tASC ROW tWRP WE V IH V IL tCAH tASC COLUMN tWRH COLUMN tRCS NOTE 1 tRCH tWPZ tRCS tAA tRAC tCAC tWHZ tCLZ DQ V OH V OL OPEN OPEN VALID DATA t OE OE tCLZ t OD V IH V IL DON’T CARE UNDEFINED NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. TIMING PARAMETERS -6 SYM MIN tAA tAR 45 tASC 0 tASR 0 tCAC tCAH 10 tCAS 12 tCLCH 10 tCLZ 0 tCP 10 tCRP 5 tCSH 50 AS4LC1M16 REV. 3/97 DS000020 -7 MAX 30 MIN 50 0 0 15 10,000 MIN MAX 40 60 0 0 20 12 13 10 0 10 5 55 -6 -8 MAX 35 10,000 20 15 20 10 0 10 5 60 10,000 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYM tOD tOE tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ tWRH tWRP 2-110 MIN 0 12 10 14 0 0 0 10 10 10 -7 MAX 15 15 60 30 45 13 MIN 0 12 10 14 0 0 0 12 10 10 -8 MAX 15 20 70 35 50 15 MIN 0 15 10 20 0 0 0 15 10 10 MAX 15 20 80 40 60 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY ?R?A/S-ONLY REFRESH CYCLE tRC tRAS tRP ,, ,,,,,,,, , , , , , , , , , , , , , ,, , , , ,, , RAS V IH V IL tRPC tCRP CASL/CASH V IH V IL ADDR V IH V IL tASR ROW V Q V OH OL WE tRAH ROW OPEN tWRP V IH V IL tWRP tWRH tWRH NOTE 1 CBR REFRESH CYCLE (Addresses and ?O/E = DON’T CARE) tRP RAS tRAS tRP tRAS V IH V IL tRPC ,,,,,,,,,,,,,,,,,, , , tCP CASL and CASH V IH V IL DQ V OH V OL tCSR NOTE: tCSR tCHR OPEN tWRP WE tRPC tCHR V IH V IL tWRH tWRP tWRH NOTE 2 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. tWRP and tWRH are for system design reference only. The ?W/E signal is actually a “don’t care” at ?R?A/S time during a CBR REFRESH. However, ?W/E should be held HIGH at ?R?A/S time during a CBR REFRESH to ensure compatibility with other DRAMs that require ?W/E HIGH at ?R?A/S time during a CBR REFRESH. TIMING PARAMETERS -6 SYM tASR tCHR tCP tCRP tCSR tRAH AS4LC1M16 REV. 3/97 DS000020 MIN 0 10 10 5 5 10 -7 MAX MIN 0 12 10 5 5 10 -6 SYM MIN MAX tRAS 60 10,000 tRC 105 tRP 40 tRPC 5 tWRH 10 tWRP 10 -8 MAX MIN 0 15 10 5 10 10 MAX UNITS ns ns ns ns ns ns 2-111 -7 MIN 70 125 50 5 10 10 MAX 10,000 -8 MIN 80 150 60 5 10 10 MAX 10,000 UNITS ns ns ns ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY CYCLE 32 HIDDEN REFRESH (?W/E = HIGH; ?O/E = LOW) tRC tRAS tRP tRAS V IH V IL , , , , , ,, ,,,,,, , ,,,,, , ,, , , , , , , , , , , , ,, ,, ,, ,, , ,, RAS tCRP tRSH tRCD tCHR V IH V IL CASL/CASH tAR tRAD tASR V IH V IL ADDR tRAH tASC ROW tRAL tCAH COLUMN tAA tRAC tCAC tOFF tCLZ DQx V IOH V IOL OPEN VALID DATA OPEN tOE V IH V IL OE tOD tORD DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYM tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD tOE AS4LC1M16 REV. 3/97 DS000020 MIN -7 MAX 30 45 0 0 MIN 50 0 0 15 10 10 0 5 0 15 15 MIN MAX 40 60 0 0 20 12 12 0 5 0 -6 -8 MAX 35 15 20 20 15 15 0 5 0 20 20 SYM tOFF tORD tRAC tRAD tRAH tRAL tRAS tRC tRCD tRP tRSH UNITS ns ns ns ns ns ns ns ns ns ns ns 2-112 MIN 3 0 12 10 30 60 105 14 40 13 -7 MAX 15 60 30 10,000 45 MIN 3 0 12 10 35 70 125 14 50 15 -8 MAX 15 70 35 MIN 3 0 15 10 40 10,000 80 145 50 20 60 15 MAX 15 80 40 10,000 60 UNITS ns ns ns ns ns ns ns ns ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. AS4LC1M16 883C 1 MEG x 16 DRAM PRELIMINARY ELECTRICAL TEST REQUIREMENTS SUBGROUPS (per Method 5005, Table I) MIL-STD-883 TEST REQUIREMENTS INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS (Method 5004) 2, 8A, 10 FINAL ELECTRICAL TEST PARAMETERS (Method 5004) 1*, 2, 3, 7*, 8, 9, 10, 11 GROUP A TEST REQUIREMENTS (Method 5005) 1, 2, 3, 4**, 7, 8, 9, 10, 11 GROUP C AND D END-POINT ELECTRICAL PARAMETERS (Method 5005) 1, 2, 3, 7, 8, 9, 10, 11 * PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance. AS4LC1M16 REV. 3/97 DS000020 2-113 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. AS4LC1M16 883C 1 MEG x 16 DRAM PRELIMINARY AS4LC1M16 REV. 3/97 DS000020 2-114 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.