ATMEL ATR2730-TLQY

Features
•
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•
•
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Supply Voltage: 8.5V
RF Frequency Range: 1400 MHz to 1550 MHz
IF Frequency Range: 150 MHz to 250 MHz
Enhanced IM3 Rejection
Overall Gain Control Range: 30 dB Typically
DSB Noise Figure: 10 dB
Gain-controlled Amplifier and L-band Mixer
Power-down Function for the Analog Part
On-chip Gain-control Circuitry
On-chip VCO, Typical Frequency 1261.568 MHz
Internal VCO Can Be Overdriven by an External LO
On-chip Frequency Synthesizer
– Fixed LO Divider Factor: 2464
– Nine Selectable Reference Divider Factors: 32, 33, 35, 36, 48, 49, 63, 64, 65
– A Reference Oscillator (Can Be Overdriven by an External Reference Signal)
– Tri-state Phase Detector with Programmable Charge Pump
– Programmable Deactivation of Tuning Output
– Lock-status Indication
– Test Interface
1. Description
L-band
Down-converter
for DAB
Receivers
ATR2730
Preliminary
The ATR2730 is a monolithically integrated L-band down-converter circuit fabricated
with Atmel®’s advanced UHF5S technology. This IC covers all functions of an L-band
down-converter in a DAB receiver. The device includes a gain-controlled amplifier, a
gain-controlled mixer, an output buffer, a gain control block, a power-save function for
the analog part, an L-band oscillator, and a complete frequency synthesizer unit. The
frequency synthesizer block consists of a reference oscillator/buffer, a reference
divider, an RF divider, a tri-state phase detector, a loop filter amplifier, a lock detector,
a programmable charge pump, a test interface, and a control interface.
4903C–DAB–03/07
Figure 1-1.
Block Diagram
IF
TH
17
AGC
VCC1 VCC3 VCC4 VCC2
19
3
20
28
6, 7, 8, 21, 22, 23, 24
18
Internal 5V supply voltage
for frequency synthesizer
∆U
Analog
part
RF
NRF
TANK
VREF
GND
9
26
Voltage
stabilizer
14
Bandgap
PLCK
Lock
detector
25
20 kΩ
5
12
RF counter
: 2464
VCO
CD
Tristate
phase
detector
4
Reference
counter
: Nref
Power save
(analog part)
Charge
pump
200/300
13
PD
Lock
detector
Test
interface
2
1
15
16
PSM
OSCB
OSCE
11
TI
Control
interface
10
CI
27
SI1
2
SI2
ATR2730 [Preliminary]
4903C–DAB–03/07
ATR2730 [Preliminary]
2. Pin Configuration
Figure 2-1.
Pinning SSO28
PSM
1
28 VCC4
SI2
2
27 SI1
VCC1
3
26 RF
VREF
4
25 NRF
TANK
5
24 GND
GND
6
23 GND
GND
7
22 GND
GND
8
21 GND
VCC2
9
20 VCC3
CI 10
19 IF
TI 11
18 AGC
CD 12
17 TH
PD 13
16 OSCE
PLCK 14
15 OSCB
3
4903C–DAB–03/07
Table 2-1.
4
Pin Description
Pin
Symbol
Function
1
PSM
2
SI2
3
VCC1
Supply voltage VCO
4
VREF
Reference pin of VCO
5
TANK
Tank pin of VCO
6, 7, 8, 21,
22, 23, 24
GND
Ground
9
VCC2
Supply voltage PLL
10
CI
Power save mode
Control input
Control input
11
TI
Test interface
12
CD
Active filter output
13
PD
Tri-state charge pump output
14
PLCK
Lock-indication output (open collector)
15
OSCB
Input of internal oscillator/buffer
16
OSCE
Output of internal oscillator/buffer
17
TH
Threshold voltage of comparator
18
AGC
Charge-pump output of comparator, AGC input for amplifier and mixer
19
IF
20
VCC3
Intermediate frequency output
25
NRF
26
RF
RF input
27
SI1
Control input
28
VCC4
Supply voltage
RF input (inverted)
Supply voltage
ATR2730 [Preliminary]
4903C–DAB–03/07
ATR2730 [Preliminary]
3. Functional Description
The ATR2730 is an L-band down-converter circuit covering a gain-controlled amplifier, a
gain-controlled mixer, an output buffer, a gain control circuitry, an L-band oscillator, and a frequency synthesizer block. Designed for applications in a DAB receiver, the circuit down-converts
incoming L-band signals in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in
the range of 190 MHz to 230 MHz, which can be handled by a subsequent DAB tuner. A block
diagram of this circuit is shown in Figure 1-1 on page 2.
3.1
Gain-controlled Amplifier
RF signals applied to the RF input pin are amplified by a gain-controlled amplifier. The complementary pin NRF is not internally blocked; it is recommended to block this pin carefully by an
external capacitor. The gain-control voltage is generated by internal gain-control circuitry. The
output signal of this amplifier is fed to a gain-controlled mixer.
3.2
Gain-controlled Mixer and Output Buffer
The purpose of this mixer is to down-convert the L-band signal in the frequency range of
1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz. Like the
amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF signal is buffered
and filtered by a one-pole low-pass filter at a 3 dB frequency of about 500 MHz, and then it is fed
to the single-ended output pin IF.
3.3
Gain-control Circuitry
The gain-control circuitry measures the signal power, compares it with a certain power level and
generates control voltages for the gain-controlled amplifier and mixer. An equivalent circuit of
this functional block is shown in Figure 10-1 on page 14.
In order to meet this functionality, the output signal of the buffer amplifier is weakly band-pass filtered (transition range of about 60 MHz to 550 MHz), rectified, low-pass filtered, and fed to a
comparator whose threshold can be defined by an external resistor, RTH, at pin TH. By varying
the value of this resistor, a power threshold of about –33 dBm to –20 dBm can be selected. In
order to achieve a good intermodulation ratio, it is recommended to keep the power threshold
below –25 dBm. An appropriate application is shown in Figure 8-1 on page 12. Depending on
the selection made by the comparator, a charge pump charges or discharges a capacitor which
is applied to the AGC pin. By varying this capacitor, different time constants of the AGC loop can
be realized. The voltage arising at the AGC pin is used to control the gain setting of the
gain-controlled amplifier and mixer. The voltage at pin AGC is in the range of 5.75V for maximum gain and 0.3V for minimum gain. This voltage can be use to control a dual-gate GaAs-FET
in front of the ATR2730 to achieve an extended AGC range. By applying an external voltage to
the AGC pin, the internal AGC loop can be overdriven.
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4903C–DAB–03/07
3.4
Voltage-controlled Oscillator
A voltage-controlled oscillator supplies an LO signal to the mixer. An equivalent circuit of this
oscillator is shown in Figure 10-2 on page 14. In the application circuits (Figure 10-3 on page 15
and Figure 11-1 on page 16), a ceramic coaxial resonator is applied to the oscillator's TANK and
VREF pins. It should be noted that Vref has to be blocked carefully. Figure 11-1 shows a different
application where the oscillator is overdriven by an external oscillator. In either case, a DC path
at a low impedance must be established between the TANK and VREF pins. The output signal
of the oscillator is fed to the LO divider block of the frequency synthesizer unit which locks the
VCO’s frequency on the frequency of a reference oscillator. Figure 9-1 on page 13 shows the
typical phase-noise performance of the oscillator in locked state.
3.5
Overall Properties of the Signal Path
The overall gain of this circuit amounts to 24 dB, the gain-control range is about 30 dB. With a
new AGC concept in the amplifier and mixer, the ATR2730 reaches better intermodulation distances (DIM3) at higher IF-output power levels.
3.6
Power Save Mode
For VPSM > 2V (pin 1) the power consumption in the analog part (gain-controlled amplifier and
mixer and gain-controlled circuitry) is reduced by 80%. The VCO and the PLL is not influenced
by the power-down mode.
3.7
Frequency Synthesizer
The frequency synthesizer block consists of a reference oscillator, a reference divider, an LO
divider in order to divide the frequency of the internal oscillator, a tri-state phase detector, a lock
detector, a programmable charge pump, a loop filter amplifier, a control interface, and a test
interface. The control interface is accessed by three control pins, CI, SI1 and SI2. The test interface provides test signals which represent output signals of the reference and the LO divider.
The purpose of this unit is to lock the frequency fVCO of the internal VCO on the frequency fref of
the reference signal applied to the input pin OSCB phase-locked loop according to the following
equation:
fVCO = SF × fref / SFref
where: SF = 2464,
SFref is the scaling factor of the reference divider according to Table 3-1
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ATR2730 [Preliminary]
4903C–DAB–03/07
ATR2730 [Preliminary]
Table 3-1.
3.8
Scaling Factors of the Reference Frequency
Voltage at Pin SI1
Voltage at Pin SI2
SFref
Reference Oscillator
Frequency
GND
OPEN
36
18.432 MHz
GND
VCC
33
–
GND
GND
48
24.576 MHz
OPEN
OPEN
65
–
OPEN
VCC
63
–
OPEN
GND
64
32.768 MHz
VCC
OPEN
35
17.920 MHZ
VCC
VCC
32
16.384 MHz
VCC
GND
49
–
Reference Oscillator
An on-chip crystal oscillator generates the reference signal which is fed to the reference divider.
By connecting a quartz crystal to pins OSCE and OSCB according to Figure 11-2 on page 16,
this oscillator generates a highly stable reference signal. The ATR2731 (Atmel’s one-chip
front-end IC) offers the reference signal at pin FREF. This reference signal (LC filtered to suppress harmonics) can be used to overdrive the oscillator. In this application (see Figure 11-3 on
page 16) the reference signal has to be applied to the pin OSCB and the pin OSCE must be left
open.
3.9
Reference Divider
Nine different scaling factors of the reference divider can be selected by different voltage settings at the input pins SI1 and SI2: 32, 33(1), 35, 36, 48, 49(1), 63(1), 64, 65(1). The reference
divider factors result in reference oscillator frequencies shown in Table 3-1.
Note:
3.10
1. These scaling factors result in an output frequency of the reference divider of 512 kHz. If harmonics of the Bd. 3 VCO fall in the L-band reception band, these spurious signals can
influence the AGC of ATR2730, which could be a problem for small incoming signals. In this
case it is possible to switch the reference divider from nref to nref + 1.
LO Divider
The LO divider is operated at the fixed division ratio 2464. Assuming the settings described in
the section “Reference Divider” , the oscillator's frequency is controlled to be 1261.568 MHz in
the locked state, and the output frequency of the RF divider is 512 kHz.
3.11
Phase Comparator, Charge Pump and Loop Filter
The tri-state phase detector causes the charge pump to source or sink current at the output pin
PD depending on the phase relation of its input signals, which are provided by the reference and
the RF divider respectively. Using the control pin CI, two different values of this current can be
selected, and the charge-pump current can be switched off.
The input of the high-gain amplifier (output pin CD), which is implemented in order to construct a
loop filter as shown in the application circuit, can be switched to GND by means of the control
pin CI (see Table 3-2 on page 8). In the application circuit, the loop filter is completed by connecting the pins PD and CD by an appropriate RC network.
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4903C–DAB–03/07
3.12
Lock Detector
An internal lock detector checks if the phase difference of the input signals of the phase detector
is smaller than approximately 250 ns in seven subsequent comparisons. If a phase lock is
detected, the open collector output pin PLCK is set to HIGH. It should be noted that the output
current of this pin must be limited by external circuitry as it is not limited internally. If the voltage
at the control pin CI is chosen to be half the supply voltage, or if this control pin is left open, the
lock-detector function is deactivated and the logical value of the PLCK output is undefined.
3.13
Test Interface
If the input control pin CI is left open (high impedance state), a test signal, which monitors the
output frequency of the reference divider, appears at the output pin TI.
Analogous to the reference divider, a test signal monitoring the output frequency of the RF
divider appears at the test interface output pin TI, if the input control pin CI is connected to
VCC/2.
Table 3-2.
8
Control Interface (CI) Settings
CI
PD
PLCK
TI
GND
200 µA
Ok
–
Vs
300 µA
Ok
–
VCC/2
0 µA
Undefined
RF divider
Open
Connected to GND
Undefined
Reference divider
ATR2730 [Preliminary]
4903C–DAB–03/07
ATR2730 [Preliminary]
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Pins
Symbol
Value
Unit
Supply voltage
3, 9, 20 and 28
VCC
–0.3 to +9.5
V
RF input voltage
25 and 26
VRF
750
mVpp
Voltage at pin AGC
18
VAGC
0.5 to 6
V
Voltage at pin TH
17
VTH
–0.3 to +4.0
V
Input voltage at pin TANK
(internal oscillator overdriven)
5
VTANK
1
Vpp
Current at IF output
19
IIF
4.0
mA
Reference input voltage (diff.)
15
Control input voltage
1, 2, 10 and 27
OSCB
1
Vpp
CI, SI1, SI2, PD
–0.3 to +9.5
V
PLCK output current
14
IPLCK
0.5
mA
PLCK output voltage
14
VPLCK
–0.3 to +5.5
V
Junction temperature
Tj
125
°C
Storage temperature
Tstg
–40 to +125
°C
Symbol
Value
Unit
VCC
8 to 9.35
V
Tamb
–40 to +85
°C
Symbol
Value
Unit
RthJA
50
K/W
5. Operating Range
Parameters
Pins
Supply voltage
3, 9, 20 and 28
Ambient Temperature
6. Thermal Resistance
Parameters
Junction ambient SSO28 (mod.)
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4903C–DAB–03/07
7. Electrical Characteristics
Operating conditions: VCC = 8.5V, Tamb = 25° C unless otherwise specified. (See application circuit Figure 10-3 on page 15.)
No. Parameters
Test Conditions
1.1
Supply current (max. gain)
pRF = –60 dBm
VPSM < 0.5V
1.2
Supply current (min. gain)
1.3
Supply current
(power-save mode)
2
Pin
Symbol
Typ.
Max.
Unit
Type*
IS,MAX
40
48
mA
A
pRF = –10 dBm
VPSM < 0.5V
IS,MIN
41
50
mA
B
pRF = –10 dBm
VPSM > 2V
IS,PD
20
24
mA
A
24
dB
A
–8
dB
B
26 →19
Amplifier Mixer Pin 26
2.1
Maximum conversion gain
pRF = –60 dBm
gc,max
2.2
Minimum conversion gain
pRF = –15 dBm
gc,min
2.3
AGC range
2.4
Third-order 2-tone
intermodulation ratio
pRF1 + pRF2 = –10 dBm
pRF1 + pRF2 = –15 dBm
2.5
DSB noise figure
(50Ω system)
Maximum gain
Minimum gain
3
RF Input
3.1
Frequency range
3.2
Maximum input power
3.3
Input impedance
4
Min.
20
∆gc
28
32
dB
A
dim3
30
35
35
40
dB
dB
B
A
10
30
dB
dB
D
MHz
C
NF
26
fin,RF
dim3 ≥ 20 dB
IF Output
1400
1550
pin,max,RF
–6
dBm
C
Zin,RF
200 || 1
Ω || pF
D
MHz
C
Ω
D
19
150
250
4.1
Frequency range
fout,IF
4.2
Output impedance
Zout,IF
50
4.3
Voltage standing wave ratio
VSWRIF
2.0
100
5
5.1
5.2
Gain Control
Threshold adjustment
Charge pump current
kΩ
D
125
µA
A
–100
–75
µA
A
0.1
0.6
V
A
V
A
External resistor
17
RTH
pRF = –10 dBm
VAGC = 3.5V
18
ICP,P
75
100
ICP,N
–125
pRF = –60 dBm
VAGC = 3.5V
5.3
Minimum gain control
voltage
pRF = –10 dBm
18
VAGCmin
5.4
Maximum gain control
voltage
pRF = –60 dBm
18
VAGCmax
5.5
5.75
fLO
1000
1261.568
6
VCO
5
6.1
Frequency
6.2
Phase noise
1 kHz distance
6.3
Minimum input power
6.4
Maximum input power
VCO overdriven, see
“Application Circuit” (Figure
10-3 on page 15)
7
7.1
D
1500
MHz
L1kHz
–75
dBc/Hz
C
pLO,MIN
–11
dBm
C
pLO,MAX
–5
dBm
C
SF
2464
Frequency Synthesizer
RF divide factor
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10
ATR2730 [Preliminary]
4903C–DAB–03/07
ATR2730 [Preliminary]
7. Electrical Characteristics (Continued)
Operating conditions: VCC = 8.5V, Tamb = 25° C unless otherwise specified. (See application circuit Figure 10-3 on page 15.)
No. Parameters
Test Conditions
7.2
Reference divide factor
SI1 = GND, SI2 = GND
SI1 = GND, SI2 = VCC
SI1 = GND, SI2 = open
SI1 = VCC, SI2 = GND
SI1 = VCC, SI2 = VCC
SI1 = VCC, SI2 = open
SI1 = open, SI2 = GND
SI1 = open, SI2 = VCC
SI1 = open, SI2 = open
Pin
Symbol
7.3
Input frequency range
Input sensitivity
15
Vrefs
fref
7.5
Maximum input signal
15
Vrefmax
7.6
Input impedance
Zref
8
Phase Detector
Single-ended
8.1
Charge-pump current
13
Pin CI connected to VCC
Pin CI connected to VCC/2
Output voltage PD
8.3
Internal reference frequency
8.4
Typical tuning voltage range
12
Lock Indication PLCK
14
13
Leakage current
VPLCK = 5.5V
9.2
Saturation voltage
IPLCK = 0.25 mA
10
Control Inputs SI
C
mVrms
C
300
mVrms
C
2.7k || 2.5
kΩ || pF
D
IPD1
240
300
360
µA
A
100
nA
A
0.3
V
A
kHz
B
5
V
C
IPLCK
10
µA
A
VPLCK,sat
0.5
V
A
0.1
VCC
A
VPD
Vtune
512
0.3
2 and 27
VM
10.3
Pin connected to VCC
12
MHz
30
A
Pin open
0
Open
A
VH
0.9
1
VCC
A
Pin connected to GND
VL
0
0.1
VCC
A
Pin connected to VCC/2
VM
VCC
A
Control Input CI
11.4
50
µA
10.2 Input voltage
11.3
A
240
VL
Input voltage
Type*
200
Pin connected to GND
11.2
Unit
160
10.1
11.1
Max.
IPD2
fPD
9.1
11
5
IPD1,tri
8.2
9
Pin CI open
Typ.
48
33
36
49
32
35
64
63
65
SFref
7.4
Pin CI connected to GND
Min.
10
Pin open
Open
Vopen
VH
Pin connected to VCC
Test Interface TI
0.5
0.9
A
1
VCC
A
11
Pin CI open
ftest,ref
512
kHz
B
12.2 LO test frequency
Pin CI = VCC/2
ftest,LO
512
kHz
B
12.3 Voltage swing
Rload ≥ 1 MΩ, Cload ≤ 15 pF,
Pin CI open or VCC/2
Vsw
400
mVpp
C
V
A
V
A
12.1 Reference test frequency
13
Power-save Mode PSM
1
13.1
PSM not active
VPSM
13.2
PSM active
VPSM
0.6
2.0
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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8. Gain Control Characteristics
Operating conditions: VCC = 8.5V, Tamb = 27° C, fRF = 1490 MHz, FLO = 1261.568 MHz
Figure 8-1.
IF Output Power (Pin 19)
-10
-15
pIF (dBm)
-20
-25
Rth = 100 kΩ
-30
-35
-40
-60
-50
-40
-30
-20
-10
0
-10
0
pRF (dBm)
Figure 8-2.
Gain Control Voltage (Pin 11)
6
5
Rth = 100 kΩ
VAGC (V)
4
3
2
1
0
-60
-50
-40
-30
-20
pRF (dBm)
12
ATR2730 [Preliminary]
4903C–DAB–03/07
ATR2730 [Preliminary]
9. Phase-noise Performance
Measurement conditions:
Values acquired at pin 19 with HP 70000 spectrum analyzer. RF input (pin 26) is blocked
with 100 pF to GND.
A low phase-noise signal generator (Marconi® 2042) was taken as PLL reference.
Figure 9-1.
Phase-noise Performance Operating Conditions: fREF = 17.92 MHz, –10 dB,
IPD = 200 µA
RL -29.29 dBm
ATTEN 10 dB
10.00 dB/DIV
< -75 dBc/Hz
Center 1.261 568 GHz
RB 100 Hz VB 100 Hz
Span 50.00 kHz
ST 15.00 sec
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4903C–DAB–03/07
10. Equivalent Circuits
Figure 10-1. AGC Control Circuit
Gain
controlled
mixer
Gain
controlled
amplifier
VRef1
550 MHz
IF
output
60 MHz
VRef2
AGC
TH
Rth
Figure 10-2. VCO Circuit
VCC
VTune
47 kΩ
BBY51
1.8 pF
15 pF
TANK
Resonator
1 pF
VREF
100 pF
Resonator: Ceramic coaxial resonator
Murata® 3 × 3 mm, 1.6 GHz
DRR030 KE1R600TC
14
ATR2730 [Preliminary]
4903C–DAB–03/07
ATR2730 [Preliminary]
Figure 10-3. Application Circuit
VAGC
3.3 µF
+
8.5V
RF
8.5V
IF
1 nF
100 pF
100 kΩ
Quartz
crystal
100 pF
100 pF
1 nF
100
pF
RF
NRF
GND
GND
21
20
19
18
17
16
15
68 pF
OSCB
SI1
22
OSCE
23
33 pF
TH
24
IF
25
VCC3
26
GND
27
GND
28
VCC4
10 nF
AGC
100 pF
10 nF
18 pF
SI2
VCC1
VREF
TANK
GND
GND
GND
VCC2
CI
TI
CD
PD
PLCK
Power save
PSM
ATR2730
1
2
3
4
5
6
7
8
9
10
11
12
13
14
5V
100 pF
1 pF
10 nF
Lock
indication
10 nF
56 kΩ
100 pF 1)
100 pF
100 pF
8.5V
47 kΩ
1 nF
15 pF
1 nF
8.5V
1.8 pF
D1
1 kΩ
1 kΩ
3.3 nF 1)
3.3 nF 1)
1) optional
Example: reference divider factor = 35, fREF = 17.92 MHz, charge-pump current = 200 µA
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11. Application Circuit for External LO Signal
With an external LO signal it is possible to overdrive the VCO. In this case, the internal VCO acts
as an LO buffer.
Figure 11-1. Application Circuit for External LO Signal
External LO signal
(50Ω signal gen.)
PLO = -10 dBM
TANK
100 pF
470 nH
50Ω
VREF
1 nF
Figure 11-2. Reference Oscillator Operation
68 pF
OSCB
Reference divider
33 pF
OSCE
Quartz
crystal
18 pF
Figure 11-3. Reference Oscillator Overdriven
OSCB
Reference
signal
L1
Reference divider
C1
OSCE
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ATR2730 [Preliminary]
4903C–DAB–03/07
ATR2730 [Preliminary]
12. Ordering Information
Extended Type Number
Package
Remarks
ATR2730-TLSY
SSO28
Tube, Pb-free
ATR2730-TLPY
SSO28
Taped and reeled according to IEC 286-3, 180 µm size,
Pb-free
ATR2730-TLQY
SSO28
Taped and reeled according to IEC 286-3, 330 µm size,
Pb-free
13. Package Information
5.4±0.2
0.65±0.05
1.3±0.05
0.05+0.1
0.25±0.05
6.45±0.15
0.15±0.05
4.4±0.1
9.35-0.25
8.45±0.05
28
15
Package: SSO28
Dimensions in mm
technical drawings
according to DIN
specifications
1
14
Drawing-No.: 6.543-5056.03-4
Issue: 1; 10.03.04
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4903C-DAB-03/07
• Put datasheet in a new template
• Section 12 “Ordering Information” on page 17 changed
17
4903C–DAB–03/07
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