ATV5000/L Features • • • • • • • • • Advanced Programmable Logic Device - High Gate Utilization Flexible Interconnect Architecture - Universal Routing Flexible Logic Cells - 128 Flip-Flops and 52 Latches Multiple Flip-Flop Types - Synchronous or Asynchronous Registers High Speed - 50 MHz Operation Complete Third Party Software Support No Placement, Routing or Layout Software Required Proven and Reliable High Speed CMOS EPROM Process 2000 V ESD Protection 200 mA Latchup Immunity Reprogrammable - Tested 100% for Programmability Commercial, Industrial and Military Temperature Grades High Density UV Erasable Programmable Logic Device Block Diagram 52 INPUT LATCHES 8 INPUT PINS UNIVERSAL AND REGIONAL INTERCONNECT 52 I/O PINS 52 LOGIC CELLS (104 FLIP-FLOPS) 24 BURIED CELLS (24 FLIP-FLOPS) Description The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regular architecture translates into increased utilization and high performance. The ATV5000 has one programmable combinatorial logic array. This guarantees easy interconnection of and uniform performance from all nodes. "Sum terms", which are easy to use groupings of AND-OR gates, provide combinatorial logic blocks. Sum terms can be wireOR’d together to integrate larger logic blocks. To expand the levels of logic, buried sum terms feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term. Each I/O pin has an individually enabled input latch. All 128 registers are configurable as D- or T-types without using extra logic gates. Individual sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A direct "clock from pin" option guarantees synchronization and fast clock to output performance. Standard, off-the-shelf third-party software tools and programmers support the ATV5000. This minimizes start-up investment and improves product support. JLCC Chip Carrier Pin Configuration Pin Name Function IN Logic and Clock Inputs Pins 2,32,36,66 Input/Register Clocks 1-4 Input/Latch Clocks 1-4 I/O Bidirectional Buffers VCC +5 V Supply IN I/Os IN I/Os 1 I/Os I/Os VCC GND I/Os Pins 1,34,35,68 GND VCC 52 18 I/Os VCC GND I/Os I/Os 35 I/Os IN GND I/Os IN VCC 0065B 1-193 Absolute Maximum Ratings* Temperature Under Bias.................-55oC to +125oC Storage Temperature......................-65oC to +150oC Voltage on Any Pin with Respect to Ground..........................-2.0 V to +7.0 V1 Voltage on Input Pins with Respect to Ground During Programming.....................-2.0 V to +14.0 V1 Programming Voltage with Respect to Ground........................-2.0 V to +14.0 V1 *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V for pulses of less than 20 ns. Integrated UV Erase Dose .............. 7258 W• sec/cm2 Functional Logic Diagram Description There are 52 identical input/ouput logic cells and 24 identical buried logic cells in the ATV5000. Each I/O cell has two flipflops, up to three sum terms, individual clock, reset, and preset terms per flip-flop, and one output enable term. Independent of output configuration, all flip-flops are always usable, and have at least four product term inputs each. Each I/O pin (52 total) signal or its latched version drives the logic array. There is one latch clock per quadrant. The ATV5000 has four identical quadrants (see Figure 2). The universal bus routes true and false signals from each of the 52 I/O pins to all four quadrants. Regional buses route each quadrant’s flip-flop Q and Q locally. The eight input-only pins are available in all four regional buses. Each logic cell has a number of "regional" and "universal" product terms (see Figure 1). The I/O logic cells contain three sum terms, two flip-flops, and an I/O buffer. The buried logic cells each contain one flip-flop. In addition, in each buried logic cell the sum term can drive the regional bus. This allows for logic expansion. Serial register preload and observability simplify testing. All registers automatically clear at power up. Quadrant Functional Logic Diagram ATV5000 UNIVERSAL INPUTS UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS INPUT/OUTPUT LOGIC CELLS (13 TOTAL PERQUADRANT) REGIONAL INPUTS REGISTERCLOCKS INPUT PINS REGISTERCLOCKS UNIVERSAL PRODUCT TERMS BURIED LOGIC CELLS (6 TOTAL PERQUADRANT) REGIONAL PRODUCT TERMS REGIONAL INPUTS UNIVERSAL BUS TO ALL QUADRANTS REGIONAL BUS Figure 1 D.C. and A.C. Operating Range Operating Temperature (Case) ATV5000-25 ATV5000/L-30 Commercial Industrial Military o o 1-194 0 C - 70 C -55 C - 125oC 5 V ± 5% 5 V ± 10% 5 V ± 10% ATV5000/L o o ATV5000/L-35 0 C - 70 C VCC Power Supply o I/O PINS ATV5000/L ATV5000 Block Diagram REGISTER CLOCK PIN 2 LATCH CLOCK PIN 1 13 I/O PINS 4-15,17 REGISTER CLOCK PIN 32 QUADRANT 1 REGIONAL BUS 13 I/O CELLS 6 BURIED LOGIC CELLS 6 BURIED LOGIC CELLS 16 UNIVERSAL BUS 13 I/O PINS 52,53,55-65 REGISTER CLOCK PIN 36 LATCH CLOCK PIN 35 13 I/O CELLS 6 BURIED LOGIC CELLS 6 BURIED LOGIC CELLS 16 REGIONAL BUS LATCH CLOCK PIN 68 16 13 I/O CELLS QUADRANT 2 REGISTER CLOCK PIN 66 QUADRANT 4 13 I/O CELLS LATCH CLOCK PIN 34 13 I/O PINS 18,19,21-31 REGIONAL BUS 16 REGIONAL BUS INPUT PINS 1,2,32,34,35, 36,66,68 13 I/O PINS 38-49,51 QUADRANT 3 Figure 2 Quadrant Logic Diagram and Description The ATV5000 has: four identical quadrants, 52 identical input/ output logic cells, and 24 identical buried logic cells. The universal bus routes true and false signals from each of the 52 I/O pins to all four quadrants. Regional buses route each quadrant’s flip-flop Q and Q locally. The eight input-only pins are available in every regional bus. Each logic cell has a number of "regional" and "universal" product terms (see Figure 3). The I/O logic cells (Figures 7, 8, 9) contain three sum terms, two flip-flops, and an I/O buffer. Sum term B has five product terms - two universal and three regional. Sum terms A and C each have four product terms - one universal and three regional. Flip-flop Q1 has global asynchronous preset, reset, and clock product terms. Flip-flop Q2 has universal asynchronous reset and clock terms and a regional asynchronous preset term. There is one universal product term for the I/O pin output enable. The buried logic cells (Figure 4) each contain one flip-flop. The sum term has one universal product term and four regional product terms for a total of five. The flip-flop has universal asynchronous preset, reset, and clock terms. In addition, in each buried logic cell the sum term can be fed back into the regional bus instead of the flip-flop. This allows for logic expansion. Regional product terms have as inputs all quadrant flip-flop outputs (or buried flip-flop inputs) and the eight dedicated input pins. Universal product terms have the same inputs plus the 52 I/O pins and their complements. Quadrant Clock Pin Assignments Quadrant Number Register Clock Pin Latch Clock Pin 1 2 1 2 32 34 3 36 35 4 66 68 Quadrant Structure UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS UNIVERSAL BUS INPUTS REGIONAL BUS INPUTS IN/LIN Q1 Q2 INPUT/ OUTPUT LOGIC CELLS (13 TOTAL) REGISTER CLOCK LATCH CLOCK 13 I/O PINS OE Q1/D1 REGISTER CLOCK BURIED LOGIC CELLS (6 TOTAL) UNIVERSAL BUS TO ALL QUADRANTS 16 REGIONAL BUS ALL 8 INPUT ONLY PINS Figure 3 1-195 Logic Cell Options The ATV5000 logic cells contain most of the chip’s logic options. The standard logic cell contains two flip-flops, three sum terms and three array inputs. The three sum terms can be combined to provide sum term options of four, five, nine, or 13 product terms. A combinatorial signal or the output of Q1 can be sent to the I/O cell. The ATV5000 retains the ATV2500’s ability to bury both registers in the I/O cell and still output a combinatorial signal (see Figure 8). A new feature, unique to the ATV5000, is the ability to output Q1 and feedback the combinatorial term directly (see Figure 7). This high speed logic expansion term increases the devices flexibility and gate utilization. Logic Cell with Buried Sum Term and Register to I/O Cell U U R R R R Q1 Q2 R U R B U R U AP1 R Buried Logic Cells R Each quadrant has six buried logic cells (see Figure 4). Each cell contains one sum term with five product terms, a flip-flop, and individual preset, clear, and clock terms. A configuration bit selects either the Q output or the D input for feedback into the regional bus. Buried Logic Cells A D1/T1 R TO I/O CELL U U CK1 U AR1 R AP2 Q1 CLOCK OPTION U R R R C SELECT D2/T2 Q2 R AP1 U R R R D1/T1 R U CK2 U AR2 CLOCK OPTION Q1 Figure 7 R U U CK1 U AR1 CLOCK OPTION Flip-Flop Clock Options Figure 4 Each register may be connected to its regional clock to provide fast clock-to-output timing (see Figure 5). In this "synchronous" mode, the clock is one of four input pins, a unique clock pin for each chip quadrant. One product term defines each flip-flop’s clock in the "asynchronous" mode. In the "synchronous" mode, the regional clock is ANDed with the product term. This provides the fast timing of a synchronous clock with the local control of the product term. Clock Option RCKn TO LOGIC CELL CLOCK PRODUCT TERM SELECT Figure 5 I/O Pin Latches I/O Pin Logic Q TO LOGIC CELL FROM LOGIC CELL U SELECT C LCKn 0/1 I/O OE Figure 6 1-196 Each I/O pin of the ATV5000 has an input latch which can be individually enabled or disabled (see Figure 6). Each chip quadrant has a unique latch clock. When the latch is inactive, pin input flows directly into the array. When activated, the latch is flow-through when the clock signal is low, and data is captured on the clock’s rising edge. D ATV5000/L Flip-Flop Types Each flip-flop in the ATV5000 may be configured as either a Tor D-type flip-flop. A T-type flip-flop can also easily be configured into a JK or SR flip-flop. ATV5000/L Logic Cell, Two Buried Registers, Combinatorial to I/O Cell U U R R R R Q1 Logic Cell with Combinable Sum Terms, Register to I/O Cell FROM I/O CELL Q2 U U U R R R R AP1 Q2 U R AP1 R R A D1/T1 U U CK1 U AR1 CLOCK OPTION U CK1 U AR1 R R U U R TO I/O CELL R TO I/O CELL CLOCK OPTION R B U Q1 A R U D1/T1 R Q1 R R FROM I/O CELL Q1 B TO D1/T1 U R AP2 R U AP2 U R C D2/T2 R Q2 D2/T2 C R Q2 R R R U CK2 U AR2 CLOCK OPTION U CK2 U AR2 Figure 8 CLOCK OPTION Figure 9 D.C. Characteristics Symbol Parameter Condition Min Typ Max Units ILI Input Load Current VIN = -0.1 V to VCC+1 V 10 µA ILO Output Leakage Current VOUT = -0.1 V to VCC+0.1 V 10 µA ICC Power Supply Current ATV5000 VCC = MAX, VIN = GND or VCC Outputs Open Com. 200 350 mA Ind.,Mil. 200 400 mA Power Supply Current ATV5000L VCC = MAX, VIN = GND or VCC Outputs Open Com. 32 40 mA Ind.,Mil. 32 50 mA ICC Clocked Power Supply Current, ATV5000L Only f = 1 MHz, VCC = MAX Outputs Open IOS (1) Output Short Circuit Current VOUT = 0.5 V VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ICC2 Com. 30 (2) mA Ind.,Mil. 30 (2) mA -120 mA -0.6 0.8 V 2.0 VCC+0.75 V 0.5 V VIN = VIH or VIL, IOL = 8 mA Com,Ind; 6 mA Mil. IOH = -100 µA VCC-0.3 V IOH = -4.0 mA 2.4 V Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 seconds. 2. See ICC vs. Frequency curve. 1-197 A.C. Waveforms Input Pin Clock (1) (1) A.C. Waveforms Product Term Clock INPUTS AND I/O PINS INPUTS AND I/O PINS tSIS tSIA tHS REGISTER CLOCK TERM tWS REGISTER CLOCK PIN tWS tPS tARS ASYNCHRONOUS RESET/PRESET tCOS REGISTERED OUTPUTS tSFS tARA tAW tCOA tAP OUTPUT VALID VALID tAP REGISTERED OUTPUTS OUTPUT VALID OUTPUT VALID tSFA tAPF tCFS INTERNAL FEEDBACKS tWA tPA ASYNCHRONOUS RESET/PRESET tAW tHA tWA tAPF tCFA INTERNAL FEEDBACKS VALID OUTPUT VALID VALID VALID Notes: 1. Timing measurement reference is 1.5 V. Input AC driving levels are 0.0 V and 3.0 V, unless otherwise specified. Register A.C. Characteristics, Input Pin Clock ATV5000-25 Symbol Parameter Min tCOS Clock to Output tCFS Clock to Feedback Max ATV5000/L-30 Min 15 0 (1) 9 Max ATV5000/L-35 Min 20 0 12 0 Max Units 25 ns 15 ns tSIS Input Setup Time 16 17 20 ns tSFS Feedback Setup Time(1) 11 13 15 ns tHS Hold Time 0 0 0 ns tWS Clock Width 10 12 15 ns tPS Clock Period 20 25 30 ns FMAXS Maximum Frequency (1/tPS) tARS Asynchronous Reset/Preset Recovery Time Note: 50 20 40 25 33 30 MHz ns 1. Add 3 ns for Universal Product Terms. Register A.C. Characteristics, Product Term Clock ATV5000-25 Symbol Parameter tCOA Clock to Output tCFA Clock to Feedback Min Min 25 7 (1) Input Setup Time tSIA Max ATV5000/L-30 (1) 20 Max ATV5000/L-35 Min 30 10 25 12 Max Units 35 ns 27 ns 10 12 15 ns tSFA Feedback Setup Time 5 8 13 ns tHA Hold Time 8 10 12 ns tWA Clock Width 12 15 15 ns tPA Clock Period 25 33 40 ns FMAXA Maximum Frequency (1/tPA) tARA Asynchronous Reset/Preset Recovery Time Note: 1-198 1. Add 3 ns for Universal Product Terms. ATV5000/L 40 15 30 20 25 25 MHz ns ATV5000/L A.C. Waveforms (1) INPUTS AND I/O PINS tS tH INPUT LATCH CLOCK tW tW tP tER1 tEA1 OUTPUT VALID OUTPUT VALID COMBINATORIAL OUTPUTS HIGH Z OUTPUT VALID HIGH Z OUTPUT VALID tPD1 REGISTERED tPD3 INTERNAL FEEDBACKS tPD4 tPD2 tER2 VALID tEA2 VALID Notes: 1. Timing measurement reference is 1.5 V. Input AC driving levels are 0.0 V and 3.0 V, unless otherwise specified. A.C. Characteristics ATV5000-25 Symbol Parameter Min (1) Input to Non-Registered Output tPD1 (1) ATV5000/L-30 Max Min Max ATV5000/L-35 Min Max Units 25 30 35 ns tPD2 Feedback to Non-Registered Output 20 25 30 ns tPD3 (1) Input to Non-Registered Feedback 20 25 30 ns tPD4 Feedback to Non-Registered Feedback(1) 15 18 22 ns tEA1 Input to Output Enable 30 35 40 ns tER1 Input to Output Disable 30 35 40 ns tEA2 Feedback to Output Enable 25 30 35 ns tER2 Feedback to Output Disable 25 30 35 ns tS Input Latch Setup Time 5 6 7 ns tH Input Latch Hold Time 5 5 5 ns tW Clock Width 10 12 12 ns tP Clock Period 20 25 30 ns FMAX Maximum Frequency (1/tP) tAW Asynchronous Reset/Preset Width tAP Asynchronous Reset/ Preset to Registered Output 30 35 40 ns tAPF Asynchronous Reset/ Preset to Registered Feedback 25 30 35 ns Note: 50 40 15 20 33 20 MHz ns 1. Add 3 ns for Universal Product Terms. Input Test Waveforms and Measurement Levels Output Test Load 5.0V 3.0V AC DRIVING LEVELS 1.5V 0.0V tR, tF < 5 ns (10% to 90%) AC MEASUREMENT LEVEL R1= 450 (580 MIL.) R2= 250 (280 MIL.) OUTPUT PIN CL= 35pF 1-199 Preload and Observability of Registers clocked out of the device on Pin 65 in FIFO fashion. If observability only is required, data out should be connected back to data in. If preload only is required, OE (pin 66) can be held high and data out (pin 65) will remain high impedance. Any user contemplating the use of register preload/obervability is encouraged to contact Atmel’s PLD applications department. Note: All register clock terms or pins must be low prior to entering the preload/observe state, and low prior to leaving the preload/observe state. Pin 1 must be low prior to entering the preload/observe state. The ATV5000’s registers include circuity to load and unload them serially. This feature simplifies testing. Any state can be forced into the registers to control test sequencing, and all registers may be observed, independent of being buried. A VIH level on the Data In pin will force the appropriate register high; a VIL will force it low, independent of the polarity or other configuration bit settings. The preload/observe state is entered by placing an 11-V to 14-V signal on pin 68 on the JLCC. When the clock (pin 1) is pulsed high, data (pin 2) is clocked serially through all registers in the device, as in the following table. All register contents are also tD tD tPR VH PRELOAD tSP CLOCK tWPP tHP Clock #1 Clock #2 Pin 65 New Q1 DATA IN tWPP Clock #128 tDMIN = 100 ns tSPMIN = 50 ns tHPMIN = 50 ns tWPPMIN = 100 ns tPRMIN = 1000 ns tERPMAX = 100 ns tEAPMAX = 100 ns tCOPMAX = 100 ns Pin 65 New Q2 tERP tCOP OE tEAP Pin 65 Q1 DATA OUT Pin 65 Q2 Pin 4 Q2 Pin 65 Q1 Preload / Observe Register Scan Order Quadrant Pin Quadrant 1 Pin DIN Quadrant 2 (Quadrant 3)→ 1-200 5 Q1 B23 Q1 Q2 18 Q2 Pin Q1 Q2 Q1 B17 Q2 19 Pin B11 52 Q2 Q2 ••• Q1 Q2 Q2 Q1 Q2 ATV5000/L B5 Q2 B18 Q2 Q1 ••• Q2 Q1 Q2 B12 Q2 B6 Q2 ••• (Quadrant 2) Q1 (Quadrant 3) Q1 (Quadrant 4) Q1 DOUT 51 Q1 Q2 ••• Q1 Q1 31 ••• 49 56 Q1 17 ••• Q1 ••• 55 Q1 15 22 40 53 Q1 Q1 21 39 Q1 ••• 6 Q2 38 Q2 (Quadrant 2)→ Quadrant 4 Q2 Pin (Quadrant 1)→ Quadrant 3 4 65 B0 Q2 ATV5000/L Power Up Reset Parameter The registers in the ATV5000 are designed to reset during power up. At a point delayed slightly from VCC crossing 3.8 V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1) The VCC rise must be monotonic, 2) After reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3) The signals from which the clock is derived must remain stable during tPR. PA R T I T I O N D E S I G N I N TO M A N A G A B L E P I E C E S S TAT E MACHINES TRUTH TA B L E S TEXT E D I TO R S C H E M AT I C E D I TO R D E S I G N D ATA B A S E (ASCII FILE) C O M P I L E A N D S I M U L AT E ER R O R S? ER R O R S? TRANSFER JEDEC FILE AND PROGRAM H A R D WA R E T E S T ER R O R S? ER R O R S? C O R R EC T SHIP IT! Power-Up Reset Time Min Typ Max Units 600 1000 ns Using The ATV5000 Design Flow Diagram RANDOM G AT E S tPR Description The ATV5000’s simple, regular architecture means that only simple logic compilers are required to configure the device. No layout or route and place are required. These software tools are readily available from companies such as Data I/O Corporation (ABEL ), Logical Devices (CUPL ), MINC Inc. (PLDesigner-XL), and ISDATA (LOGiC ). The first step in designing a device as complex as the ATV5000 is to partition your design into manageable blocks. These blocks are then allocated proportionally to each of the four quadrants of the ATV5000. Random gates can be described either with boolean equations (a behavioral description) or with a schematic editor. Truth table logic and state machines are best described behaviorially and entered with a text editor. The design is then combined into one ASCII file, which is then submitted to the logic compiler. Compilation, logic reduction, simulation, JEDEC file creation and documentation are then completed by all of the popular compilers. Assignment of signals to pins or buried nodes as well as selecting the various options of the ATV5000 (such as register clocks and input latches) can be done manually in the design data base file, or an automatic fitter may be used. A logic fitter assigns pins and nodes to make best use of the features in the ATV5000, and frees the designer from being required to learn all of the features of a complex device such as the ATV5000. For further information on fitters for the ATV5000, contact Atmel’s PLD applications department. After correcting any syntax and logic errors discovered by the compiler, the JEDEC file is ready to download to an PLD programmer. These are available from a number of manufacturers. Programmed devices are usually first tested in the programmer with your supplied test vectors. The next step is check out your "custom chip" in the target system. When this hardware debug step is complete, your system is ready to go— all in a matter of hours. ABEL , CUPL , PLDesigner-XL and LOGiC may be trademarks of others. 1-201 ATV5000 PLCC/PGA Pin Assignments PLCC Pin PGA Pin Name 1 B6 IN 2 A6 3 PLCC Pin PGA Pin Name 18 F2 I/O IN 19 F1 B5 VCC 20 4 A5 I/O 5 B4 6 PLCC Pin PGA Pin Name PLCC Pin PGA Pin Name 35 K6 IN 52 F10 I/O I/O 36 L6 IN 53 F11 I/O G2 VCC 37 K7 VCC 54 E10 VCC 21 G1 I/O 38 L7 I/O 55 E11 I/O I/O 22 H2 I/O 39 K8 I/O 56 D10 I/O A4 I/O 23 H1 I/O 40 L8 I/O 57 D11 I/O 7 B3 I/O 24 J2 I/O 41 K9 I/O 58 C10 I/O 8 A3 I/O 25 J1 I/O 42 L9 I/O 59 C11 I/O 9 A2 I/O 26 K1 I/O 43 L10 I/O 60 B11 I/O 10 B2 I/O 27 K2 I/O 44 K10 I/O 61 B10 I/O 11 B1 I/O 28 L2 I/O 45 K11 I/O 62 A10 I/O 12 C2 I/O 29 K3 I/O 46 J10 I/O 63 B9 I/O 13 C1 I/O 30 L3 I/O 47 J11 I/O 64 A9 I/O 14 D2 I/O 31 K4 I/O 48 H10 I/O 65 B8 I/O 15 D1 I/O 32 L4 IN 49 H11 I/O 66 A8 IN 16 E2 GND 33 K5 GND 50 G10 GND 67 B7 GND 17 E1 I/O 34 L5 IN 51 G11 I/O 68 A7 IN Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units CIN 6 8 pF VIN = 0 V COUT 8 12 pF VOUT = 0 V Note: Conditions 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Security Fuse Usage Erasure Characteristics A single fuse is provided to prevent unauthorized copying of the ATV5000 fuse patterns. Once programmed, all outputs appear programmed during verify. The security fuse should be programmed last (after verifying all other programmed bits), as its effect is immediate. The security fuse also inhibits preload and observability. The entire memory array of an ATV5000 is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 µW/cm2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W• sec/cm2. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. 1-202 ATV5000/L ATV5000/L SUPPLY CURRENT vs. INPUT FREQUENCY ATV5000 (TA = 25C, VCC = 5V) S U P P L Y 200 150 C U R R E N T 100 50 0 m A 0 3 6 9 12 15 18 21 INPUT FREQUENCY (MHz) SUPPLY CURRENT vs. INPUT FREQUENCY S U P P L Y C U R R E N T m A ATV5000L (TA = 25C, VCC = 5V) 200 150 100 50 0 0 3 6 9 12 15 18 21 INPUT FREQUENCY (MHz) 1-203 Ordering Information tPD (ns) tCOS (ns) fMAX (MHz) 25 15 30 20 35 25 Ordering Code Package 50 ATV5000-25JC ATV5000-25KC ATV5000-25UC 68J 68KW 68UW Commercial (0°C to 70°C) 40 ATV5000-30JC ATV5000-30KC ATV5000-30UC 68J 68KW 68UW Commercial (0°C to 70°C) ATV5000-30KI ATV5000-30UI 68KW 68UW Industrial (-40°C to 85°C) ATV5000-30KM ATV5000-30UM 68KW 68UW Military (-55°C to 125°C) ATV5000-30KM/883 ATV5000-30UM/883 68KW 68UW Military/883C Class B, Fully Compliant (-55°C to 125°C) ATV5000-35JC ATV5000-35KC ATV5000-35UC 68J 68KW 68UW Commercial (0°C to 70°C) ATV5000-35KI ATV5000-35UI 68KW 68UW Industrial (-40°C to 85°C) ATV5000-35KM ATV5000-35UM 68KW 68UW Military (-55°C to 125°C) ATV5000-35KM/883 ATV5000-35UM/883 68KW 68UW Military/883C Class B, Fully Compliant (-55°C to 125°C) ATV5962-93248 02M XX ATV5962-93248 02M YX 68KW 68UW Military/883C Class B, Fully Compliant (-55°C to 125°C) Ordering Code Package 33 Operation Range 35 25 33 tPD (ns) tCOS (ns) fMAX (MHz) 30 20 40 ATV5000L-30JC ATV5000L-30KC ATV5000L-30UC 68J 68KW 68UW Commercial (0°C to 70°C) 35 25 33 ATV5000L-35JC ATV5000L-35KC ATV5000L-35UC 68J 68KW 68UW Commercial (0°C to 70°C) ATV5000L-35KI ATV5000L-35UI 68KW 68UW Industrial (-40°C to 85°C) ATV5000L-35KM ATV5000L-35UM 68KW 68UW Military (-55°C to 125°C) ATV5000L-35KM/883 ATV5000L-35UM/883 68KW 68UW Military/883C Class B, Fully Compliant (-55°C to 125°C) ATV5962-93248 03M XX ATV5962-93248 08M YX 68KW 68UK Military/883C Class B, Fully Compliant (-55°C to 125°C) 35 1-204 25 33 ATV5000/L Operation Range ATV5000/L Ordering Information Package Type 68J 68 Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 68KW 68 Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) 68UW 68 Pin, Windowed, Ceramic Pin Grid Array (PGA) 1-205