1/4 STRUCTURE PRODUCT SERIES Silicon Monolithic Integrated Circuit 7-Channel Switching Regulator Controller for Digital Camera TYPE BD9354MWV PIN ASSIGNMENT BLOCK DIAGRAM PACKAGE Functions ● Fig.1 Fig.1 Fig.2 Power supply voltage 2.2~5.5V(at start-up), 2.05~5.5V(after start-up) ● CH1step-down converter, CH2cross converter, CH3 step-down converter, CH4 step- down converter CH5 inverting converter for CCD, CH6 boost converter for CCD, CH7 boost converter for LED ● All Internal Power MOSFETs ● Built-In MOSFETs for synchronous rectifying action mode on CH1~4 ● Built-In feedback resistors on CH2 ● All channels contain internal compensation between inputs outputs of error amps ● Contains sequence control circuit for CH1~4 ● Operating frequency 1.5MHz(CH1,3,4)、750KHz(CH2,5,6,7) ● Built-In Short-circuit Protection (SCP) ● CH6 have high side switches with soft start function ● Built-In Over voltage Protection (OVP) ● Thermally enhanced UQFN036V5050 package(5mm×5mm, 0.4mm pitch) ○Absolute maximum ratings(Ta=25℃) Parameter P o w e r I n p u t O u t p u t P O S J Symbol V o l t a g e c u r r e n t o w e r D i s s i p a t i o p e r a t i n g T e m p e r a t u r t o r a g e T e m p e r a t u r u n c t i o n T e m p e r a t u r n e e e VCC,Hx13,Hx2, Hx4,Hx567,VO2,HS6L STB1234,56 PWM7 Hx5 - Lx5 Lx6 Lx7,VO7 IomaxLx1 IomaxHx2 IomaxHx3 IomaxHx4,Lx4 IomaxHx5 IomaxHS6L IomaxLx6~7 Pd Topr Tstg Tjmax Limit Unit -0.3~7 V -0.3~7 -0.3~7 -0.3~15 -0.3~20 -0.3~21 ±0.8 ±1.5 ±0.8 ±1.0 ±1.5 ±1.2 ±1.2 0.88 *1 -25~+85 -55~+150 +150 V V V V V A A A A A A A W ℃ ℃ ℃ *1 Should be derated by 7.04mW/℃ at Ta=25℃ or more. When mounted on a glass epoxy PCB of 74.2mm×74.2 mm×1.6 mm ○Recommended operating conditions Parameter Power Supply Voltage (at start-up) Power Supply Voltage (after start-up) VREF Pin Connecting Catacitor VREGA Pin Connecting Capacitor PWM7 freqency 【Oscillator】 Oscillator (CH1,3,4) OSC Timing Resistor MIN Limit TYP MAX VCC1 VCC2 CVREF CVREGA fpwm 2.2 2.05 0.047 0.47 20 0.1 1.0 - 5.5 5.5 0.47 4.7 100 V V μF μF kHz fosc RT 0.8 47 1.5 62 1.8 120 MHz kΩ Symbol REV. A Unit 2/4 ○Electrical characteristics(Ta=25℃, VCC=3V, RT=62kΩ, STB1~6=3V,PWM7=2.5V) Standard Value Parameter Symbol MIN TYP MAX 2.2 2.275 Unit Parameter Condition Output Voltage 2.125 V CH1,2,4 Soft Start time Io=5mA 【Under Voltage Lockout】 VCC startup voltage Threshold VCC minimum operating voltage Vuv1 Vuv2 after Turn-On VREGA startup voltage Vuv3 Threshold VREGA minimum operating voltage Vuv4 after Turn-On 【Short Circuit Protection】 Timer Startup Threshold Delay time for SCP 1 Vtcinv Tscp - 1.95 2.05 V - 2.05 2.15 V - - 2.025 V VCC=2.2V - - 2.15 V VCC=2.2V 0.42 50 0.48 70 0.54 90 V msec 1.5 1.7 MHz RT=62kΩ Rrequency CH2,5,6,7 fosc2 0.65 0.75 0.85 MHz RT=62kΩ - - 100 % Vscp=0V - - 100 % 86 92 96 % Dmax2 INV Threshold INV7 Threshold 1 INV7 Threshold 2 INV7 Threshold 3 INV7 Threshold 4 VO2S Input Current 3.5 msec RT=62kΩ 1.5 2.5 msec RT=62kΩ CH5 Soft Start time Tss5 1.8 2.8 3.8 msec RT=62kΩ CH6 Soft Start time Tss6 2.5 3.5 4.5 msec RT=62kΩ SW ON CH2 Lx21 Highside SW ON resistance CH2 Lx21 Lowside SW ON resisitance CH2 Lx22 Highside SW ON resistance CH2 Lx22 Lowside SW ON resistance (※1) 1.3 2.6 5.2 msec Td1 9 15 21 msec RT=62kΩ Td56 0.23 0.42 0.61 msec RT=62kΩ, STB1234=H RON1P - 300 450 mΩ Hx1=3.6V RON1N - 230 350 mΩ Hx1=3.6V RON21P - 120 180 mΩ Hx2=3.6V RON21N - 120 180 mΩ Hx2=3.6V, RON22P - 150 230 mΩ VO2=3.4V RON22N - 120 180 mΩ Hx2=3.6V CH3 Highside SW ON resistance RON3P - 300 450 mΩ Hx3=3.6V CH3 Lowside SW ON resistace RON3N - 230 350 mΩ Hx3=3.6V CH4 Highside SW ON resistace RON4P - 190 290 mΩ Hx4=3.6V CH4 Lowside SW ON resistance RON4N - 110 170 mΩ Hx4=5V CH5 PMOS SW ON resistace RON5P - 600 900 mΩ Hx56=3.6V - - 100 % Dmax4 86 92 96 % CH6,7 NMOS SW ON resistance RON6N - 500 800 mΩ IINV - 0 50 nA INV1,3~6=3.0V CH6 Load SW ON resistace RON67P - 200 300 mΩ VINV 0.79 0.80 0.81 V CH1,3~6 【STB1~6】 mV PWM7 Duty=100% VINV7 1 VINV7 2 VINV7 3 VINV7 4 598 630 662 449 473 497 mV PWM7 Duty=75% 234 252 270 mV PWM7 Duty=40% 17 32 47 mV PWM7 Duty=5% STB Control Voltage VO2 IVO2S 3.332 4.7 3.46 8 V 6.7 8.7 uA VO2S= 3.4V -6.00 -5.91 V INV5 1M//200kΩ, 1MΩ(※2) 3.4 CH5 Output Voltage VOUT 5 Line Regulation DVLi - 4.0 12.5 mV VCC= 2.2~5V Output Current When shorted Ios 0.2 1.0 - mA VREF5=0V -6.09 VSTBH1 1.5 - 5.5 V VSTBL1 -0.3 - 0.3 V RSTB1 250 400 700 kΩ H Level VPWMH 2.05 - 4.00 V L Level VPWML 0 - 0.40 V Pull Down Resistance RPWM 250 400 700 kΩ CH7 Delay time for shutdown Toff7 200 300 - μsec RLED - 2 3 Ω VCC=3.6V VOVP7 18 19 20 V VO7 monitor VCC terminal ISTB1 - - 5 μA Hx terminal ISTB2 - - 5 μA Lx terminal ISTB3 - - 5 μA Icc - 5.0 11.0 mA STB1234, STB56 【PWM7】 PWM7 Control Voltage RT=62kΩ 【LEDSW】 LED PIN SW ON resistance 【OVP】 OVP Threshold 【Circuit Current】 Circuit Current (VCC PIN Current) When circuit is operated by 100% duty at CH1,3 and CH4, SCP timer start. So it is possible to use only for transition time shorter than Tscp. Recommend resistor value over 20kΩ between VREF to INV5, because VREF current is under 100uA. And, Please set resistor value considered phase compensation for coil and output capacitor. (※3) Hx56=3.6V Active Stand-by Current (※2) Hx56=3.6V Non Active Pull Down Resistance 【Reference Voltage Vref for CH5】 (※1) TDTC L=6.4μH, Co=4.7μF LED 3pcs (※3) Dmax3 【CH2 Feedback】 CH2 Output Voltage 2.5 0.5 CH1 Lowside SW ON resistance 【Error AMP】 Input Bias Current 1.5 Tss3 CH1 Highside resisitance CH1~7 1.3 Max duty 5,6,7 Max duty CH2 Lx21 Max duty CH2 Lx22 Condition Tss1,2,4 CH1~4 Delay time for Soft Start CH 5,6 Delay time for Soft Start INV pin monitor CH4 fosc1 Max duty 4 Unit 【Output Driver】 Frequency CH1,3,4 Dmax1 d Dmax1 u Standard Value TYP MAX CH3 Soft Start time CH7 Soft Start time 【Oscillator】 Max duty 1,3 MIN 【Soft Start】 【Internal Regulator VREGA】 VREG A Symbol Related to LED quantity , LED forward voltage and Input voltage. ◎ This product is not designed for normal operation with in a radioactive environment.. REV. A INV1-7=1.2V INV5=-0.2V VCC= 3.0V 3/4 GND RT INV4 INV1 INV3 26 25 24 23 22 21 SCP VREF5 27 VREGA INV5 ○PIN Assignment ・Block Diagram 20 19 2.5V REG 18 VO2S + + - INV7 29 - - + - + - - + 1.0V VREF + OSC INV6 28 17 VCC + - 30 16 VO2 VO7 31 PWM7 32 HS6L 33 HX567 34 15 LX22 OVP PWM & LOGIC BLOCK FILTER PRE DRIVER LED 14 PGND2 13 LX21 12 HX2 PRE DRIVER PRE DRIVER STB56 35 11 LX3 PRE DRIVER 36 PRE DRIVER LX5 PRE DRIVER PRE DRIVER 10 PGND13 1 2 3 4 5 6 7 8 9 LX6 PGND567 LX7 PGND4 LX4 HX4 STB1234 HX13 LX1 B.G CTL ○Package Fig .1 ○PIN Description 端 子 名 機 VCC IC Power Supply Input GND Ground 能 PGND13,2,4,567 Ground for Internal FET VREGA BD9354 VREF5 Hx13,2,4,567 Lx1,3,4,5,6,7 Terminal for Connecting Inductor Lx22 VO2 CH2 DC/DC Output Output Terminal for Internal Load Switch VO2S RT SCP STB1234,56 PWM7 REV. A Terminal for Connecting Inductor For CH2 Input Terminal for Connecting Inductor For CH2 Output HS6L INV1,3,4,5,6,7 図-2 CH5 Reference Output CH1~3,5,6 Pch FET Source Terminal , FET Driver Power Supply Lx21 LOT No. VREGA Output Error Amp Inverted Input CH2 Output Feedback Terminal Terminal for Connecting a Resister To Set the OSC Frequency SCP Timer Flag Terminal CH1~CH6 ON/OFF Control Terminal CH7 ON/OFF Control, PWM Dimming Input LED Terminal for connecting LED Cathode VO7 CH7 DC/DC Output 4/4 ○Operation Notes 1.) Absolute maximum ratings This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. 2.) GND potential Make sure GND is connected at lowest potential. All pins except NON5, must not have voltage below GND. Also, NON5 pin must not have voltage below - 0.3V on start up. 3.) Setting of heat Make sure that power dissipation does not exceed maximum ratings. 4.) Pin short and mistake fitting Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output to GND condition will not happen because this may damage the IC. 5.) Actions in strong magnetic field Exposing the IC within a strong magnetic field area may cause malfunction. 6.) Mutual impedance Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and capacitor network to keep the ripple voltage minimum. 7.) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. 8.) Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply injection. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. 9.) IC Terminal Input This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed. For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.15): ○When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. ○When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other elements in the proximity of the aforementioned parasitic diode. Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to the input terminal. Transistor (NPN) B E (Terminal B) C Resistor (Terminal A) GND (TerminalA) P P+ N N P-board P P+ P+ N N N P+ Parasitic element N P-board Parasitic element ~ ~ N GND Parasitic l t Fig - 3 Simplified structure of a Bipolar IC REV. A GND Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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