1/4 STURUCTURE Silicon Monolithic Integrated Circuit Type PRODUCUT SERIES 4 Channel Switching Regulator control system for DSC BD9855MWV THYSICAL DIMENSIONS Package(Plastic Mold) Fig.1、Block Diagram Fig.2、Pin Description Fig.3 ●Include step-down 2ch,Cross converter 1ch,step down/inverting 1ch. ●Short Circuit Protection (SCP), Under Voltage Lockout Function (UVLO), Include external synchronous rectification operation ●Independent ON/OFF Function Each Channel、UQFN044V6060 Package(0.4mm pitch) ○Absolute Maximum Ratings(Ta=25℃) FEATURES Parameter Symbol Limits Units P o w e r S u p p l y Vo l t a g e VCC,PVCC -0.3~15 V BST1-LX1、BST2-LX2 -0.3~7 V LX31 -0.3~15 V Vo3,LX32 -0.3~8.4 V PG,SYNC, CTL1,2,3,4 -0.3~15 V I n p u t V o l t a g e SEL -0.3~7 V Pd 540(*1),1000(*2) mW Topr -25~+85 ℃ S t o r a g e Te m p e r a t u r e Tstg -55~+150 ℃ J u n c t i o n Te m p e r a t u r e Tjmax 150 ℃ Power Dissipation O p e r a t i n g Te m p e r a t u r e (*1) Without external heat sink, the power dissipation degrades by 4.2mW/℃ above 25℃. (*2)Power dissipation degrades by 8.0mW/℃ above 25℃, when mounted on a PCB (70mm×70mm×1.6mm). ○Operating Conditions Parameter Spec. Symbol Unit MIN TYP MAX 4 6 14 【Input Voltage】 Power Supply Voltage VCC,PVCC V 【Reference Output】 CVR* 0.47 1.0 2.2 μF CVREF 0.047 0.1 2.2 μF CSCP 0.001 - 2.2 μF Fosc 0.6 1.0 1.5 MHz RT 47 82 120 kΩ CRTSS 1000 10000 - pF SYNC terminal input H VSYNCH 3.0 - VCC V SYNC terminal input L VSYNCL -0.3 - 0.5 V Dsync 40 50 60 % VREG,VREGA terminal capacitor VREF terminal capacitor 【Protect Circuit】 SCP terminal capacitor 【Oscillator】 Oscillator frequency OSC timming resistor RTSS terminal capacitor SYNC terminal input Duty 【Driver】 BST-Lx voltage Vbst 3.5 - 5.5 V BST-Lx capacitor Cbst 0.047 0.1 0.22 μF V VLX31 - - 14 VVOUT3 4.0 - 7.0 V PVCC1,2,4 terminal input voltage PVCC1,2,4 - - 14 V CH1,2,3output current Ioutch1,2,3 - - 1 A LX31terminal input voltage CH3 output range ※)Please connect capacitor at input/output terminal (VCC,PVCC,VREF,VREG etc.) to operate IC stabilize. Status of this document The Japanese language version of this document shall be the official specification. Any translation of this document shall be for reference only. REV. C Condition 2/4 ○Electrical Characteristics(Ta=25℃,VCC=PVCC=6V, RT=82kohm, CTL1~4=3V with no designation) Parameter Standard value TYP MAX Units 4.8 5 5.2 V Ireg=1mA 2.4 2.5 2.6 V Ireg=1mA Vstd1,2 3.4 3.6 3.8 V VCCMonitor,VREGMonitor Vhys1,2 - 0.1 0.2 V VCC cancel ,VREG cancel Symbol MIN 【Internal Regulator】 Regulator Output voltage for Boost terminal VREG Regulator Output Voltage for inside standard VREGA Threshold Voltage1,2 Hysterisis voltage width Conditions Test circuit 【Under Voltage Lock Function】 【Short Circuit Protection】 Timer Start Threshold Voltage Vtc 2.1 2.2 2.3 V Iscp1 2.5 5 7.5 μA SCP Threshold Voltage Vtsc 0.45 0.5 0.55 V Stand by Voltage Vssc - 10 100 mV SCP Out Source Voltage FB Pin Monitor VSCP=0.1V 【Oscillator】 fosc123 0.8 1 1.2 MHz Fosc4 0.4 0.5 0.6 MHz Max duty 1,2(Step Down) Dmax1,2 - - 100 % Max duty CH3 Lx31 Dmax31 - - 100 % Max duty CH3 Lx32 Dmax32 78 84 90 % Max duty 4 Dmax4 86 92 96 % SEL=VREGA RTSS Pin Standby Voltage RTSSF - 1 20 mV CTL1~4=0V RTSS Pin smk Current IRTSSI -7 -5 -3 μA RTSS Pin source Current IRTSSO 3 5 7 μA Frequency CH1~3 Frequency CH4 RT=82kΩ、SEL=GND RT=82kΩ、SEL=VREGA Vscp=0V ※ 【Error AMP】 IINV - 30 100 nA INV1~4, NON4=0V INV Threshold Voltage 1 VINV1 0.79 0.8 0.81 V CH1~3 NON_INVoffset Voltage Voff - - 5 mV Input Bias Current NON4=1V, INV4=FB4 【Reference Voltage VREF】 VREF Output Voltage VOREF 0.99 1 1.01 V Line Regulation DVLi - 1 7.5 mV Load Regulation DVLo - 1 7.5 mV Iref=10μA~100μA Ios 2 10 - mA Vref=0V VSCP=0.1V Output Current when shorted VCC=4.8~8.4V 【Soft Start】 SS1,2,3,4 source current Iss 1 2 3 μA SS Discharge Resistance RdisSS - 500 1000 Ω Vss=0.2V 【Output Driver】 CH1,2 Highside SW ON Resistance RON12p - 200 350 mΩ ILX=50mA CH1,2 Highside SW ON Resistance RON12N - 150 300 mΩ ILX=-50mA CH3 Driver Output Voltage H Vout3H PVCC-1.0 PVCC -0.5 - V IOUT3=50mA CH3 Driver Output Voltage L Vout3L - 0.5 1 V IOUT3=-50mA CH3 Lx31Pin Lowside SW ON Resistance RON31N - 250 400 mΩ CH3 Lx32Pin Highside SW ON Resistance CH3 Lx32Pin Lowside SW ON Resistance RON32p - 200 350 mΩ Vo3=6.0V, ILX=50mA RON32N - 150 300 mΩ ILX=-50mA CH4 Driver Output Voltage H Vout4H PVCC-1.0 PVCC -0.5 - V IOUT4=50mA,INV4=1.1V CH4 Driver Output Voltage L Vout4L - 0.5 1 V IOUT4=-50mA,INV4=0.9V RonPG - 0.5 1 kΩ PG=1V IlkPG - 0 1 uA PG=15V VCTLH VCTLL VSELH VSELL RCTL,RSEL 2 -0.3 2 -0.3 - Vcc 0.8 7 0.8 V V V V 250 400 700 kΩ STAND-by Current Circuit Current(VCC,PVCC Pin Input Current) ISTB - 0 5 μA CTL1~4=0V Icc - 4 8 mA INV=2.5V,NON=1V Circuit Current(Application Io=none) Iccapl - 25 35 mA All CH ON ILX=-50mA 【PG Output Pin】 PG Pin ON Resistance PG Pin Leak Current 【Control terminal】 CTL terminal voltage(ON), CTL terminal voltage (OFF), SEL terminal voltage (? frequency) SEL terminal voltage (same frequency) CTL,SEL Pull down Resistance 【Circuit Current】 ※The protective circuit start working when circuit is operated by 100% duty. So it is possible to use only for transition time shorter than charge time for SCP. ◎This product is not designed for normal operation with in a radioactive environment. REV. C 3/4 ○ Package BD9855 Lot No. Plastic Mold (UNIT:mm) Fig.1 ○ Block Diagram ○ Pin Description BST1 FB1 BST1 INV1 + + SS1 BST1 PVCC1 ERRORAMP1 Lx1 CH1 Step Down (Current mode) PGND12 BST2 BST2 FB2 BST2 INV2 PVCC2 ERRORAMP2 + + SS2 Lx2 CH2 Step Down (Current mode) OUT3 PVCC4 FB3 INV3 Lx31 ERRORAMP3 + + SS3 CH3 cross converter PGND3 Lx32 Vo3 FB4 PWMCOMP4 + NON4 + OUT4 - SS4 SS monitor VREF PGND4 + VREF SCP PVCC4 ERRORAMP4 INV4 PROTECTION SCP TIMER LATCH VCC TSD UVLO latch VREGA VREG PG CH_CTL CTL1 CTL2 CTL3 CTL4 OSC SYNC OSC RTSS RT SEL SYNC latch VREGA VREG GND Fig.3 Fig.2 REV. C 4/4 ○Operation Notes 1.) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2.) GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin(except INV4 terminal), including during actual transient phenomena. 3.) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4.) Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. 5.) Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 6.) Common impedance Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). 7.) Voltage of CTL pin The threshold voltages of CTL pin are 0.8V and 2.0V. STB state is set below 0.8V while action state is set beyond 2.0V. The region between 0.8V and 2.0V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF. 8.) Thermal shutdown circuit (TSD circuit) This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. 9.) IC pin input This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart, the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input and output pins. (Pin A) (Pin B) C B ~ Transistor (NPN) Resistance E P P+ N N P+ P P+ N N (PinA) P+ N N P substrate P substrate GND Parasitic elementals Parasitic elementals Fig.4 Simplified structure of a Bipolar IC REV. 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