UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.0 REVISION HISTORY REVISION DESCRIPTION Preliminary Rev. 0.1 Original. 1.Revised CMOS low power operating : Rev. 1.0 Operating current : 195 150mA (max.) Standby current : 30mA (max.) 1mA(Typ.) 2.Revised power supply : 3.0~3.6V 3.15~3.6V 3.Revised DC CHARACTERISTICE ICC –8ns (max) : 200 150mA ICC –10ns (max) : 195 120mA ICC –12ns (max) : 190 100mA ICC –15ns (max) : 150 80 mA ISB (max) : 30 10mA, ISB (typ) : NA 3mA ISB1 (max) : 10 3mA, ISB1 (typ) : NA 1mA ISB1 (max)<1 mA for special order 4. Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Date Jan 2,2002 May 20,2003 P80077 UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.0 ___________________________________________________________________________________________________________ FEATURES GENERAL DESCRIPTION The UT61L1288 is a 1,048,576-bit high-speed CMOS static random access memory organized as 131,072 words by 8 bits. Fast access time : 8ns for Vcc=3.15V~3.6V 10/12/15ns for Vcc=3.0V~3.6V CMOS low power operating : Operating current : 150mA (max.) Standby current : 1mA (Typ.) Single 3.15~3.6V power supply Operating temperature : Commercial : 0℃~70℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Package : 32-pin 8mm x 13.4mm STSOP The UT61L1288 operates from a single 3.15~3.6V power supply and all inputs and outputs are fully TTL compatible. It is fabricated using high performance, high reliability CMOS technology. PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K × 8 bit MEMORY ARRAY A0 1 32 A16 A1 2 31 A15 A2 3 30 A3 4 29 A13 5 28 OE 6 27 I/O7 7 26 I/O6 Vcc 8 25 Vss Vss 9 24 Vcc 23 I/O5 22 I/O4 CE IO0 IO1 Vcc Vss IO2 IO3 I/O DATA CIRCUIT I/O0-I/O7 CE OE WE COLUMN I/O 10 11 WE 12 21 A12 A4 13 20 A11 A5 14 19 A6 15 18 A9 A7 16 17 A8 STSOP CONTROL CIRCUIT PIN DESCRIPTION SYMBOL A0 - A16 I/O0 - I/O7 CE DESCRIPTION Address Inputs Data Inputs/Outputs Chip enable Input WE Write Enable Input OE VCC VSS NC Output Enable Input Power Supply Ground No Connection _________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80077 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 A14 A10 UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.0 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to Vss Operating Temperature Commercial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 0 to 70 -65 to 150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE H L L L OE X H L X WE X H H L I/O OPERATION SUPPLY CURRENT High - Z High - Z DOUT DIN ISB,ISB1 ICC ICC ICC H = VIH, L=VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃) PARAMETER SYMBOL TEST CONDITION Power Voltage VCC Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIH VIL ILI ILO VOH VOL Operating Power Supply Current ICC Standby Current (TTL) ISB Standby Current (CMOS) ISB1 8 10/12/15 VSS ≦VIN ≦VCC VSS ≦VI/O ≦VCC; Output Disable IOH= -4mA IOL= 8mA Cycle time=min, 100%duty 8 10 I/O=0mA, CE =VIL 12 15 CE =VIH, other pins =VIL or VIH CE =VCC-0.2V, other pins at 0.2V or Vcc-0.2V MIN. TYP. MAX. 3.15 3.3 3.6 3.0 3.3 3.6 2.0 VCC+0.3 -0.3 0.8 -2 2 -2 2 2.4 0.4 150 120 100 80 3 10 - 1 3* 4 UNIT V V V V µA µA V V mA mA mA mA mA mA Notes: 1. Overshoot : Vcc+3.0v for pulse width less than 6ns. 2. Undershoot : Vss-3.0v for pulse width less than 6ns. 3. Overshoot and Undershoot are sampled, not 100% tested. 4. ISB1< 1mA for special order or requirement. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80077 UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev 1.0 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX. 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 3ns 1.5V CL=30pF, IOH/IOL= -4mA / 8mA AC ELECTRICAL CHARACTERISTICS (TA = 0℃ to 70℃) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change UT61L1288 UT61L1288 UT61L1288 UT61L1288 -8 -10 -12 -15 SYMBOL VCC=3.15∼3.6 VCC=3.0∼3.6 VCC=3.0∼3.6 VCC=3.0∼3.6 MIN. MAX. MIN. MIN. MIN. MAX. MIN. MAX. tRC 8 10 12 15 tAA 8 10 12 15 tACE 8 10 12 15 tOE 4 5 6 7 tCLZ* 3 3 3 3 tOLZ* 0 0 0 0 tCHZ* 4 5 6 7 tOHZ* 4 5 6 7 tOH 3 3 3 3 - UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z UT61L1288 UT61L1288 UT61L1288 UT61L1288 -8 -10 -12 -15 SYMBOL VCC=3.15∼3.6 VCC=3.0∼3.6 VCC=3.0∼3.6 VCC=3.0∼3.6 MIN. MAX. MIN. MIN. MIN. MAX. MIN. MAX. tWC 8 10 12 15 tAW 7 8 9 10 tCW 7 8 9 10 tAS 0 0 0 0 tWP 7 8 9 10 tWR 0 0 0 0 tDW 5.5 6 7 8 tDH 0 0 0 0 tOW* 3 3 3 3 tWHZ* 4 5 6 7 UNIT *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80077 ns ns ns ns ns ns ns ns ns ns UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev 1.0 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE OE tCHZ tOE tOHZ tCLZ tOLZ Dout t OH High-Z Data Valid High-Z Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low. 3.Address must be valid prior to or coincident with CE =low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80077 UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev 1.0 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tRC Address tAA tOH Dout tOH Previousdatavalid DataValid WRITE CYCLE 2 ( CE Controlled) (1,2,5,6) t RC Address tAA CE tACE OE tCHZ tOE tOHZ tCLZ tOLZ Dout t OH High-Z Data Valid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 High-Z P80077 UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev 1.0 Notes : 1. WE , CE must be high during all address transitions. 2.A write occurs during the overlap of a low CE , low WE . 3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80077 UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev 1.0 PACKAGE OUTLINE DIMENSION 32-pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 32 16 17 b E e 1 "A" Seating Plane D 16 y 17 0.254 A2 A GAUGE PLANE A1 0 SEATING PLANE L1 "A" DATAIL VIEW 32 1 UNIT SYMBOL A A1 A2 b D E e HD L1 y Θ INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 ±0.001 0.465 ±0.004 0.315 ±0.004 0.020 (TYP) 0.528 ±0.008 0.0315 ±0.004 0.003 (MAX) o o 0 ∼5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.200 ±0.025 11.800 ±0.100 8.000 ±0.100 0.50 (TYP) 13.40 ±0.20. 0.80 ±0.10 0.076 (MAX) o o 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80077 UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev 1.0 ORDERING INFORMATION PART NO. UT61L1288LS-8 UT61L1288LS-10 UT61L1288LS-12 UT61L1288LS-15 ACCESS TIME (ns) 8 10 12 15 PACKAGE 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP ORDERING INFORMATION (for lead free product) PART NO. UT61L1288LSL-8 UT61L1288LSL-10 UT61L1288LSL-12 UT61L1288LSL-15 ACCESS TIME (ns) 8 10 12 15 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 PACKAGE 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP P80077 UTRON UT61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev 1.0 THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80077