UTRON Rev. 1.1 UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM REVISION HISTORY REVISION Rev. 1.0 Rev. 1.1 DESCRIPTION Original. 1. Delete Partial refresh function 2. Add Package : 48-pin 12mmX20mm TSOP-I UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Draft Date Apr. 15, 2003 Aug. 06,2003 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 FEATURES GENERAL DESCRIPTION The UT65L168 is a 8,388,608-bit CMOS random access memory organized as 524,288 words by 16 bits. It is fabricated using PSEUDO SRAM techniques, yields high-density and low power consumption device. Fast access time : 60/70ns (max.) Low operating power Operating current : 20mA (typ) Standby current : 50uA (typ) Power supply voltage : 2.5V~3.3V Operating temperature : Extended(E) : -20℃ ~ 80℃ Industrial(I) : -40℃ ~ 85℃ Low power modes Deep power Down : Isb < 10uA Three state output and TTL compatible Separated I/O power (Vccq) & Core Power (Vcc) Page mode operation by 8 words Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 48-pin 6.0mm × 8.0mm TFBGA 48-pin 12mmX20mm TSOP-I The UT65L168 is design for upper and low byte access by data byte control ( UB 、 LB ).It has low power modes by using control pin ZZ . PIN DESCRIPTION SYMBOL A0 - A18 I/O1 - I/O16 CE A0-A18 DECODER I/O DATA CIRCUIT COLUMN I/O Vcc Vccq Vss I/O1-I/O8 Lower Byte I/O9-I/O16 Upper Byte Output Enable Input Lower Byte Control LB UB Upper Byte Control ZZ VCC Vccq VSS NC Low Power Modes Core Power I/O power Ground No Connection PIN CONFIGURATION A CE OE WE LB UB Write Enable Input WE OE FUNCTIONAL BLOCK DIAGRAM 512K × 16 MEMORY ARRAY DESCRIPTION Address Inputs Data Inputs/Outputs Chip enable Input CONTROL CIRCUIT ZZ LB OE A0 A1 A2 ZZ B I/O9 UB A3 A4 CE I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 A17 A7 I/O4 Vcc E Vccq I/O13 Vss A16 I/O5 Vss F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H A18 A8 A9 A10 A11 NC 1 2 3 4 5 6 TFBGA UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 PIN CONFIGURATION A13 A14 A15 A16 A17 A18 A1 A0 NC NC WE ZZb NC UB LB A10 A9 A8 A7 A6 A5 A4 A3 A2 48 47 46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 UT65L168 23 24 A12 NC Vss I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 Vcc I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 OE Vss CE A11 TSOP-I ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on any pin relative to VSS Voltage on Vcc supply relative to VSS Extended Operating Temperature Industrial Storage Temperature Power Dissipation SYMBOL VIN, VOUT VCC TA TA TSTG PD RATING -0.2 to Vcc+0.3 -0.2 to 4.2 -25 to 80 -40 to 85 -65 to +150 1.0 UNIT V V ℃ ℃ ℃ W *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE OE WE LB UB ZZ Standby H X X X X H L L L L L L L L X H H L L L X X X X H H H H H L L L X L X L H L L H L X X L H L L H L L X H H H H H H H H L Output Disable Read Write Deep Power Down Note: I/O OPERATION SUPPLY CURRENT I/O1-I/O8 I/O9-I/O16 High – Z High – Z ISB, ISB1 High – Z High – Z ICC,ICC1,ICC2 DOUT High – Z DOUT DIN High – Z DIN High – Z High – Z DOUT DOUT High – Z DIN DIN High – Z ICC,ICC1,ICC2 ICC,ICC1,ICC2 ISB0 H = VIH, L=VIL, X = Don't care. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 DC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.3V) PARAMETER Power Voltage SYMBOL VCC TEST CONDITION MIN. 2.5 TYP. 3.0 MAX. 3.3 UNIT V I/O operating voltage Vccq 2.5 3.0 3.3 V Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage *1*3 VIH *2*3 VIL 2.2 -0.2 -1 -1 2.2 - 2.7 - VCC+0.2 0.4 1 1 0.4 V V µA µA V V - 20 30 mA CE ≦0.2V, ZZ = VIH VIN ≦ 0.2V or VIN ≧Vcc-0.2V - - 7 mA - - 0.3 mA - 50 70 µA - - 10 µA ILI ILO VOH VOL Icc Average Operating Current VSS ≦VIN ≦VCC VSS ≦VI/O ≦VCC; Output Disable IOH= -1mA IOL= 2mA Cycle time=Min,100%duty, II/O=0mA CE =VIL , ZZ = VIH , VIN=VIL or VIH Cycle time=1µs,100%duty, II/O=0mA Icc1 Standby Current (TTL) ISB CE = ZZ =VIH, other inputs =VIL or VIH Standby Current (CMOS) ISB1 CE ≧Vcc-0.2 , ZZ ≧Vcc-0.2V other inputs = 0 ~ Vcc Deep Power Down ISB0 ZZ ≦0.2V, other pins = 0 ~ Vcc No refresh LL LL Note : *1.Overshoot : Vcc+1.0V in case of pulse width ≦ 20ns. *2.Undershoot : -1.0V in case of pulse width ≦ 20ns. *3.Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 8 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to 2.4V 5ns 1.5V CL = 30pF+1TTL, IOH/IOL = -1mA / 2mA AC ELECTRICAL CHARACTERISTICS (VCC =2.5V~3.3V) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip enable to output Output Enable to Valid Output Chip enable to Low-Z output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change LB , UB Access Time LB , UB LB , UB Disable to High-Z Output Enable to Low-Z Output SYMBOL tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH tBA tBHZ tBLZ UT65L168-60 MIN. MAX. 60 40k 60 60 25 10 5 0 5 0 5 5 60 0 5 10 - UT65L168-70 MIN. MAX. 70 40k 70 70 25 10 5 0 5 0 5 5 70 0 5 10 - UT65L168-60 MIN. MAX. 60 40k 50 50 0 50 0 20 0 5 0 5 50 - UT65L168-70 MIN. MAX. 70 40k 60 60 0 50 0 20 0 5 0 5 60 - UT65L168-60 MIN. MAX. 25 25 40k UT65L168-70 MIN. MAX. 25 25 40k UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Write to Output High Z LB , UB Valid to End of Write SYMBOL tWC tAW tCW tAS tWP tWR tDW tDH tOW tWHZ tBW UNIT ns ns ns ns ns ns ns ns ns ns ns (3) PAGE MODE CYCLE PARAMETER Page Mode Cycle Time Page Mode Address Access Time Maximum Cycle Time SYMBOL tPC tPAA tMRC UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 UNIT ns ns ns P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 POWER UP SEQUENCE 1. 2. 3. Apply power Maintain stable power for a minimum of 200us with CE =VIH Issue read operation at least 2 times STANDBY MODE STATE MACHINES CE = VIH Power on Initial State (wait 200us) Standby Mode UB or/and LB=VIL CE = VIL , ZZ = VIH CE = VIH ZZ = VIH Active mode ZZ = VIL optinal ZZ = VIL Deep power down mode CE = VIH , ZZ = VIH STANDBY MODE CHARACTERISTICS Mode Standby Deep Power Down Memory cell data Full array Valid Full array Invalid Standby current (µA) 70 (ISB1) LL 10 (ISB0) LL UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 Wait time (µs) 0 200 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled, OE = CE =VIL , WE = ZZ =VIH , LB and/or UB =VIL) tRC Address tAA tOH tOH DOUT Data Valid READ CYCLE 2 ( WE = ZZ =VIH) t RC Address t AA t ACE CE t CHZ t OE t OLZ OE t OHZ t BLZ t BA LB , UB t BHZ t OH t CLZ Dout HIGH-Z HIGH-Z Data Valid Notes : 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ(Max.) is less than tCLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 40us. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 WRITE CYCLE 1 ( WE Controlled, ZZ =VIH ) t WC Address t AW CE t CW (2) t AS (3) t WR (4) t WP (1) WE t BW LB , UB t WHZ t OW High-Z Dout t DW Din t DH Data Valid WRITE CYCLE 2 ( CE Controlled, WE = ZZ =VIH) t WC Address CE t AS (3) WE LB , UB Dout t AW t CW (2) t WP (1) t t WR (4) BW High-Z High-Z t t DW Din DH Data Valid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 WRITE CYCLE 3 ( LB , UB controlled, ZZ =VIH) t WC Address t AW CE t CW (2) t WR (4) t WP (1) WE t BW LB , UB t AS (3) Dout High-Z High-Z t DH t DW Din Data Valid Notes : 1. A write occurs during the overlap (tWP) of low WE and CE . A write begins when CE goes low and WE goes low with asserting LB or UB for single byte operation or simultaneously asserting LB and UB for double byte operation. A write ends at the earliest transition when CE goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CE going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. The tWR applied in case a write ends as CE or WE going high. 5. Don’t access device with cycle timing shorter than tRC (tWC) for continuous periods > 40us. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 PAGE READ CYCLE ( ZZ = WE =VIH, 8 words access ) tPC tRC tPC tPC tPC tPC tPC tPC A0~A2 tAA A3~A18 tOH tACE CE tCHZ tBA UB , LB tBHZ tOE OE tCLZ Data Out High - Z tOLZ tBLZ tPAA data valid tPAA data valid tPAA data valid tPAA data valid tPAA data valid tPAA data valid tPAA data valid tOHZ data valid 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ(Max.) is less than tCLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 40us UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80094 UTRON Rev. 1.1 UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM PACKAGE OUTLINE DIMENSION 48-pin 6.0mm × 8.0mm TFBGA Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 P80094 UTRON Rev. 1.1 UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM PACKAGE OUTLINE DIMENSION 48 pin 12mm x 20mm TSOP-I Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 P80094 UTRON UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM Rev. 1.1 ORDERING INFORMATION Extended temperature PART NO. UT65L168BS-60LLE UT65L168BS-70LLE UT65L168LC-60LLE UT65L168LC-70LLE ACCESS TIME (ns) 60 70 60 70 STANDBY CURRENT (µA) Typ. 50 50 50 50 ACCESS TIME (ns) 60 70 60 70 STANDBY CURRENT (µA) typ 50 50 50 50 PACKAGE 48 PIN TFBGA 48 PIN TFBGA 48 PIN TSOP-I 48 PIN TSOP-I Industrial temperature PART NO. UT65L168BS-60LLI UT65L168BS-70LLI UT65L168LC-60LLI UT65L168LC-70LLI UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 PACKAGE 48 PIN TFBGA 48 PIN TFBGA 48 PIN TSOP-I 48 PIN TSOP-I P80094 UTRON Rev. 1.1 UT65L168(E)/UT65L168(I) 512K X 16 BITS LOW POWER PSEUDO SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 14 P80094