STL100NHS3LL N-channel 30V - 0.0032Ω - 22A - PowerFLAT™ (6x5) STripFET™ Power MOSFET plus monolithic Schottky Preliminary Data Features Type VDSS RDS(on) ID STL100NHS3LL 30V < 0.0042Ω 22A(1) 1. This value is rated according to Rthj-pcb ■ Optimal RDS(on) x Qg trade-off @ 4.5V ■ Reduced switching losses ■ Reduced conduction losses ■ Improved junction-case thermal resistance PowerFLAT™(6x5) Application ■ Switching applications Figure 1. Description Internal schematic diagram This product utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology and a proprietary process for integrating a monolithic Schottky diode. The new Power MOSFET is optimized for the most important demanding synchronous switch function in DCDC converter for Computer and Telecom. Table 1. Device summary Order code Marking Package Packaging STL100NHS3LL L100NHS3LL PowerFLAT™ (6 x 5) Tape & reel September 2007 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/9 www.st.com 9 Electrical ratings 1 STL100NHS3LL Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit 30 V ± 16 V Drain current (continuous) at TC = 25°C 22 A ID (1) Drain current (continuous) at TC = 100°C 13.7 A ID(2) Drain current (continuous) at TC = 25°C 100 A VDS Drain-source voltage (VGS = 0) VGS Gate-source voltage ID (1) (3) Drain current (pulsed) 88 A PTOT(1) Total dissipation at TC = 25°C 80 W PTOT(2) Total dissipation at TC = 25°C 4 W -55 to 150 °C Value Unit Thermal resistance junction-case (drain) Max 1.56 °C/W Thermal resistance junction-pcb Max 31.3 °C/W IDM Tj Tstg Operating junction temperature Storage temperature 1. The value is rated accordingly to Rthj-pcb 2. This value is according Rthj-c 3. Pulse width limited by safe operating area Table 3. Thermal resistance Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on FR-4 board of 1inch2, 2 oz. Cu., t<10sec Table 4. 2/9 Thermal resistance Symbol Parameter Value Unit IAV Avalanche current, not repetitive (pulse width limited by Tjmax) 10 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID=IAV, VDD=24V) 1.8 J STL100NHS3LL 2 Electrical characteristics Electrical characteristics (TCASE=25°C unless otherwise specified) Table 5. Symbol On/off states Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage ID = 1mA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = 24V 500 µA IGSS Gate body leakage current (VDS = 0) VDS = ± 16V ±100 nA Gate threshold voltage VDS= VGS, ID = 1mA 2.5 V V(BR)DSS VGS(th) RDS(on) Table 6. Symbol Static drain-source on resistance 30 V 1 VGS= 10V, ID= 11A VGS= 4.5V, ID= 11A 0.0032 0.0042 0.004 0.0057 Ω Ω VGS=10V, ID=11A@125°C VGS=4.5V, ID=11A@125°C 0.005 0.006 Ω Ω Dynamic Parameter Test conditions Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS=25V, f = 1MHz, VGS=0 Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 15V, ID = 22A, VGS = 4.5V (see Figure 3) Min. Typ. Max. 4200 700 46.2 27 8.5 7.2 Unit pF pF pF 35 nC nC nC 3/9 Electrical characteristics Table 7. Symbol STL100NHS3LL Switching times Parameter Test conditions Typ. Max. Unit td(on) tr Turn-on delay time Rise time VDD = 15V, ID = 11A RG= 4.7Ω, VGS= 10V, (see Figure 2), (see Figure 7) 16 45 ns ns td(off) tf Turn-off delay time Fall time VDD = 15V, ID = 11A RG= 4.7Ω, VGS= 10V, (see Figure 2) (see Figure 7) 68 8 ns ns Table 8. Symbol ISD ISDM VSD (1) trr Qrr IRRM Source drain diode Parameter Test conditions Min. Typ. Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 5A, VGS = 0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 22V, di/dt = 100A/µs VDD = 20V, Tj = 25°C (see Figure 4) 1. Pulsed: Pulse duration = 300µs, duty cycle 1.5% 4/9 Min. 30 30 2 Max Unit 22 88 A A 0.75 V ns nC A STL100NHS3LL Test circuit 3 Test circuit Figure 2. Switching times test circuit for resistive load Figure 4. Test circuit for inductive load Figure 5. switching and diode recovery times Unclamped inductive load test circuit Figure 6. Unclamped inductive waveform Switching time waveform Figure 3. Figure 7. Gate charge test circuit 5/9 Package mechanical data 4 STL100NHS3LL Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 6/9 STL100NHS3LL Package mechanical data PowerFLAT™ (6x5) MECHANICAL DATA mm. inch DIM. A MIN. TYP MAX. MIN. TYP. 0.80 0.83 0.93 0.031 0.032 0.036 0.02 0.05 0.0007 0.0019 A1 A3 b 0.20 0.35 0.40 0.007 0.47 0.013 0.015 D 5.00 0.196 D1 4.75 0.187 D2 4.15 4.20 4.25 0.163 0.165 E 6.00 0.236 E1 5.75 0.226 E2 3.43 3.48 3.53 E4 2.58 2.63 2.68 e L 0.135 1.27 0.70 0.80 MAX. 0.018 0.167 0.137 0.139 0.103 0.105 0.050 0.90 0.027 0.031 0.035 7/9 Revision history 5 STL100NHS3LL Revision history Table 9. 8/9 Document revision history Date Revision 03-Sep-2007 1 Changes First release STL100NHS3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. 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