STL15N3LLH5 N-channel 30 V, 0.0045 Ω, 15 A, PowerFLAT™ (3.3 x 3.3) STripFET™ V Power MOSFET Preliminary Data Features Type VDSS RDS(on) ID STL15N3LLH5 30V <0.0054Ω 15A (1) 1. The value is rated according Rthj-pcb ■ RDS(on) * Qg industry benchmark ■ Extremely low on-resistance RDS(on) ■ Very low switching gate charge ■ High avalanche ruggedness PowerFLAT™(3.3x3.3) ■ Low gate drive power losses (Chip scale package) Applications ■ Switching applications Figure 1. Internal schematic diagram Description This product utilizes the 5th generation of design rules of ST’s proprietary STripFET™ technology. The lowest available RDS(on)*Qg, in this chip scale package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved. Table 1. Device summary Order code Marking Package Packaging STL15N3LLH5 15N3LLH5 PowerFLAT™ (3.3 x 3.3) Tape and reel August 2008 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/10 www.st.com 10 Contents STL15N3LLH5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2/10 ................................................ 6 STL15N3LLH5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit 30 V ± 22 V VDS Drain-source voltage (VGS = 0) VGS Gate-source voltage ID(1) Drain current (continuous) at TC = 25 °C 15 A ID (1) Drain current (continuous) at TC=100 °C 9.3 A (2) Drain current (pulsed) 60 A PTOT(3) Total dissipation at TC = 25 °C 50 W PTOT(1) Total dissipation at TC = 25 °C 2 W 0.4 W/°C -55 to 150 °C Value Unit IDM Derating factor TJ Operating junction temperature storage temperature Tstg 1. The value is rated according Rthj-pcb 2. Pulse width limited by safe operating area. 3. The vaule is rated according Rthj-c Table 3. Thermal resistance Symbol Rthj-case Parameter Thermal resistance junction-case (drain) 2.5 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 42.8 °C/W Rthj-pcb (2) Thermal resistance junction-pcb 63.5 °C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec 2. Steady state 3/10 Electrical characteristics 2 STL15N3LLH5 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions ID = 250 µA, VGS= 0 Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = ± 22 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 10 V, ID= 7.5 A Symbol Ciss Unit V 1 1 10 µA µA ±100 nA 2.5 V 0.0045 0.0054 0.006 0.0075 Ω Ω Dynamic Parameter Test conditions VGS =4.5 V Qgd Total gate charge Gate-source charge Gate-drain charge RG Gate input resistance Qg Qgs Max. 30 VGS= 4.5 V, ID= 7.5 A VDS =25 V, f=1 MHz, VGS=0 Crss Typ. VDS = Max rating @125 °C Input capacitance Output capacitance Reverse transfer capacitance Coss Min. VDS = Max rating, IDSS Table 5. 4/10 On/off states Min. VDD=15 V, ID = 15 A (see Figure 3) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV Open drain 0.5 Typ. Max. Unit 1500 295 39 pF pF pF 12 4 4.7 nC nC nC 1.5 2.5 Ω STL15N3LLH5 Electrical characteristics Table 6. Symbol td(on) tr td(off) tf Table 7. Symbol Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. 9.3 14.5 22.7 4.5 VDD=15 V, ID= 7.5 A, RG=4.7 Ω, VGS=4.5 V (see Figure 2) Unit ns ns ns ns Source drain diode Max. Unit Source-drain current 15 A ISDM(1) Source-drain current (pulsed) 60 A VSD(2) Forward on voltage 1.1 V ISD trr Qrr IRRM Parameter Reverse recovery time Reverse recovery charge Reverse recovery current Test conditions Min. Typ. ISD=15 A, VGS=0 ISD=15 A, di/dt = 100 A/µs, VDD=20 V, Tj=150 °C (see Figure 7) 25 17.5 1.4 ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/10 Test circuit STL15N3LLH5 3 Test circuit Figure 2. Switching times test circuit for resistive load Figure 4. Test circuit for inductive load Figure 5. switching and diode recovery times Unclamped inductive load test circuit Figure 6. Unclamped inductive waveform Switching time waveform 6/10 Figure 3. Figure 7. Gate charge test circuit STL15N3LLH5 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 7/10 Package mechanical data STL15N3LLH5 PowerFLAT™ ( 3.3 x 3.3) mechanical data mm inch Dim Min A 0.950 A3 Max Min 1.000 0.037 0.200 Typ Max 0.039 0.008 b 0.29 0.34 0.39 0.011 0.013 0.015 D 3.200 3.300 3.400 0.126 0.123 0.134 D2 2.24 2.29 2.34 0.088 0.090 0.092 E 2.20 3.30 3.40 0.086 0.123 0.1338 E2 1.660 1.710 1.760 0.065 0.067 0.069 e 0.650 0.025 L 0.40 0.0157 L1 8/10 Typ 0.45 0.50 0.55 0.017 0.0196 0.021 STL15N3LLH5 5 Revision history Revision history Table 8. Document revision history Date Revision 25-Aug-2008 1 Changes First release 9/10 STL15N3LLH5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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