STMICROELECTRONICS STL70N4LLF5

STL70N4LLF5
N-channel 40 V, 0.0055 Ω, 18 A, PowerFLAT™ (6x5)
STripFET™ V Power MOSFET
Preliminary Data
Features
Type
VDSS
RDS(on)
max
ID
STL70N4LLF5
40 V
0.0065 Ω
18 A (1)
1. The value is rated according Rthj-pcb
■
RDS(on) * Qg industry benchmark
■
Extremely low on-resistance RDS(on)
■
High avalanche ruggedness
■
Low gate drive power losses
PowerFLAT™ ( 6x5 )
Application
■
Switching applications
Figure 1.
Description
Internal schematic diagram
This product utilizes the 5th generation of design
rules of ST’s proprietary STripFET™ technology.
The lowest available RDS(on)*Qg, in this chip scale
package, makes this device suitable for the most
demanding DC-DC converter applications, where
high power density is to be achieved.
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL70N4LLF5
70N4LLF5
PowerFLAT™ (6x5)
Tape and reel
December 2008
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/10
www.st.com
10
Contents
STL70N4LLF5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2/10
.............................................. 6
STL70N4LLF5
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
40
V
± 22
V
VDS
Drain-source voltage (VGS = 0)
VGS
Gate-source voltage
ID(1)
Drain current (continuous) at TC = 25 °C
70
A
ID (1)
Drain current (continuous) at TC = 100 °C
44
A
ID(2)
Drain current (continuous) at TC = 25 °C
18
A
(3)
Drain current (continuous) at TC=100 °C
11.5
A
(3)
Drain current (pulsed)
72
A
PTOT (1)
Total dissipation at TC = 25 °C
60
W
(2)
Total dissipation at TC = 25 °C
4
W
0.03
W/°C
-55 to 150
°C
ID
IDM
PTOT
Derating factor
TJ
Operating junction temperature
Storage temperature
Tstg
1. The value is rated according Rthj-c
2. The value is rated according Rthj-pcb
3. Pulse width limited by safe operating area
Table 3.
Thermal resistance
Symbol
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case (drain) (steady state)
2.08
°C/W
Thermal resistance junction-ambient
31.3
°C/W
Value
Unit
Rthj-pcb
(1)
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Table 4.
Symbol
Avalanche data
Parameter
IAV
Not-repetitive avalanche current,
(pulse width limited by Tj Max)
TBD
A
EAS
Single pulse avalanche energy
(starting TJ = 25 °C, ID = IAV , VDD = 24 V)
TBD
mJ
3/10
Electrical characteristics
2
STL70N4LLF5
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5.
Symbol
V(BR)DSS
Parameter
Drain-source breakdown
voltage
Test conditions
ID = 250 µA, VGS= 0
Zero gate voltage drain
current (VGS = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±22 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 9 A
Symbol
Ciss
Coss
Crss
Qg
Typ.
Max.
40
V
VDS = Max rating @125 °C
1
10
µA
µA
±100
nA
1
VGS= 4.5 V, ID= 9 A
Unit
V
0.0055
TBD
0.0065
0.009
Typ.
Max.
Ω
Ω
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
RG
Gate input resistance
Qgs
Min.
VDS = Max rating,
IDSS
Table 6.
4/10
On/off states
Test conditions
VDS = 25 V, f=1 MHz,
VGS=0
VDD=15 V, ID = 18 A
VGS = 4.5 V
(see Figure 3)
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
Min.
Unit
1800
270
40
pF
pF
pF
13
TBD
TBD
nC
nC
nC
TBD
Ω
STL70N4LLF5
Electrical characteristics
Table 7.
Symbol
td(on)
tr
td(off)
tf
Table 8.
Symbol
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
Typ.
Max.
TBD
TBD
TBD
TBD
VDD=15 V, ID= 9A,
RG=4.7 Ω, VGS=10 V
(see Figure 2)
Unit
ns
ns
ns
ns
Source drain diode
Max
Unit
Source-drain current
18
A
ISDM(1)
Source-drain current (pulsed)
72
A
VSD(2)
Forward on voltage
ISD = 18A, VGS=0
1.1
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 18A,
ISD
trr
Qrr
IRRM
Parameter
Test conditions
di/dt = 100 A/µs,
VDD= 25 V
Min
Typ.
TBD
TBD
TBD
ns
nC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
5/10
Test circuits
STL70N4LLF5
3
Test circuits
Figure 2.
Switching times test circuit for
resistive load
Figure 4.
Test circuit for inductive load
Figure 5.
switching and diode recovery times
Unclamped inductive load test
circuit
Figure 6.
Unclamped inductive waveform
Switching time waveform
6/10
Figure 3.
Figure 7.
Gate charge test circuit
STL70N4LLF5
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
7/10
Package mechanical data
STL70N4LLF5
PowerFLAT™(6x5) mechanical data
mm.
DIM.
Min.
A
Min.
0.031
0.83
0.93
0.02
0.05
A3
0.20
0.35
D
D2
0.40
0.47
0.013
4.20
0.32
0.036
0.0007
0.0019
0.015
0.163
0.165
E
6.00
0.236
5.75
0.226
E2
3.43
3.48
3.53
E4
2.58
2.63
2.68
0.70
0.80
L
0.018
0.187
4.25
E1
e
Max.
0.196
4.75
4.15
Typ.
0.007
5.00
D1
8/10
inch
Max.
A1
b
0.80
Typ.
0.135
1.27
0.167
0.137
0.139
0.103
0.105
0.050
0.90
0.027
0.031
0.035
STL70N4LLF5
5
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
01-Dec-2008
1
Changes
First release
9/10
STL70N4LLF5
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