IXLD02SI Differential 2A Ultra Fast Laser Diode Driver Features General Description • • • • • • • The IXLD02 is an ultra high-speed differential laser diode driver. The IXLD02 is designed specifically to drive single junction laser diodes in a differential fashion. A Q output and a Q-Bar output are provided via a low inductance multi-pin topology. These two signals make their transitions at the same time with transition times in the picoseconds. This technique provides the highest possible slew rate across the diode. In addition the IXLD02 is capable of currents exceeding 2A. Ultra Fast Pulsed Current Source High Output Currents >2A Peak 17MHz Max Operating Frequency <1.5ns Minimum Pulse Width 600ps Rise And Fall Times Pulse Width and Frequency Agile Real Time Electronic Programming of Current and Pulse Width • Low Inductance High Power Package Design • Simultaneous Frequency, Pulse Width and Amplitude Modulation Applications • • • • • High Speed Laser Diode Drivers High Power Ultra Fast Line Drivers Differential Power Drivers High Power Pulse Generators High Speed High Frequency Modulators These performance features are combined with frequency agility to a maximum operating frequency of 17MHz, a minimum pulse width of <1.5ns and rise and fall times of approximately 600ps. In addition, the pulse width and the current programming can be modulated in real time to >10MHz. The IXLD02 is assembled in a high power SO-28 surface mount package. For additional operational instructions, see the IXLD02 Evaluation Board application note on the DEI web site at www.directedenergy.com Figure 1 - Functional Diagram Copyright © Directed Energy, Inc. 2002, 2003 First Release IXLD02SI Absolute Maximum Ratings (Note 1) Name VDD Definition Logic supply input voltage Min -0.4 VDDA Analog bias supply input voltage -0.4 VTT IBI VIBI Internal bias voltage input Internal bias current input Applied IBI terminal voltage Pulse width programming current input -0.4 -10 -0.4 Max 5.5 Units V 5.5 V VDDA/2 0.1 VDDA+.5 10 VDDin+0.5 V mA V -10 0.1 10 mA VIPW Applied IPW terminal voltage -0.4 VDDin+0.5 V IOP Output current programming input -10 10 mA VIOP Applied IOP terminal voltage -0.4 VDDin+0.5 V VPDN Power-down logic input -0.4 VDDin+0.5 V VRST Reset logic input -0.4 VDDin+0.5 V VFIN Pulse frequency logic input -0.4 VDDin+0.5 V VOUT Pulse current true output -0.1 3 Amps VOUT OUT terminal voltage -0.4 9 V OUTB Pulse current complement output -0.1 3 Amps VOUTB OUTB terminal voltage -0.4 9 V IPW Typ -40 1 TC Device Case Temperature PD Package power dissipation @ TC=85C 32 RTHJC Thermal resistance, junction to case 2 TJ Junction Temperature 150 o 150 o 300 o TS Storage temperature -55 TL Lead temperature (soldering, 10 sec) 25 o 85 C Watts Test Conditions Measured at the bottom of the SO28 package heat slug insert. SO28 package heat slug insert o held at TC=85 C. o C/W C C C Note 1: Operating the device beyond parameters with listed “Absolute Maximum Ratings” may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component. Ordering Information Part Number IXLD02SI 2 Package Type 28-Pin SOIC Temp. Range -40°C to +85°C Grade Industrial IXLD02SI Recommended Operating Conditions Unless otherwise noted, VDD=VDDA=5V, TC=25C Name Typ Max VDD VDDA VTT RVTT Logic supply input voltage Analog bias supply input voltage Internal bias voltage input VTT terminal resistance 4.5 4.5 2 30 VDDA/2 50 5.5 5.5 3 70 IIBI Internal bias current input range 10 100 300 uA VIBI Measured IBI terminal voltage 0.6 1.7 V IIPW Pulse width programming current input range. Measured IPW terminal voltage -1 400 uA 1.7 V 3 ns mA 1.7 V IIBI=400uA, IIPW=300uA, IIOP=1mA. External current source between VDDA and IBI terminals. IBI=100uA. 2200 I/I IIOP=1mA, VOUT=VOUTB=10V. VIPW tPW IIOP VIOP Definition IOUT=2A peak, Output current pulse width OUT and OUTB output current, IOUT, programming current. Measured IOP terminal voltage IOUT/IIOP Output current to programming current gain VIH VIL ILIN tPDN tRST tFIN fFINmax IOUT tR tF TONDLY TOFFDLY PWmax Tj VOUT Logic input high threshold for PDN, RST, & FIN inputs. Logic input high threshold for PDN, RST, & FIN inputs. Logic input bias current for PDN, RST, & FIN inputs. Min 100 0.6 1 1 0 0.6 1800 2000 0.7*VDD Units -10 .3*VDD V 10 uA 50 ns 30 ns IXLD02 reset logic delay, VRST logical low to high transition. IXLD02 reset logic delay, VRST logical low to high transition. IXLD02 pulse frequency input, VFIN, logical low to high transition to IOUT pulse delay. Maximum pulse frequency, FIN, logic input. 100 ns 100 ns 50 ns 17 Peak true pulse current output. 1.6 2 600 600 On-time propagation delay Off-time propagation delay Pulse width maximum Jitter 30 30 >1 <300 8 0 VOUTB OUTB terminal voltage 8 External current source between VDDA and IPW terminal. IIPW=100uA. For logic inputs, PDN, RST, & FIN held at:-0.5V<VLIN<VDD IIBI=400uA, IIPW=300uA, IIOP=1mA.. MHz IIBI=400uA, IIPW=300uA, IIOP=1mA.. Rise time Fall time IOUTB Minimum complement pulse current output. External current source between VDDA and IBI terminal. IIBI=100uA. V IXLD02 power down delay, VPDN logical low to high transition. IXLD02 power up delay, VPDN logical high to low transition. OUT terminal voltage Test Conditions V V V Measured with Zin>10meg DVM. Kohms Measured with VDDin=VDDA=0V. 2.4 ns ns us ps 12 0.2 0.4 12 3 Amps IIBI=400uA, IIPW=300uA, IIOP=1mA., VOUT=VOUTB=10V. ps ps V IIBI=400uA, IIPW=300uA, IIOP=1mA, 1.4A<IOUT<2.6A peak. Amps IIBI=400uA, IIPW=300uA, IIOP=1mA., VOUT=VOUTB=10V. V IIBI=400uA, IIPW=300uA, IIOP=1mA, 0A<IOUT<0.6A minimum. IXLD02SI Pin Configurations And Package Outline NOTE: Bottom-side heat sinking metalization is connected to ground Pin Description P in s Nam e D e s c rip tio n 1 ,2 , 13, 14 VDD T h is p in is a hig h c u rren t, lo w in d u cta nc e pin de s ig n ed to a cce p t p ea ks of 2Am ps at 5V. 3 VDDA T h is is a lo w c u rre n t a n a lo g pow e r in p u t. C irc u it c om p on e n ts s e ns itive to th e n o is e p re se n t o n V D D in a re su p plied b y th is pin . 4 VTT 5 T h is p in is th e 1 /2 V D D A in te rna l a na log c om p a ra to r re fe re n ce p o in t. L o w c u rre n t, lo w n o ise a na log re tu rn . N o ise se ns itive c irc u it GNDA c o m p o n en ts a re re tu rne d h e re. T h e c u rre n t, I IB I , flo w in g into the IB I pin ac ts a s a ba s eline c urre n t w ith re s p ec t to I IPW c u rre n t to c o m pe n s ate fo r in te rn al d ela ys . S e e F ig u re 2 . 6 IB I 7 IO P A c u rren t, I IO P , in to th e IO P p in p ro g ram s th e las e r dio d e o u tpu t s w itc h e s, p in 1 9 th rou g h p in 24 . T h e p rog ra m ra tio is 1 :1 0 00 X . T h is m e a ns a 1 m A c u rre n t w ill p ro du c e 1 A m p . S e e F ig u re 2 . 8 IPW A c u rren t, I IPW , flo w in g into the IPW p in d e te rm in es the o u tp ut c u rren t p u lse w id th , t PW , w ith res p e c t to I IB I . If I IPW = I IB I , th e p u ls e w id th is 0 . A s I IPW a pp ro ac h es I IB I b u t le ss tha n I IB I , th e pu lse w id th b ec om es n on ze ro . S e e F ig u re 2 fo r t PW a s a fu nc tion o f I IB I a nd I IPW . 9 PDN A T T L h ig h o n this p in w ill p o w e r d o w n th e de vic e s o th a t o n ly le a k ag e c u rre nt w ill flo w fro m V D D to D G N D . A T T L lo w w ill tu rn o n th e d e vic e w ith in 3 0 n s . S ee F ig u re 3 . 10 RST A s ys tem res e t pin , w h ich in itia lize s th e d e vic e s o th a t it s ta rts in a p re d e te rm in e d in itial s ta te . 11 12 T h is p in is th e re tu rn fo r th e inp u t lo g ic , I IB I , I IO P , a n d I IPW c u rre n ts . It is D G N D in te rna lly co n ne c te d to th e o the r g ro un d s, A G N D o r G N D , th ro u g h th e s u bs tra te . W ith P D N lo w , a p o sitive ed g e o f a T T L c o m p a tib le s ig n a l h ere w ill p ro d uc e th e pu lse cu rre n t o u tpu t a va ila b le a t th e O U T a n d a F IN c o m p lem e n t o f it a t O U T b p in s. R e fe r to F ig u re 3 fo r F IN a nd P D N tim in g . 1 5 , 1 6, 1 7 , 1 8, 2 5 , 2 6, 27, 28 G N D O u tp u t g ro u n d p in s de sig n e d fo r lo w in d uc tan c e . 1 9 , 2 0. 21 OUT T ru e la s e r d iod e d rive o u tp u t cu rre n t. D e s ig n ed fo r lo w in d ucta n ce a nd o u tp u t vo lta ge co m p lian ce to + 1 2 V . C o m p le m en ta ry las e r d iod e d rive o u tp u t c u rre n t. D e sig n ed fo r lo w 2 2 , 2 3, O U Tb in d uc ta nc e a n d o u tpu t vo lta g e c o m p lia n ce to + 1 2 V . 24 4 IXLD02SI Figure 2 - Programmed IOUT pulse width, tPW as a function of IIPW and IIBI Figure 2 is an illustration of the pulse width vs. programming current. The programming current is typically a DC level, however it could just as well be a time varying signal. The bandwidth of this portion of the IXLD02 is equivalent to the maximum operating frequency of 17MHz. For the fastest response time this pin should be driven from a low source impedance. Figure 3 - Control Gate Timing Diagram Figure 3 is a timing chart for the IXLD02. The proper gating of the IXLD02 is extremely important. The device is capable of 2A of current and may consume in excess of 3A during the pulse. If the supply voltage is at 7V with 3A of current, the total power dissipated is 21W. Therefore ample heat sinking must be provided, and/or the duty cycle must be limited so that the power dissipation capability of the device is not exceeded. The Power Up Gate (PDN) is applied to activate the device. Time interval “A” can be >30ns. At the end of this time period the control gate “B” (FIN), can be applied. The range of “B” is from 1ns to several µs. The maximum frequency 1/C is approximately 17MHz. 5 IXLD02SI Figure 4 - Duty Cycle Figure 4 illustrates the Duty Cycle (DC), FIN and PDN relation ships. The PDN command must be in a TTL “High” state 30ns prior to the first FIN pulse. It must stay in this state for the duration of the laser light burst, T1 to T2. The Duty cycle is defined as: Power in the IC is: DC = T 2 − T1 T 3 − T1 Total dc Power X DC Figure 5 - IPW And IOP Modulation Figure 5 illustrates the simultaneous modulation of both the IPW control current and the IOP control current. The FIN frequency in this figure is held constant. At T0 the IPW and the IOP signals are near zero, both begin to ramp up at T1 and reach their maximums at T2. As illustrated, the output current rises in amplitude with the increasing IOP and the pulse width widens with the IPW ramp. An additional mode of modulation can be added to the two above by also modulating the frequency of the FIN signal. This will allow three mode of simultaneous modulation. The three modes do not have to be used together; each is fully independent. The obvious caveat is that the pulse width must be consistent with the chosen frequency. This agility provides the designer with a broad range of design choices. Directed Energy, Inc. An IXYS Company 2401 Research Blvd. Ste. 108 Ft. Collins, CO 80526 Tel: 970-493-1901; Fax: 970-493-1903 e-mail: [email protected] www.directedenergy.com Doc #9200-0258 Rev 2 6