Eon Silicon Solution Inc. Application Note EON EN25QH256 (Version : Preliminary 0.2) vs MXIC MX25L25635E (Version : 1.0) Specification Comparison This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 1 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 1. INTRODUCTION The application note introduces how to implement a system design from MXIC MX25L25635E Flash to Eon EN25QH256 Flash. 2. GENERAL FUNCTION COMPARISON TABLE: 2-1 The following table highlights the major features of these two devices. Features Voltage range Pin to pin compatible (standard SPI mode) SPI frequency Secured silicon sector region Sector architecture SPI mode EQIO mode (Full quad mode) Page program Continuous program Block erase 64K byte Block erase 32K byte Sector erase 4K byte 4-byte address mode Advanced individual block protect High bank latch mode SFDP information Minimum endurance cycle Package EN25QH256 MX25L25635E 2.7 ~ 3.6V 16-pins SOP 300mil (except pin 3,4, 5, 6, 11, 12, 13, 14 = NC) 8 contact VDFN (except 7 = Hold#(DQ3)) 104MHz (standard mode) 80MHz @ Dual & Quad mode 2.7 ~ 3.6V 16-pins SOP 300mil (except pin 3 = Reset#, 4, 5, 6, 11, 12, 13, 14 = NC) 8 WSON (except 7 = Reset#(SIO3)) 80MHz (standard mode) 70MHz @ Dual & Quad mode 512 Byte 512 Byte Uniform 8192 sectors of 4K byte 512 blocks of 64K byte Mode 0 / Mode 3 Uniform 8192 sectors of 4K byte 1024 blocks of 32K byte 512 blocks of 64K byte Mode 0 / Mode 3 Yes No Yes Yes No Yes Yes Yes No Yes Yes Yes Yes Yes No Yes Yes No Yes No 100K 100K 8 contact VDFN (6 x 8 mm) 16 pins SOP 300mil 24 balls BGA (6 x 8 mm) 8 WSON (8 x 6 mm) 16-pins SOP 300mil This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 2 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 3. HARDWARE CONSIDERATIONS 3-1 ICC comparison Current (Max) EN25QH256 MX25L25635E Unit Read ICC3 45 @ 80MHz 40 @ 70MHz 25 mA Page Program (PP) ICC4 25 @ 100MHz 20 @ 80MHz 28 Sector Erase (SE) ICC6 25 25 mA Standby ICC1 20 200 A 3-2 mA Pin configuration (16-pin package) Pin number Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin 16 EN25QH256 HOLD# (DQ3) VCC NC NC NC NC CS# DO (DQ1) WP# (DQ2) VSS NC NC NC NC DI (DQ0) CLK MX25L25635E HOLD# / SIO3 VCC Reset# NC NC NC CS# SO / SIO1 / WP# / SIO2 GND NC NC NC NC SI / SIO0 SCLK Note: 1. The HOLD# (DQ3) pin of Eon EN25QH256 Flash doesn’t have an internal weak pull up on the pin. This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 3 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 4. SOFTWARE CONSIDERATIONS 4-1 Manufacturer, Memory Type & Device Identification comparison (M7~M0: manufacture ID, D15~ID0: memory type, ID7~ID0: memory density) EN25QH256: OP Code (M7-M0) (ID15-ID0) ABh (ID7-ID0) 18h 90h 1Ch 9Fh 1Ch 18h 7019h MX25L25635E: This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 4 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 4-2 Instruction Set Comparison 4-2.1 Different block protection area EN25QH256: Status Register Content BP3 Bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 Bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 Bit 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Memory Content Protect Areas Addresses None Block 0 to 510 Block 0 to 509 Block 0 to 507 Block 0 to 503 Block 0 to 495 Block 0 to 479 All None Block 511 to 1 Block 511 to 2 Block 511 to 4 Block 511 to 8 Block 511 to 16 Block 511 to 32 All None 0000000h-1FEFFFFh 0000000h-1FDFFFFh 0000000h-1FBFFFFh 0000000h-1F7FFFFh 0000000h-1EFFFFFh 0000000h-1DFFFFFh 0000000h-1FFFFFFh None 1FFFFFFh-0010000h 1FFFFFFh-0020000h 1FFFFFFh-0040000h 1FFFFFFh-0080000h 1FFFFFFh-0100000h 1FFFFFFh-0200000h 1FFFFFFh-0000000h Density(KB) None 32704KB 32640KB 32512KB 32256KB 31744KB 30720KB 32768KB None 32704KB 32640KB 32512KB 32256KB 31744KB 30720KB 32768KB Portion None Lower 511/512 Lower 510/512 Lower 508/512 Lower 504/512 Lower 496/512 Lower 480/512 All None Upper 511/512 Upper 510/512 Upper 508/512 Upper 504/512 Upper 496/512 Upper 480/512 All MX25L25635E: This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 5 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 4-2.2 Different RDSR bit definition EN25QH256: S7 SRP Status Register Protect 1 = status register write disable S6 OTP_LOCK QE (Quad Enable) bit (note 1) 1 = Quad enable 0 = not Quad enable 1 = OTP sector is protected Non-volatile bit S5 S4 S3 S2 S1 S0 BP3 BP2 BP1 BP0 WEL (note 2) (note 2) (note 2) (note 2) 1 = write enable 0 = not write enable 1 = write operation 0 = not in write operation volatile bit volatile bit (Block (Block (Block (Block (Write Enable Protected bits) Protected bits) Protected bits) Protected bits) Latch) Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit WIP (Write In Progress bit) (Note 3) Note 1. In OTP mode, SRP bit is served as OTP_LOCK bit. 2. See the table “Protected Area Sizes Sector Organization”. 3. When executed the (RDSR) (05h) command, the OTP_LOCK bit (S7 / in OTP mode) value is the same as OTP_LOCK bit (S2) in Security Register table. MX25L25635E: Bit 7 is only used for SRWD (status register write protect). This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 6 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 4-2.3 Security / Information Register definition EN25QH256: S0, S3, and S4 are reserved. S7 HBL (High Bank Latch bit) 1 = access larger than 128Mb 0 = access smaller than 128Mb (default = 0) volatile bit Read Only S6 S5 S4 S3 Erase Fail Flag Program Fail Flag S2 S1 S0 4 BYTE OTP_LOCK bit 1 = indicate 1 = indicate 1 = 4-byte Reserved bit Erase failed Program failed Reserved bit Reserved bit address mode 1 = OTP sector 0 = normal 0 = normal 0 = 3-byte is protected Erase succeed Program succeed address mode (default = 0) (default = 0) (default = 0) volatile bit volatile bit volatile bit non-volatile bit Read Only Read Only Read Only Read Only Note: 1. When executed the (RDIFR) (2Bh) command, the OTP_LOCK bit (S1) value is the same as OTP_LOCK bit (S7 / in OTP mode) in table 6. 2. Default at Power-up is “0” MX25L25635E: Bit 0 is used for 4K-bit Secured OTP Bit 1 is used for LDSO (lock-down 4K-bit Secured OTP), can be changed by writing WRSCUR instruction. Bit 4 is used for Continuously Program mode Bit 7 is used for WPSEL This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 7 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 4-2.4 EQIO mode (Enable Quad I/O) (38h) EN25QH256: This command will enable device enter Full Quad mode. MX25L25635E: Only support the page program under Quad mode. 4-2.5 Enter Secured OTP command EN25QH256: Support. (3Ah) MX25L25635E: Support. (B1h) 4-2.6 Exit Secured OTP command EN25QH256: Support. (04h) MX25L25635E: Support. (C1h) 4-2.7 Secured OTP Addresses EN25QH256: Sector Size Address Range 512 byte xxx000h – xxx1FFh MX25L25635E: This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 8 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 4-2.8 The other instructions comparison Instructions Command EN25QH256 MX25L25635E RSTQIO (Reset Quad I/O) RSTEN (Reset Enable) RST (Reset) BE 32K (block erase 32KB) CP (Continuously Program mode) REMS2 (Read ID for 2x I/O mode) REMS4 (Read ID for 4x I/O mode) WRSCUR (Write Security register) ESRY (Enable SO to output RY/BY#) DSRY (Disable SO to output RY/BY#) CLSR (Clear SR Fail Flags) HPM (High Performance Enable Mode) WPSEL (write protection selection) SBLK (single block lock) SBULK (single block unlock) RDBLOCK (block protect read) GBLK (gang block lock) GBULK (gang block unlock) FFh 66h 99h 52h Yes Yes Yes No No No No Yes ADh No Yes EFh No Yes DFh No Yes 2Fh No Yes 70h No Yes 80h No Yes 30h No Yes A3h No Yes 68h No Yes 36h No Yes 39h No Yes 3Ch No Yes 7Eh No Yes 98h No Yes This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 9 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 5. Introduction to high bank latch mode EN25QH256 can support both high bank latch mode and 4-byte address mode while MX25L25635E can only support 4-byte address mode. The High Bank Latch mode (ENHBL) instruction enables the first byte addresses was accessed at the memory area of higher bank (larger than 128Mb) while execute the read / program / erase command, that means the address 24-bit was asserted high after entering this mode. In other words, for read / program / erase command the Host system can also access the addresses from 1000000h to 1FFFFFF even if without inputting 4 byte address. The device default is in the memory area of lower bank (smaller than 128M); after sending out the ENHBL instruction, the bit 7 (HBL bit) of Information register will be automatically set to “1” to indicate the High Bank Latch has been enabled. Once the High Bank Latch mode is enable, if execute read / program / erase command, then the first byte addresses will be accessed at memory area of the higher bank (larger than 128Mb) instead of the default the memory area lower bank (smaller than 128M). There are some methods that can exit the High Bank Latch mode: power-off, or by writing Reset Quad I/O (RSTQIO), Enter 4-byte mode (EN4B) and Exit High Bank Latch mode (EXHBL) instructions. The sequence of issuing ENHBL instruction is: CS# goes low -> sending ENHBL instruction to enter High Bank Latch mode (automatically set HBL bit as “1”) -> CS# goes high, as shown in figure as below. This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 10 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. 6. PERFORMANCE DIFFERENCES 6-1 Erase and program performance EN25QH256 Parameter MX25L25635E Unit Typ Max Typ Max Page Programming Time 0.6 2.5 1.4 5 ms Sector Erase Time 50 250 60 300 ms Block Erase Time (32KB) N/A N/A 0.5 2 sec Block Erase Time (64KB) 0.2 1.6 0.7 2 sec Chip (Bulk) Erase Time 100 200 160 400 sec 6-2 Key AC parameter PERFORMANCE EN25QH256 MX25L25635E tCH (serial clock high time) Min @ 4ns Min @ 5.5ns tCL (serial clock low time) Min @ 4ns Min @ 5.5ns tCLCH(serial clock rise time) Min @ 0.1V / ns Min @ 0.1V / ns tCLCL(serial clock fall time) Min @ 0.1V / ns Min @ 0.1V / ns Min@ 5ns Min @ 5ns Min, read @15ns Min, read @15ns Program/Erase @50ns Program/Erase @100ns tDSU(Data in setup time) Min @ 2ns Min @ 2ns tDH(Data in hold time) Min @ 5ns Min @ 5ns Parameter tCHSH(CS# active setup / hold time) tSHSL(CS# high time) This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com Eon Silicon Solution Inc. Revisions List Revision No Description A B Date Initial Release 2010/02/12 Update comparison of latest datasheet version (Eon from 2010/10/01 Preliminary 0.0 to Preliminary 0.2, MXIC from 0.02 to 1.0) This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 12 ©2005 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/ 02/12 www.eonssi.com