ESD200-B1-CSP0201 Data Sheet (1.1 MB, EN)

Protection Device
TVS (Transient Voltage Suppressor)
ESD200-B1-CSP0201
Bi-directional, 5.5 V, 6.5 pF, 0201, RoHS and Halogen Free compliant
ESD200-B1-CSP0201
Data Sheet
Revision 1.2, 2016-04-21
Final
Power Management & Multimarket
Edition 2016-04-21
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD200-B1-CSP0201
Product Overview
1
Product Overview
1.1
Features
•
ESD / transient protection of data lines according to:
– IEC61000-4-2 (ESD): ±19 kV (air), ±17 kV (contact discharge)
– IEC61000-4-4 (EFT): ±2 kV / ±40 A (5/50 ns)
– IEC61000-4-5 (surge): ±3 A (8/20 µs)
Bi-directional working voltage up to: VRWM = ±5.5 V
Line capacitance: CL = 6.5 pF (typical) at f = 1 MHz
Clamping voltage: VCL = 13 V (typical) at ITLP = 16 A with RDYN = 0.2 Ω (typical)
Very low reverse current: IR < 1 nA (typical)
Minimized clamping overshoot due to extremely low parasitic inductance
Small form factor SMD Size 0201 and low profile (0.58 mm x 0.28 mm x 0.15 mm)
Bidirectional and symmetric I/V characteristics for optimized design and assembly
Pb-free (RoHS compliant) and halogen free package
•
•
•
•
•
•
•
•
Guidelines for optimized PCB design and assembly process available [2]
1.2
•
•
Application Examples
ESD Protection of highly susceptible IC/ASICs in audio, headset, human digital interfaces
Dedicated solution to boost space saving and high performance in miniaturized modern electronics
1.3
Product Description
a) Pin configuration top view
b) Schematic diagram
Configuration _Schematic_Diagram.vst.vsd
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1
Part Information
Type
Package
Configuration
Marking code
ESD200-B1-CSP0201
WLL-2-1
1 line, bi-directional
A1)
1) The device does not have any marking or date code on the device backside. The Marking code is on pad side.
Final Data Sheet
3
Revision 1.2, 2016-04-21
ESD200-B1-CSP0201
Maximum Ratings
2
Maximum Ratings
Table 2-1
Maximum Ratings at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
Reverse working voltage
ESD discharge
contact
air
Values
±5.5
VRWM
2)
Unit
V
kV
VESD
±17
±19
Peak pulse power3)
PPK
45
W
Peak pulse current
IPP
±3
A
Operating temperature range
TOP
-55 to 125
°C
Storage temperature
Tstg
-65 to 150
°C
3)
1) Device is electrically symmetrical
2) VESD according to IEC61000-4-2 (R = 330 Ω, C = 150 pF discharge network)
3) Stress pulse: 8/20μs current waveform according to IEC61000-4-55
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Figure 3-1 Definitions of electrical characteristics
Final Data Sheet
4
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ESD200-B1-CSP0201
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Table 3-1
DC Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Breakdown voltage
VBR
6
-
10
V
IBR = 1 mA
Reverse current
IR
-
0.1
100
nA
VR = 5.5 V
Unit
Note / Test Condition
pF
VR = 0 V, f = 1 MHz
1) Device is electrically symmetrical
Table 3-2
AC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Line capacitance
Table 3-3
CL
Values
Min.
Typ.
Max.
-
6.5
-
-
6.5
-
VR = 0 V, f = 1 GHz
ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
2)
Clamping voltage
VCL
Values
Min.
Typ.
Max.
-
12
-
Unit
Note / Test Condition
V
VESD = 8 kV
contact discharge
3)
Clamping voltage
-
10
13
-
ITLP = 1 A, tp = 100 ns
ITLP = 16 A, tp = 100 ns
Clamping voltage4)
-
10
12.5
-
IPP = 1 A, tp = 8/20 µs
IPP = 3 A, tp = 8/20 µs
-
0.2
-
Dynamic resistance3)
1)
2)
3)
4)
RDYN
Ω
tp = 100 ns
Device is electrically symmetrical
VESD according to IEC61000-4-2 (R = 330 Ω, C = 150 pF discharge network)
Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 0.6 ns
Stress pulse: 8/20μs current waveform according to IEC61000-4-5
Final Data Sheet
5
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ESD200-B1-CSP0201
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical characteristics diagram at TA = 25 °C, unless otherwise specified
-3
10
-4
10
10-5
-6
IR [A]
10
10-7
-8
10
-9
10
10-10
-11
10
-12
10
-10
-8
-6
-4
-2
0
VR [V]
2
4
6
8
10
Figure 4-1 Reverse leakage current: IR = f(VR)
IR [nA]
10+1
10
+0
-1
10
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90 100 110 120 130
TA [°C]
Figure 4-2 Reverse current: IR = f(TA), VR = 5.5 V
Final Data Sheet
6
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ESD200-B1-CSP0201
Typical Characteristics Diagrams
9
8.9
8.8
VBR [V]
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90 100 110 120 130
TA [°C]
Figure 4-3 Reverse voltage: VBR = f(TA), IR = 1 mA
10
9
8
CL [pF]
7
1 MHz
6
1 GHz
5
4
3
2
1
0
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
VR [V]
1
1.5
2
2.5
3
Figure 4-4 Line capacitance: CL = f(VR)
Final Data Sheet
7
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ESD200-B1-CSP0201
Typical Characteristics Diagrams
50
Scope: 6 GHz, 20 GS/s
45
VCL [V]
40
35
VCL-max-peak = 25 V
30
VCL-30ns-peak = 12 V
25
20
15
10
5
0
-5
-100
0
100
200
300
400
tp [ns]
500
600
700
800
900
Figure 4-5 Clamping voltage (ESD): VCL = f(t), 8 kV positive pulse
5
0
-5
-10
VCL [V]
-15
-20
-25
-30
VCL-max-peak = -24 V
-35
VCL-30ns-peak = -11 V
-40
-45
-50
-100
Scope: 6 GHz, 20 GS/s
0
100
200
300
400
tp [ns]
500
600
700
800
900
Figure 4-6 Clamping voltage (ESD): VCL = f(t), 8 kV negative pulse
Final Data Sheet
8
Revision 1.2, 2016-04-21
ESD200-B1-CSP0201
Typical Characteristics Diagrams
50
Scope: 6 GHz, 20 GS/s
45
VCL [V]
40
35
VCL-max-peak = 34 V
30
VCL-30ns-peak = 13 V
25
20
15
10
5
0
-5
-100
0
100
200
300
400
tp [ns]
500
600
700
800
900
Figure 4-7 Clamping voltage (ESD): VCL = f(t), 15 kV positiv pulse from pin 1 to pin 2
5
0
-5
-10
VCL [V]
-15
-20
-25
-30
VCL-max-peak = -35 V
-35
VCL-30ns-peak = -12 V
-40
-45
-50
-100
Scope: 6 GHz, 20 GS/s
0
100
200
300
400
tp [ns]
500
600
700
800
900
Figure 4-8 Clamping voltage (ESD): VCL = f(t), 15 kV negative pulse
Final Data Sheet
9
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ESD200-B1-CSP0201
Typical Characteristics Diagrams
30
15
ESD200-B1-CSP0201
RDYN
25
12.5
20
10
15
7.5
RDYN = 0.20 Ω
5
5
2.5
0
0
-5
-2.5
-10
Equivalent VIEC [kV]
ITLP [A]
10
-5
RDYN = 0.20 Ω
-15
-7.5
-20
-10
-25
-12.5
-30
-20
-15
-10
-5
0
5
10
15
-15
20
VTLP [V]
Figure 4-9 Clamping voltage (TLP): ITLP = f(VTLP) [1]
Final Data Sheet
10
Revision 1.2, 2016-04-21
ESD200-B1-CSP0201
Typical Characteristics Diagrams
5
4
3
2
IPP [A]
1
0
-1
-2
-3
-4
-5
-20
-15
-10
-5
0
VCL [V]
5
10
15
20
Figure 4-10 Clamping voltage (Surge): IPP = f(VCL) [1]
Final Data Sheet
11
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ESD200-B1-CSP0201
Typical Characteristics Diagrams
0
Insertion Loss [dB]
-5
-10
-15
-20
-25
ESD200-B1-CSP0201
-30
-35
10
100
1000
f [MHz]
10000
Figure 4-11 Insertion loss vs. frequency in a 50 Ω system
Final Data Sheet
12
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ESD200-B1-CSP0201
Package
5
Package
Top view
Bottom view
0.15 ±0.01
0.28 ±0.03
0.58 ±0.03
1
0.2 ±0.02
0.36
(0.16)
2
0.26 ±0.02
SG-WLL-2-1-PO V01
Figure 5-1 WLL-2-1 Package outline (dimension in mm)
0.19
0.24
Solder mask
0.19
0.57
0.14
0.62
Copper
0.19
0.27
0.24
0.32
Stencil apertures
Figure 5-2 WLL-2-1 Footprint (dimension in mm) Recommendation for Printed Circuit Board Assembly[2]
8
0.68
0.23
2
0.21
0.35
Deliveries can be in Embossed Tape with or without vacuum hole (no selection possible).
Specification allows identical processing (pick & place) by users.
SG-WLL-2-1-TP V02
Figure 5-3 WLL-2-1 Packing (dimension in mm)
Marking on pad-side
Type code
1
1
1
Type code
1
SG-WLL-2-1-MK V03
Figure 5-4 WLL-2-1 Marking example Table 1-1 “Part Information” on Page 3
Final Data Sheet
13
Revision 1.2, 2016-04-21
ESD200-B1-CSP0201
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendation for Printed Circuit Board Assembly of Infineon WLL Packages
http://www.infineon.com/dgdl/?fileId=db3a304344f7b4f9014503db540027c0 [3]
Infineon AG - Application Note AN392: TVS Diodes in ChipScalePackage reduce size and save cost
Final Data Sheet
14
Revision 1.2, 2016-04-21
ESD200-B1-CSP0201
Revision History: Revision 1.1, 2015-02-03
Page or Item
Subjects (major changes since previous revision)
Revision 1.2, 2016-04-21
All
Update to new Layout
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Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
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Last Trademarks Update 2010-10-26
Final Data Sheet
15
Revision 1.2, 2016-04-21
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Published by Infineon Technologies AG
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