ESD231-B1-W0201 Data Sheet (845 KB, EN)

Protection Device
TVS (Transient Voltage Suppressor)
ESD231-B1-W0201
Bi-directional, 5.5 V, 3.5 pF, 0201, RoHS and Halogen Free compliant
ESD231-B1-W0201
Data Sheet
Revision 1.1, 2015-10-02
Final
Power Management & Multimarket
Edition 2015-10-02
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD231-B1-W0201
Product Overview
1
Product Overview
1.1
Features
•
ESD / transient protection of susceptible I/O lines to:
– IEC61000-4-2 (ESD): ±30 kV (air/contact discharge)
– IEC61000-4-4 (EFT): ±4 kV / ±80 A(5/50 ns)
– IEC61000-4-5 (surge): ±12 A (8/20 µs)
Bi-directional working voltage up to: VRWM = ±5.5 V
Line capacitance: CL = 3.5 pF (typical) at f = 1 MHz
Clamping voltage: VCL = 12 V (typical) at ITLP = 16 A with RDYN = 0.3 Ω (typical)
Very low reverse current. IR < 1 nA (typical)
Minimized clamping overshoot due to extremely low parasitic inductance
Small form factor SMD Size 0201 and low profile (0.58 mm x 0.28 mm x 0.15 mm)
Bidirectional and symmetric I/V characteristics for optimized design and assembly
Pb-free (RoHS compliant) and halogen free package
•
•
•
•
•
•
•
•
Guidelines for optimized PCB design and assembly process available [2]
1.2
•
•
•
•
Application Examples
USB 2.0 HA, MIPI, (µ)SD-card (UHS), SIM-card
Control ports for DVI, HDMI, Display Port, and Thunderbolt
Audio Line, Speaker, Headset, Microphone Protection
Human Interface Devices (Keyboard, Touchpad, Buttons)
1.3
Product Description
a) Pin configuration
b) Schematic diagram
Configutation_Schematic_Diagram.vsd
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1
Part Information
Type
Package
Configuration
Marking code
ESD231-B1-W0201
WLL-2-1
1 line, bi-directional
M1)
1) The device does not have any marking or date code on the device backside. The Marking code is on pad side.
FinalData Sheet
3
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ESD231-B1-W0201
Maximum Ratings
2
Maximum Ratings
Table 2-1
Maximum Rating at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
Values
Unit
VRWM
±5.5
V
ESD air discharge
ESD contact discharge2)
VESD
±30
±30
kV
Peak pulse power3)
PPK
132
W
Peak pulse current
IPP
12
A
Operating temperature
TOP
-55 to 125
°C
Storage temperature
Tstg
-65 to 150
°C
Reverse working voltage
2)
3)
1) Device is electrically symmetrical
2) VESD according to IEC61000-4-2
3) Stress pulse: 8/20μs current waveform according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the component.
Table 2-2
Thermal Resistance
Parameter
Symbol
Values
Min.
1)
Typ.
Unit
Max.
Junction - soldering point
RthJS
30
1) For calculation of RthJA please refer to Application Note [3] 077 Thermal Resistance Calculation.
FinalData Sheet
4
K/W
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ESD231-B1-W0201
Electrical Characteristics at TA = 25 °C, unless otherwise specified
3
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Table 3-1
( )!! %! )*
!
+! )#! % ##%# Figure 3-1 Definitions of electrical characteristics
!"!!""!" #$%"&!'!! DC Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note /
Test Condition
Trigger voltage
Vt1
6.1
9.5
–
V
Holding voltage
Vh
6.1
7.8
12.5
V
IR = 10 mA
Reverse current
IR
–
–
20
nA
VR = 5.5 V
Unit
Note /
Test Condition
pF
VR = 0 V, f = 1 MHz
1) Device is electrically symmetrical
Table 3-2
RF Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Line capacitance
FinalData Sheet
Symbol
CL
Values
Min.
Typ.
Max.
3
3.5
4.1
–
3.2
–
5
VR = 0 V, f = 1 GHz
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ESD231-B1-W0201
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Table 3-3
ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified 1)
Parameter
Symbol
2)
VCL
Clamping voltage
Clamping voltage3)
Dynamic resistance
2)
RDYN
Values
Unit
Note /
Test Condition
V
ITLP = 16 A,
tp = 100 ns
Min.
Typ.
Max.
–
12
–
–
16
–
ITLP = 30 A,
tp = 100 ns
–
8
–
IPP = 2 A, tp = 8/20 µs
–
10
–
IPP = 9 A, tp = 8/20 µs
–
0.3
–
Ω
tp = 100 ns
1) Device is electrically symmetrical
2) Please refer to Application Note AN210[1].TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 0.6 ns.
3) Stress pulse: 8/20μs current waveform according to IEC61000-4-5
FinalData Sheet
6
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ESD231-B1-W0201
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical characteristics diagrams at TA = 25°C, unless otherwise specified
10-6
-7
10
10-8
IR [A]
10-9
10-10
10-11
10-12
-13
10
-5
-4
-3
-2
-1
0
VR [V]
1
2
3
4
5
Figure 4-1 Reverse leakage current: IR = f(VR)
4
3.8
CL [pF]
3.6
3.4
1 MHz
3.2
3
2.8
2.6
1 GHz
-5
-4
-3
-2
-1
0
VR [V]
1
2
3
4
5
Figure 4-2 Line capacitance: CL = f(VR)
FinalData Sheet
7
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Typical Characteristics Diagrams
45
Scope: 6 GHz, 20 GS/s
VCL [V]
30
VCL-max-peak = 31 V
15
VCL-30ns-peak = 10 V
0
-15
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-3 Clamping voltage (ESD): VCL = f(t), 8 kV positive pulse
15
Scope: 6 GHz, 20 GS/s
VCL [V]
0
-15
VCL-max-peak = -31 V
-30
-45
-50
VCL-30ns-peak = -9 V
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-4 Clamping voltage (ESD): VCL = f(t), 8 kV negative pulse
FinalData Sheet
8
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ESD231-B1-W0201
Typical Characteristics Diagrams
60
Scope: 6 GHz, 20 GS/s
VCL [V]
45
VCL-max-peak = 47 V
30
VCL-30ns-peak = 13 V
15
0
-15
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-5 Clamping voltage (ESD): VCL = f(t), 15 kV positive pulse
15
Scope: 6 GHz, 20 GS/s
VCL [V]
0
-15
-30
VCL-max-peak = -47 V
VCL-30ns-peak = -12 V
-45
-60
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-6 Clamping voltage (ESD): VCL = f(t), 15 kV negative pulse
FinalData Sheet
9
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ESD231-B1-W0201
Typical Characteristics Diagrams
70
35
ESD231-B1-W0201
RDYN
60
30
50
25
40
20
30
15
20
10
10
5
0
0
-10
-5
-20
-10
-30
-15
-40
-20
Equivalent VIEC [kV]
ITLP [A]
RDYN = 0.3 Ω
RDYN = 0.3 Ω
-50
-25
-60
-30
-70
-30 -25 -20 -15 -10
-5
0
5
10
15
20
25
-35
30
VTLP [V]
Figure 4-7 Clamping voltage (TLP): ITLP = f(VTLP) [1]
FinalData Sheet
10
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ESD231-B1-W0201
Typical Characteristics Diagrams
14
12
10
8
6
4
IPP [A]
2
0
-2
-4
-6
-8
-10
-12
-14
-12
-10
-8
-6
-4
-2
0
2
VCL [V]
4
6
8
10
12
Figure 4-8 Clamping voltage (Surge): IPP = f(VCL)[1]
FinalData Sheet
11
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ESD231-B1-W0201
Typical Characteristics Diagrams
0
Insertion Loss (|S21|) [dB]
1
2
3
4
5
6
7
8
9
10
10-2
ESD231-B1-W0201
0.1
1
10
Frequency [GHz]
Figure 4-9 Insertion loss vs. frequency in a 50 Ω system
FinalData Sheet
12
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ESD231-B1-W0201
Package Information
5
Package Information
5.1
WLL-2-1
Top view
Bottom view
0.15 ±0.01
0.28 ±0.03
0.58 ±0.03
1
0.2 ±0.02
0.36
(0.16)
2
0.26 ±0.02
SG-WLL-2-1-PO V01
Figure 5-1 WLL-2-1 Package outline (dimension in mm)
0.19
0.24
Solder mask
0.19
0.57
0.14
0.62
Copper
0.19
0.27
0.24
0.32
Stencil apertures
SG-WLL-2-1-FP V01
Figure 5-2 WLL-2-1 Footprint (dimension in mm) Recommendation for Printed Circuit Board Assembly[2]
8
0.68
0.23
2
0.21
0.35
SG-WLL-2-1-TP V02
Figure 5-3 WLL-2-1 Packing (dimension in mm)
Marking on pad-side
Type code
1
1
1
Type code
1
SG-WLL-2-1-MK V03
Figure 5-4 WLL-2-1 Marking example Table 1-1 “Part Information” on Page 3
FinalData Sheet
13
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ESD231-B1-W0201
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendation for Printed Circuit Board Assembly of Infineon WLL Packages
http://www.infineon.com/dgdl/?fileId=db3a304344f7b4f9014503db540027c0 [3]
Infineon AG - Application Note AN077: Thermal Resistance Calculation
FinalData Sheet
8
Revision 1.1, 2015-10-02
ESD231-B1-W0201
Revision History: Rev. 1.0 2015-07-31
Page or Item
Subjects (major changes since previous revision)
Revision 1.1, 2015-10-02
All
Sales code change from ESD231-B1-CSP0201 to ESD231-B1-W0201
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Last Trademarks Update 2010-10-26
FinalData Sheet
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Published by Infineon Technologies AG
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