ESD128-B1-W0201 Data Sheet (801 KB, EN)

Protection Device
TVS (Transient Voltage Suppressor)
ESD128-B1-W0201
Bi-directional, 18 V (AC), 13 V (DC), 0.3 pF, 0201, RoHS and Halogen Free
compliant
ESD128-B1-W0201
Data Sheet
Revision 1.3, 2016-04-06
Final
Power Management & Multimarket
Edition 2016-04-06
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD128-B1-W0201
Product Overview
1
Product Overview
1.1
Features
•
ESD / transient protection of high speed data lines according to:
– IEC61000-4-2 (ESD): ±15 kV (air/contact discharge)
– IEC61000-4-4 (EFT): ±2 kV / ±40 A(5/50 ns)
– IEC61000-4-5 (surge): ±2 A (8/20 µs)
Bi-directional working voltage up to: VRWM = ±18 V (AC), ±13 V (DC)
Line capacitance: CL = 0.3 pF (typical) at f = 1 MHz
Clamping voltage: VCL = 32 V (typical) at ITLP = 16 A with RDYN = 0.85 Ω (typical)
Very low reverse current. IR < 1 nA (typical)
Minimized clamping overshoot due to extremely low parasitic inductance
Small form factor SMD Size 0201 and low profile (0.58 mm x 0.28 mm x 0.15 mm)
Bidirectional and symmetric I/V characteristics for optimized design and assembly
Pb-free (RoHS compliant) and halogen free package
•
•
•
•
•
•
•
•
Guidelines for optimized PCB design and assembly process available [2]
1.2
•
Application Examples
ESD Protection of RF signal lines in Near Field Communication (NFC) applications[3]
1.3
Product Description
a) Pin configuration
b) Schematic diagram
Configutation_Schematic_Diagram.vsd
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1
Part Information
Type
Package
Configuration
Marking code
ESD128-B1-W0201
WLL-2-1
1 line, bi-directional
K1)
1) The device does not have any marking or date code on the device backside. The Marking code is on pad side.
Final Data Sheet
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ESD128-B1-W0201
Maximum Ratings
2
Maximum Ratings
Table 2-1
Maximum Ratings at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
Values
Unit
2)
Reverse working voltage
VRWM
±18
±133)
V
ESD (air / contact) discharge4)
VESD
±15
kV
Peak pulse power5)
PPK
53
W
Peak pulse current
IPP
±2
A
Operating temperature range
TOP
-55 to 125
°C
Storage temperature
Tstg
-65 to 150
°C
5)
1)
2)
3)
4)
5)
Device is electrically symmetrical
For RF peak voltage (NFC)
For DC voltage
VESD according to IEC61000-4-2
Stress pulse: 8/20μs current waveform according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3
Electrical Characteristics at TA = 25 °C, unless otherwise specified
( )!! %! )*
!
+! )#! % ##%# !"!!""!" #$%"&!'!! Figure 3-1 Definitions of electrical characteristics
Final Data Sheet
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ESD128-B1-W0201
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Table 3-1
DC Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
VR = 18 V
Reverse current
IR
–
<1
30
nA
Trigger voltage
Vt1
20
22
–
V
Holding voltage
Vh
13
17
21
V
IT = 40 mA
Unit
Note / Test Condition
pF
VR = 0 V, f = 1 MHz
1) Device is electrically symmetrical
Table 3-2
AC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Line capacitance
Table 3-3
CL
Values
Min.
Typ.
Max.
0.15
0.3
0.5
–
0.3
–
VR = 0 V, f = 1 GHz
ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified1)
Parameter
Symbol
2)
Clamping voltage
VCL
3)
Clamping voltage
2)
Dynamic resistance
RDYN
Values
Min.
Typ.
Max.
–
32
–
–
18.5
–
–
0.85
–
Unit
Note / Test Condition
V
ITLP = 16 A, tp = 100 ns
IPP = 1 A, tp = 8/20 µs
Ω
tp = 100 ns
1) Device is electrically symmetrical
2) Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 0.6 ns.
3) Stress pulse: 8/20μs current waveform according to IEC61000-4-5
Final Data Sheet
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ESD128-B1-W0201
Typical Characteristics Diagrams
4
Typical Characteristics Diagrams
Typical charateristics diagrams at TA = 25 °C, unless otherwise specified
-3
10
10-4
10-5
10-6
-7
10
-8
IR [A]
10
-9
10
10-10
10-11
10-12
-13
10
-14
10
-18
-15
-12
-9
-6
-3
0
3
VR [V]
6
9
12
15
18
12
15
18
Figure 4-1 Reverse leakage current IR = f(VR)
1
0.9
0.8
CL [pF]
0.7
0.6
0.5
0.4
1 MHz
0.3
1 GHz
0.2
0.1
0
-18
-15
-12
-9
-6
-3
0
VR [V]
3
6
9
Figure 4-2 Line capacitance CL = f(VR), f = 1 MHz
Final Data Sheet
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ESD128-B1-W0201
Typical Characteristics Diagrams
140
Scope: 6 GHz, 20 GS/s
120
100
VCL [V]
80
VCL-max-peak = 122 V
60
VCL-30ns-peak = 26 V
40
20
0
-20
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-3 Clamping voltage (ESD): VCL = f(t), 8 kV positive pulse
Scope: 6 GHz, 20 GS/s
0
VCL [V]
-25
-50
-75
VCL-max-peak = -124 V
-100
VCL-30ns-peak = -26 V
-125
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-4 Clamping voltage (ESD): VCL = f(t), 8 kV negative pulse
Final Data Sheet
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ESD128-B1-W0201
Typical Characteristics Diagrams
180
Scope: 6 GHz, 20 GS/s
160
140
VCL-max-peak = 157 V
VCL [V]
120
VCL-30ns-peak = 46 V
100
80
60
40
20
0
-20
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-5 Clamping voltage (ESD): VCL = f(t), 15 kV positive pulse
20
Scope: 6 GHz, 20 GS/s
0
-20
VCL [V]
-40
-60
-80
-100
VCL-max-peak = -150 V
-120
VCL-30ns-peak = -46 V
-140
-160
-180
-50
0
50
100
150
200
tp [ns]
250
300
350
400
450
Figure 4-6 Clamping voltage (ESD): VCL = f(t), 15 kV negative pulse
Final Data Sheet
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Typical Characteristics Diagrams
10
ESD128-B1-W0201
RDYN
RDYN = 0.85 Ω
15
ITLP [A]
10
7.5
5
5
2.5
0
0
-5
-2.5
-10
-15
Equivalent VIEC [kV]
20
-5
RDYN = 0.85 Ω
-7.5
-20
-10
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40
VTLP [V]
Figure 4-7 Clamping voltage (TLP): ITLP = f(VTLP) [1]
Final Data Sheet
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ESD128-B1-W0201
Typical Characteristics Diagrams
2.5
2
1.5
1
IPP [A]
0.5
0
-0.5
-1
-1.5
-2
-2.5
-25
-20
-15
-10
-5
0
VCL [V]
5
10
15
20
25
Figure 4-8 Clamping voltage(Surge): IPP = f(VCL) [1]
Final Data Sheet
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ESD128-B1-W0201
Typical Characteristics Diagrams
0
Insertion Loss (|S21|) [dB]
1
2
3
4
5
6
7
8
9
10
10-2
ESD128-B1-W0201
0.1
1
Frequency [GHz]
10
Figure 4-9 Insertion loss vs. frequency in a 50 Ω system
Final Data Sheet
11
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ESD128-B1-W0201
Application Information
Application Information
Mobile phone
Main PCB / Top shell
differential antenna
Interconnection
top/bottom shell
“external pads”
RF=13.56MHz
signal vs. GND<+-18Vp
+Vsignal vs. -Vsignal <36V!!!
TX+
NFC Module
TX/RX section
Bottom shell
loop+
TX-
EMI
- LP filter
Antenna
matching
GND
RX
Loopantenna
~1µH
5
GND
loop-
Caps should be high
voltage type to be save
regards the residual
ESD peak
Mobile phone
single ended antenna
Interconnection
top/bottom shell
“external pads”
Main PCB / Top shell
Bottom shell
RF=13.56MHz
signal vs. GND<+-18Vp
NFC Module
TX/RX section
TX+
loop
TXGND
RX
EMI- LP filter
Antenna
matching
GND
Caps should be high
voltage type to be save
regards the residual
ESD peak
ESD 18V_application example.vsd
Figure 5-1 Bi-directional ESD / Transient protection for NFC Frontend [3]
Final Data Sheet
12
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ESD128-B1-W0201
Package Information
6
Package Information
6.1
WLL-2-1
Top view
Bottom view
0.15 ±0.01
0.28 ±0.03
0.58 ±0.03
1
0.2 ±0.02
0.36
(0.16)
2
0.26 ±0.02
SG-WLL-2-1-PO V01
Figure 6-1 WLL-2-1 Package outline (dimension in mm)
0.19
0.24
Solder mask
0.19
0.57
0.14
0.62
Copper
0.19
0.27
0.24
0.32
Stencil apertures
SG-WLL-2-1-FP V01
Figure 6-2 WLL-2-1 Footprint (see:Recommendation for Printed Circuit Board Assembly[2])
8
0.68
0.23
2
0.21
0.35
SG-WLL-2-1-TP V02
Figure 6-3 WLL-2-1 Packing (dimension in mm)
Marking on pad-side
Type code
1
1
1
Type code
1
SG-WLL-2-1-MK V03
Figure 6-4 WLL-2-1 Marking example Table 1-1 “Part Information” on Page 3
Final Data Sheet
13
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ESD128-B1-W0201
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendation for Printed Circuit Board Assembly of Infineon WLL Packages
http://www.infineon.com/dgdl/?fileId=db3a304344f7b4f9014503db540027c0 [3]
Infineon AG - Application Note AN244: Tailored ESD Protection for the NFC Frontend
Final Data Sheet
8
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ESD128-B1-W0201
Revision History: Rev. 1.2, 2015-09-29
Page or Item
Subjects (major changes since previous revision)
Revision 1.3, 2016-04-06
All
New layout
Trademarks of Infineon Technologies AG
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Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™
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RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.
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UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™
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Last Trademarks Update 2010-10-26
Final Data Sheet
9
Revision 1.3, 2016-04-06
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Published by Infineon Technologies AG